1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 34 #include <linux/vga_switcheroo.h> 35 #include <linux/slab.h> 36 #include <linux/pm_runtime.h> 37 #include "amdgpu_amdkfd.h" 38 39 #if defined(CONFIG_VGA_SWITCHEROO) 40 bool amdgpu_has_atpx(void); 41 #else 42 static inline bool amdgpu_has_atpx(void) { return false; } 43 #endif 44 45 /** 46 * amdgpu_driver_unload_kms - Main unload function for KMS. 47 * 48 * @dev: drm dev pointer 49 * 50 * This is the main unload function for KMS (all asics). 51 * Returns 0 on success. 52 */ 53 int amdgpu_driver_unload_kms(struct drm_device *dev) 54 { 55 struct amdgpu_device *adev = dev->dev_private; 56 57 if (adev == NULL) 58 return 0; 59 60 if (adev->rmmio == NULL) 61 goto done_free; 62 63 if (amdgpu_device_is_px(dev)) { 64 pm_runtime_get_sync(dev->dev); 65 pm_runtime_forbid(dev->dev); 66 } 67 68 amdgpu_amdkfd_device_fini(adev); 69 70 amdgpu_acpi_fini(adev); 71 72 amdgpu_device_fini(adev); 73 74 done_free: 75 kfree(adev); 76 dev->dev_private = NULL; 77 return 0; 78 } 79 80 /** 81 * amdgpu_driver_load_kms - Main load function for KMS. 82 * 83 * @dev: drm dev pointer 84 * @flags: device flags 85 * 86 * This is the main load function for KMS (all asics). 87 * Returns 0 on success, error on failure. 88 */ 89 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 90 { 91 struct amdgpu_device *adev; 92 int r, acpi_status; 93 94 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 95 if (adev == NULL) { 96 return -ENOMEM; 97 } 98 dev->dev_private = (void *)adev; 99 100 if ((amdgpu_runtime_pm != 0) && 101 amdgpu_has_atpx() && 102 (amdgpu_is_atpx_hybrid() || 103 amdgpu_has_atpx_dgpu_power_cntl()) && 104 ((flags & AMD_IS_APU) == 0)) 105 flags |= AMD_IS_PX; 106 107 /* amdgpu_device_init should report only fatal error 108 * like memory allocation failure or iomapping failure, 109 * or memory manager initialization failure, it must 110 * properly initialize the GPU MC controller and permit 111 * VRAM allocation 112 */ 113 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 114 if (r) { 115 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 116 goto out; 117 } 118 119 /* Call ACPI methods: require modeset init 120 * but failure is not fatal 121 */ 122 if (!r) { 123 acpi_status = amdgpu_acpi_init(adev); 124 if (acpi_status) 125 dev_dbg(&dev->pdev->dev, 126 "Error during ACPI methods call\n"); 127 } 128 129 amdgpu_amdkfd_load_interface(adev); 130 amdgpu_amdkfd_device_probe(adev); 131 amdgpu_amdkfd_device_init(adev); 132 133 if (amdgpu_device_is_px(dev)) { 134 pm_runtime_use_autosuspend(dev->dev); 135 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 136 pm_runtime_set_active(dev->dev); 137 pm_runtime_allow(dev->dev); 138 pm_runtime_mark_last_busy(dev->dev); 139 pm_runtime_put_autosuspend(dev->dev); 140 } 141 142 out: 143 if (r) { 144 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 145 if (adev->rmmio && amdgpu_device_is_px(dev)) 146 pm_runtime_put_noidle(dev->dev); 147 amdgpu_driver_unload_kms(dev); 148 } 149 150 return r; 151 } 152 153 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 154 struct drm_amdgpu_query_fw *query_fw, 155 struct amdgpu_device *adev) 156 { 157 switch (query_fw->fw_type) { 158 case AMDGPU_INFO_FW_VCE: 159 fw_info->ver = adev->vce.fw_version; 160 fw_info->feature = adev->vce.fb_version; 161 break; 162 case AMDGPU_INFO_FW_UVD: 163 fw_info->ver = adev->uvd.fw_version; 164 fw_info->feature = 0; 165 break; 166 case AMDGPU_INFO_FW_GMC: 167 fw_info->ver = adev->mc.fw_version; 168 fw_info->feature = 0; 169 break; 170 case AMDGPU_INFO_FW_GFX_ME: 171 fw_info->ver = adev->gfx.me_fw_version; 172 fw_info->feature = adev->gfx.me_feature_version; 173 break; 174 case AMDGPU_INFO_FW_GFX_PFP: 175 fw_info->ver = adev->gfx.pfp_fw_version; 176 fw_info->feature = adev->gfx.pfp_feature_version; 177 break; 178 case AMDGPU_INFO_FW_GFX_CE: 179 fw_info->ver = adev->gfx.ce_fw_version; 180 fw_info->feature = adev->gfx.ce_feature_version; 181 break; 182 case AMDGPU_INFO_FW_GFX_RLC: 183 fw_info->ver = adev->gfx.rlc_fw_version; 184 fw_info->feature = adev->gfx.rlc_feature_version; 185 break; 186 case AMDGPU_INFO_FW_GFX_MEC: 187 if (query_fw->index == 0) { 188 fw_info->ver = adev->gfx.mec_fw_version; 189 fw_info->feature = adev->gfx.mec_feature_version; 190 } else if (query_fw->index == 1) { 191 fw_info->ver = adev->gfx.mec2_fw_version; 192 fw_info->feature = adev->gfx.mec2_feature_version; 193 } else 194 return -EINVAL; 195 break; 196 case AMDGPU_INFO_FW_SMC: 197 fw_info->ver = adev->pm.fw_version; 198 fw_info->feature = 0; 199 break; 200 case AMDGPU_INFO_FW_SDMA: 201 if (query_fw->index >= adev->sdma.num_instances) 202 return -EINVAL; 203 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 204 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 205 break; 206 default: 207 return -EINVAL; 208 } 209 return 0; 210 } 211 212 /* 213 * Userspace get information ioctl 214 */ 215 /** 216 * amdgpu_info_ioctl - answer a device specific request. 217 * 218 * @adev: amdgpu device pointer 219 * @data: request object 220 * @filp: drm filp 221 * 222 * This function is used to pass device specific parameters to the userspace 223 * drivers. Examples include: pci device id, pipeline parms, tiling params, 224 * etc. (all asics). 225 * Returns 0 on success, -EINVAL on failure. 226 */ 227 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 228 { 229 struct amdgpu_device *adev = dev->dev_private; 230 struct drm_amdgpu_info *info = data; 231 struct amdgpu_mode_info *minfo = &adev->mode_info; 232 void __user *out = (void __user *)(long)info->return_pointer; 233 uint32_t size = info->return_size; 234 struct drm_crtc *crtc; 235 uint32_t ui32 = 0; 236 uint64_t ui64 = 0; 237 int i, found; 238 239 if (!info->return_size || !info->return_pointer) 240 return -EINVAL; 241 242 switch (info->query) { 243 case AMDGPU_INFO_ACCEL_WORKING: 244 ui32 = adev->accel_working; 245 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 246 case AMDGPU_INFO_CRTC_FROM_ID: 247 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 248 crtc = (struct drm_crtc *)minfo->crtcs[i]; 249 if (crtc && crtc->base.id == info->mode_crtc.id) { 250 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 251 ui32 = amdgpu_crtc->crtc_id; 252 found = 1; 253 break; 254 } 255 } 256 if (!found) { 257 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 258 return -EINVAL; 259 } 260 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 261 case AMDGPU_INFO_HW_IP_INFO: { 262 struct drm_amdgpu_info_hw_ip ip = {}; 263 enum amd_ip_block_type type; 264 uint32_t ring_mask = 0; 265 uint32_t ib_start_alignment = 0; 266 uint32_t ib_size_alignment = 0; 267 268 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 269 return -EINVAL; 270 271 switch (info->query_hw_ip.type) { 272 case AMDGPU_HW_IP_GFX: 273 type = AMD_IP_BLOCK_TYPE_GFX; 274 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 275 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 276 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 277 ib_size_alignment = 8; 278 break; 279 case AMDGPU_HW_IP_COMPUTE: 280 type = AMD_IP_BLOCK_TYPE_GFX; 281 for (i = 0; i < adev->gfx.num_compute_rings; i++) 282 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 283 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 284 ib_size_alignment = 8; 285 break; 286 case AMDGPU_HW_IP_DMA: 287 type = AMD_IP_BLOCK_TYPE_SDMA; 288 for (i = 0; i < adev->sdma.num_instances; i++) 289 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 290 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 291 ib_size_alignment = 1; 292 break; 293 case AMDGPU_HW_IP_UVD: 294 type = AMD_IP_BLOCK_TYPE_UVD; 295 ring_mask = adev->uvd.ring.ready ? 1 : 0; 296 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 297 ib_size_alignment = 16; 298 break; 299 case AMDGPU_HW_IP_VCE: 300 type = AMD_IP_BLOCK_TYPE_VCE; 301 for (i = 0; i < adev->vce.num_rings; i++) 302 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 303 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 304 ib_size_alignment = 1; 305 break; 306 default: 307 return -EINVAL; 308 } 309 310 for (i = 0; i < adev->num_ip_blocks; i++) { 311 if (adev->ip_blocks[i].type == type && 312 adev->ip_block_status[i].valid) { 313 ip.hw_ip_version_major = adev->ip_blocks[i].major; 314 ip.hw_ip_version_minor = adev->ip_blocks[i].minor; 315 ip.capabilities_flags = 0; 316 ip.available_rings = ring_mask; 317 ip.ib_start_alignment = ib_start_alignment; 318 ip.ib_size_alignment = ib_size_alignment; 319 break; 320 } 321 } 322 return copy_to_user(out, &ip, 323 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 324 } 325 case AMDGPU_INFO_HW_IP_COUNT: { 326 enum amd_ip_block_type type; 327 uint32_t count = 0; 328 329 switch (info->query_hw_ip.type) { 330 case AMDGPU_HW_IP_GFX: 331 type = AMD_IP_BLOCK_TYPE_GFX; 332 break; 333 case AMDGPU_HW_IP_COMPUTE: 334 type = AMD_IP_BLOCK_TYPE_GFX; 335 break; 336 case AMDGPU_HW_IP_DMA: 337 type = AMD_IP_BLOCK_TYPE_SDMA; 338 break; 339 case AMDGPU_HW_IP_UVD: 340 type = AMD_IP_BLOCK_TYPE_UVD; 341 break; 342 case AMDGPU_HW_IP_VCE: 343 type = AMD_IP_BLOCK_TYPE_VCE; 344 break; 345 default: 346 return -EINVAL; 347 } 348 349 for (i = 0; i < adev->num_ip_blocks; i++) 350 if (adev->ip_blocks[i].type == type && 351 adev->ip_block_status[i].valid && 352 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 353 count++; 354 355 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 356 } 357 case AMDGPU_INFO_TIMESTAMP: 358 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 359 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 360 case AMDGPU_INFO_FW_VERSION: { 361 struct drm_amdgpu_info_firmware fw_info; 362 int ret; 363 364 /* We only support one instance of each IP block right now. */ 365 if (info->query_fw.ip_instance != 0) 366 return -EINVAL; 367 368 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 369 if (ret) 370 return ret; 371 372 return copy_to_user(out, &fw_info, 373 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 374 } 375 case AMDGPU_INFO_NUM_BYTES_MOVED: 376 ui64 = atomic64_read(&adev->num_bytes_moved); 377 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 378 case AMDGPU_INFO_NUM_EVICTIONS: 379 ui64 = atomic64_read(&adev->num_evictions); 380 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 381 case AMDGPU_INFO_VRAM_USAGE: 382 ui64 = atomic64_read(&adev->vram_usage); 383 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 384 case AMDGPU_INFO_VIS_VRAM_USAGE: 385 ui64 = atomic64_read(&adev->vram_vis_usage); 386 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 387 case AMDGPU_INFO_GTT_USAGE: 388 ui64 = atomic64_read(&adev->gtt_usage); 389 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 390 case AMDGPU_INFO_GDS_CONFIG: { 391 struct drm_amdgpu_info_gds gds_info; 392 393 memset(&gds_info, 0, sizeof(gds_info)); 394 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 395 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 396 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 397 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 398 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 399 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 400 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 401 return copy_to_user(out, &gds_info, 402 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 403 } 404 case AMDGPU_INFO_VRAM_GTT: { 405 struct drm_amdgpu_info_vram_gtt vram_gtt; 406 407 vram_gtt.vram_size = adev->mc.real_vram_size; 408 vram_gtt.vram_size -= adev->vram_pin_size; 409 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 410 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 411 vram_gtt.gtt_size = adev->mc.gtt_size; 412 vram_gtt.gtt_size -= adev->gart_pin_size; 413 return copy_to_user(out, &vram_gtt, 414 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 415 } 416 case AMDGPU_INFO_READ_MMR_REG: { 417 unsigned n, alloc_size; 418 uint32_t *regs; 419 unsigned se_num = (info->read_mmr_reg.instance >> 420 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 421 AMDGPU_INFO_MMR_SE_INDEX_MASK; 422 unsigned sh_num = (info->read_mmr_reg.instance >> 423 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 424 AMDGPU_INFO_MMR_SH_INDEX_MASK; 425 426 /* set full masks if the userspace set all bits 427 * in the bitfields */ 428 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 429 se_num = 0xffffffff; 430 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 431 sh_num = 0xffffffff; 432 433 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 434 if (!regs) 435 return -ENOMEM; 436 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 437 438 for (i = 0; i < info->read_mmr_reg.count; i++) 439 if (amdgpu_asic_read_register(adev, se_num, sh_num, 440 info->read_mmr_reg.dword_offset + i, 441 ®s[i])) { 442 DRM_DEBUG_KMS("unallowed offset %#x\n", 443 info->read_mmr_reg.dword_offset + i); 444 kfree(regs); 445 return -EFAULT; 446 } 447 n = copy_to_user(out, regs, min(size, alloc_size)); 448 kfree(regs); 449 return n ? -EFAULT : 0; 450 } 451 case AMDGPU_INFO_DEV_INFO: { 452 struct drm_amdgpu_info_device dev_info = {}; 453 454 dev_info.device_id = dev->pdev->device; 455 dev_info.chip_rev = adev->rev_id; 456 dev_info.external_rev = adev->external_rev_id; 457 dev_info.pci_rev = dev->pdev->revision; 458 dev_info.family = adev->family; 459 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 460 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 461 /* return all clocks in KHz */ 462 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 463 if (adev->pm.dpm_enabled) { 464 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 465 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 466 } else { 467 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 468 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 469 } 470 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 471 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 472 adev->gfx.config.max_shader_engines; 473 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 474 dev_info._pad = 0; 475 dev_info.ids_flags = 0; 476 if (adev->flags & AMD_IS_APU) 477 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 478 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 479 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 480 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 481 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 482 AMDGPU_GPU_PAGE_SIZE; 483 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 484 485 dev_info.cu_active_number = adev->gfx.cu_info.number; 486 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 487 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 488 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 489 sizeof(adev->gfx.cu_info.bitmap)); 490 dev_info.vram_type = adev->mc.vram_type; 491 dev_info.vram_bit_width = adev->mc.vram_width; 492 dev_info.vce_harvest_config = adev->vce.harvest_config; 493 494 return copy_to_user(out, &dev_info, 495 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 496 } 497 default: 498 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 499 return -EINVAL; 500 } 501 return 0; 502 } 503 504 505 /* 506 * Outdated mess for old drm with Xorg being in charge (void function now). 507 */ 508 /** 509 * amdgpu_driver_lastclose_kms - drm callback for last close 510 * 511 * @dev: drm dev pointer 512 * 513 * Switch vga_switcheroo state after last close (all asics). 514 */ 515 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 516 { 517 struct amdgpu_device *adev = dev->dev_private; 518 519 amdgpu_fbdev_restore_mode(adev); 520 vga_switcheroo_process_delayed_switch(); 521 } 522 523 /** 524 * amdgpu_driver_open_kms - drm callback for open 525 * 526 * @dev: drm dev pointer 527 * @file_priv: drm file 528 * 529 * On device open, init vm on cayman+ (all asics). 530 * Returns 0 on success, error on failure. 531 */ 532 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 533 { 534 struct amdgpu_device *adev = dev->dev_private; 535 struct amdgpu_fpriv *fpriv; 536 int r; 537 538 file_priv->driver_priv = NULL; 539 540 r = pm_runtime_get_sync(dev->dev); 541 if (r < 0) 542 return r; 543 544 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 545 if (unlikely(!fpriv)) { 546 r = -ENOMEM; 547 goto out_suspend; 548 } 549 550 r = amdgpu_vm_init(adev, &fpriv->vm); 551 if (r) { 552 kfree(fpriv); 553 goto out_suspend; 554 } 555 556 mutex_init(&fpriv->bo_list_lock); 557 idr_init(&fpriv->bo_list_handles); 558 559 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 560 561 file_priv->driver_priv = fpriv; 562 563 out_suspend: 564 pm_runtime_mark_last_busy(dev->dev); 565 pm_runtime_put_autosuspend(dev->dev); 566 567 return r; 568 } 569 570 /** 571 * amdgpu_driver_postclose_kms - drm callback for post close 572 * 573 * @dev: drm dev pointer 574 * @file_priv: drm file 575 * 576 * On device post close, tear down vm on cayman+ (all asics). 577 */ 578 void amdgpu_driver_postclose_kms(struct drm_device *dev, 579 struct drm_file *file_priv) 580 { 581 struct amdgpu_device *adev = dev->dev_private; 582 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 583 struct amdgpu_bo_list *list; 584 int handle; 585 586 if (!fpriv) 587 return; 588 589 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 590 591 amdgpu_uvd_free_handles(adev, file_priv); 592 amdgpu_vce_free_handles(adev, file_priv); 593 594 amdgpu_vm_fini(adev, &fpriv->vm); 595 596 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 597 amdgpu_bo_list_free(list); 598 599 idr_destroy(&fpriv->bo_list_handles); 600 mutex_destroy(&fpriv->bo_list_lock); 601 602 kfree(fpriv); 603 file_priv->driver_priv = NULL; 604 605 pm_runtime_mark_last_busy(dev->dev); 606 pm_runtime_put_autosuspend(dev->dev); 607 } 608 609 /** 610 * amdgpu_driver_preclose_kms - drm callback for pre close 611 * 612 * @dev: drm dev pointer 613 * @file_priv: drm file 614 * 615 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 616 * (all asics). 617 */ 618 void amdgpu_driver_preclose_kms(struct drm_device *dev, 619 struct drm_file *file_priv) 620 { 621 pm_runtime_get_sync(dev->dev); 622 } 623 624 /* 625 * VBlank related functions. 626 */ 627 /** 628 * amdgpu_get_vblank_counter_kms - get frame count 629 * 630 * @dev: drm dev pointer 631 * @pipe: crtc to get the frame count from 632 * 633 * Gets the frame count on the requested crtc (all asics). 634 * Returns frame count on success, -EINVAL on failure. 635 */ 636 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 637 { 638 struct amdgpu_device *adev = dev->dev_private; 639 int vpos, hpos, stat; 640 u32 count; 641 642 if (pipe >= adev->mode_info.num_crtc) { 643 DRM_ERROR("Invalid crtc %u\n", pipe); 644 return -EINVAL; 645 } 646 647 /* The hw increments its frame counter at start of vsync, not at start 648 * of vblank, as is required by DRM core vblank counter handling. 649 * Cook the hw count here to make it appear to the caller as if it 650 * incremented at start of vblank. We measure distance to start of 651 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 652 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 653 * result by 1 to give the proper appearance to caller. 654 */ 655 if (adev->mode_info.crtcs[pipe]) { 656 /* Repeat readout if needed to provide stable result if 657 * we cross start of vsync during the queries. 658 */ 659 do { 660 count = amdgpu_display_vblank_get_counter(adev, pipe); 661 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 662 * distance to start of vblank, instead of regular 663 * vertical scanout pos. 664 */ 665 stat = amdgpu_get_crtc_scanoutpos( 666 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 667 &vpos, &hpos, NULL, NULL, 668 &adev->mode_info.crtcs[pipe]->base.hwmode); 669 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 670 671 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 672 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 673 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 674 } else { 675 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 676 pipe, vpos); 677 678 /* Bump counter if we are at >= leading edge of vblank, 679 * but before vsync where vpos would turn negative and 680 * the hw counter really increments. 681 */ 682 if (vpos >= 0) 683 count++; 684 } 685 } else { 686 /* Fallback to use value as is. */ 687 count = amdgpu_display_vblank_get_counter(adev, pipe); 688 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 689 } 690 691 return count; 692 } 693 694 /** 695 * amdgpu_enable_vblank_kms - enable vblank interrupt 696 * 697 * @dev: drm dev pointer 698 * @pipe: crtc to enable vblank interrupt for 699 * 700 * Enable the interrupt on the requested crtc (all asics). 701 * Returns 0 on success, -EINVAL on failure. 702 */ 703 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 704 { 705 struct amdgpu_device *adev = dev->dev_private; 706 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 707 708 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 709 } 710 711 /** 712 * amdgpu_disable_vblank_kms - disable vblank interrupt 713 * 714 * @dev: drm dev pointer 715 * @pipe: crtc to disable vblank interrupt for 716 * 717 * Disable the interrupt on the requested crtc (all asics). 718 */ 719 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 720 { 721 struct amdgpu_device *adev = dev->dev_private; 722 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 723 724 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 725 } 726 727 /** 728 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp 729 * 730 * @dev: drm dev pointer 731 * @crtc: crtc to get the timestamp for 732 * @max_error: max error 733 * @vblank_time: time value 734 * @flags: flags passed to the driver 735 * 736 * Gets the timestamp on the requested crtc based on the 737 * scanout position. (all asics). 738 * Returns postive status flags on success, negative error on failure. 739 */ 740 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 741 int *max_error, 742 struct timeval *vblank_time, 743 unsigned flags) 744 { 745 struct drm_crtc *crtc; 746 struct amdgpu_device *adev = dev->dev_private; 747 748 if (pipe >= dev->num_crtcs) { 749 DRM_ERROR("Invalid crtc %u\n", pipe); 750 return -EINVAL; 751 } 752 753 /* Get associated drm_crtc: */ 754 crtc = &adev->mode_info.crtcs[pipe]->base; 755 if (!crtc) { 756 /* This can occur on driver load if some component fails to 757 * initialize completely and driver is unloaded */ 758 DRM_ERROR("Uninitialized crtc %d\n", pipe); 759 return -EINVAL; 760 } 761 762 /* Helper routine in DRM core does all the work: */ 763 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 764 vblank_time, flags, 765 &crtc->hwmode); 766 } 767 768 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 769 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 770 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 771 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 772 /* KMS */ 773 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 774 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 775 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 776 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 777 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 778 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 779 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 780 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 781 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 782 }; 783 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 784 785 /* 786 * Debugfs info 787 */ 788 #if defined(CONFIG_DEBUG_FS) 789 790 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 791 { 792 struct drm_info_node *node = (struct drm_info_node *) m->private; 793 struct drm_device *dev = node->minor->dev; 794 struct amdgpu_device *adev = dev->dev_private; 795 struct drm_amdgpu_info_firmware fw_info; 796 struct drm_amdgpu_query_fw query_fw; 797 int ret, i; 798 799 /* VCE */ 800 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 801 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 802 if (ret) 803 return ret; 804 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 805 fw_info.feature, fw_info.ver); 806 807 /* UVD */ 808 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 809 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 810 if (ret) 811 return ret; 812 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 813 fw_info.feature, fw_info.ver); 814 815 /* GMC */ 816 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 817 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 818 if (ret) 819 return ret; 820 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 821 fw_info.feature, fw_info.ver); 822 823 /* ME */ 824 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 825 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 826 if (ret) 827 return ret; 828 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 829 fw_info.feature, fw_info.ver); 830 831 /* PFP */ 832 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 833 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 834 if (ret) 835 return ret; 836 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 837 fw_info.feature, fw_info.ver); 838 839 /* CE */ 840 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 841 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 842 if (ret) 843 return ret; 844 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 845 fw_info.feature, fw_info.ver); 846 847 /* RLC */ 848 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 849 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 850 if (ret) 851 return ret; 852 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 853 fw_info.feature, fw_info.ver); 854 855 /* MEC */ 856 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 857 query_fw.index = 0; 858 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 859 if (ret) 860 return ret; 861 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 862 fw_info.feature, fw_info.ver); 863 864 /* MEC2 */ 865 if (adev->asic_type == CHIP_KAVERI || 866 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 867 query_fw.index = 1; 868 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 869 if (ret) 870 return ret; 871 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 872 fw_info.feature, fw_info.ver); 873 } 874 875 /* SMC */ 876 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 877 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 878 if (ret) 879 return ret; 880 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 881 fw_info.feature, fw_info.ver); 882 883 /* SDMA */ 884 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 885 for (i = 0; i < adev->sdma.num_instances; i++) { 886 query_fw.index = i; 887 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 888 if (ret) 889 return ret; 890 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 891 i, fw_info.feature, fw_info.ver); 892 } 893 894 return 0; 895 } 896 897 static const struct drm_info_list amdgpu_firmware_info_list[] = { 898 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 899 }; 900 #endif 901 902 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 903 { 904 #if defined(CONFIG_DEBUG_FS) 905 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 906 ARRAY_SIZE(amdgpu_firmware_info_list)); 907 #else 908 return 0; 909 #endif 910 } 911