1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 91 DRM_WARN("smart shift update failed\n"); 92 93 amdgpu_acpi_fini(adev); 94 amdgpu_device_fini_hw(adev); 95 } 96 97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 98 { 99 struct amdgpu_gpu_instance *gpu_instance; 100 101 mutex_lock(&mgpu_info.mutex); 102 103 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 104 DRM_ERROR("Cannot register more gpu instance\n"); 105 mutex_unlock(&mgpu_info.mutex); 106 return; 107 } 108 109 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 110 gpu_instance->adev = adev; 111 gpu_instance->mgpu_fan_enabled = 0; 112 113 mgpu_info.num_gpu++; 114 if (adev->flags & AMD_IS_APU) 115 mgpu_info.num_apu++; 116 else 117 mgpu_info.num_dgpu++; 118 119 mutex_unlock(&mgpu_info.mutex); 120 } 121 122 /** 123 * amdgpu_driver_load_kms - Main load function for KMS. 124 * 125 * @adev: pointer to struct amdgpu_device 126 * @flags: device flags 127 * 128 * This is the main load function for KMS (all asics). 129 * Returns 0 on success, error on failure. 130 */ 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 132 { 133 struct drm_device *dev; 134 int r, acpi_status; 135 136 dev = adev_to_drm(adev); 137 138 /* amdgpu_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = amdgpu_device_init(adev, flags); 145 if (r) { 146 dev_err(dev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 if (amdgpu_device_supports_px(dev) && 151 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 152 adev->runpm = true; 153 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 154 } else if (amdgpu_device_supports_boco(dev) && 155 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 156 adev->runpm = true; 157 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 158 } else if (amdgpu_device_supports_baco(dev) && 159 (amdgpu_runtime_pm != 0)) { 160 switch (adev->asic_type) { 161 case CHIP_VEGA20: 162 case CHIP_ARCTURUS: 163 /* enable runpm if runpm=1 */ 164 if (amdgpu_runtime_pm > 0) 165 adev->runpm = true; 166 break; 167 case CHIP_VEGA10: 168 /* turn runpm on if noretry=0 */ 169 if (!adev->gmc.noretry) 170 adev->runpm = true; 171 break; 172 default: 173 /* enable runpm on CI+ */ 174 adev->runpm = true; 175 break; 176 } 177 if (adev->runpm) 178 dev_info(adev->dev, "Using BACO for runtime pm\n"); 179 } 180 181 /* Call ACPI methods: require modeset init 182 * but failure is not fatal 183 */ 184 185 acpi_status = amdgpu_acpi_init(adev); 186 if (acpi_status) 187 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 188 189 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 190 DRM_WARN("smart shift update failed\n"); 191 192 out: 193 if (r) 194 amdgpu_driver_unload_kms(dev); 195 196 return r; 197 } 198 199 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 200 struct drm_amdgpu_query_fw *query_fw, 201 struct amdgpu_device *adev) 202 { 203 switch (query_fw->fw_type) { 204 case AMDGPU_INFO_FW_VCE: 205 fw_info->ver = adev->vce.fw_version; 206 fw_info->feature = adev->vce.fb_version; 207 break; 208 case AMDGPU_INFO_FW_UVD: 209 fw_info->ver = adev->uvd.fw_version; 210 fw_info->feature = 0; 211 break; 212 case AMDGPU_INFO_FW_VCN: 213 fw_info->ver = adev->vcn.fw_version; 214 fw_info->feature = 0; 215 break; 216 case AMDGPU_INFO_FW_GMC: 217 fw_info->ver = adev->gmc.fw_version; 218 fw_info->feature = 0; 219 break; 220 case AMDGPU_INFO_FW_GFX_ME: 221 fw_info->ver = adev->gfx.me_fw_version; 222 fw_info->feature = adev->gfx.me_feature_version; 223 break; 224 case AMDGPU_INFO_FW_GFX_PFP: 225 fw_info->ver = adev->gfx.pfp_fw_version; 226 fw_info->feature = adev->gfx.pfp_feature_version; 227 break; 228 case AMDGPU_INFO_FW_GFX_CE: 229 fw_info->ver = adev->gfx.ce_fw_version; 230 fw_info->feature = adev->gfx.ce_feature_version; 231 break; 232 case AMDGPU_INFO_FW_GFX_RLC: 233 fw_info->ver = adev->gfx.rlc_fw_version; 234 fw_info->feature = adev->gfx.rlc_feature_version; 235 break; 236 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 237 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 238 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 239 break; 240 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 241 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 242 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 243 break; 244 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 245 fw_info->ver = adev->gfx.rlc_srls_fw_version; 246 fw_info->feature = adev->gfx.rlc_srls_feature_version; 247 break; 248 case AMDGPU_INFO_FW_GFX_MEC: 249 if (query_fw->index == 0) { 250 fw_info->ver = adev->gfx.mec_fw_version; 251 fw_info->feature = adev->gfx.mec_feature_version; 252 } else if (query_fw->index == 1) { 253 fw_info->ver = adev->gfx.mec2_fw_version; 254 fw_info->feature = adev->gfx.mec2_feature_version; 255 } else 256 return -EINVAL; 257 break; 258 case AMDGPU_INFO_FW_SMC: 259 fw_info->ver = adev->pm.fw_version; 260 fw_info->feature = 0; 261 break; 262 case AMDGPU_INFO_FW_TA: 263 switch (query_fw->index) { 264 case TA_FW_TYPE_PSP_XGMI: 265 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 266 fw_info->feature = adev->psp.xgmi_context.context 267 .bin_desc.feature_version; 268 break; 269 case TA_FW_TYPE_PSP_RAS: 270 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 271 fw_info->feature = adev->psp.ras_context.context 272 .bin_desc.feature_version; 273 break; 274 case TA_FW_TYPE_PSP_HDCP: 275 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 276 fw_info->feature = adev->psp.hdcp_context.context 277 .bin_desc.feature_version; 278 break; 279 case TA_FW_TYPE_PSP_DTM: 280 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 281 fw_info->feature = adev->psp.dtm_context.context 282 .bin_desc.feature_version; 283 break; 284 case TA_FW_TYPE_PSP_RAP: 285 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 286 fw_info->feature = adev->psp.rap_context.context 287 .bin_desc.feature_version; 288 break; 289 case TA_FW_TYPE_PSP_SECUREDISPLAY: 290 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 291 fw_info->feature = 292 adev->psp.securedisplay_context.context.bin_desc 293 .feature_version; 294 break; 295 default: 296 return -EINVAL; 297 } 298 break; 299 case AMDGPU_INFO_FW_SDMA: 300 if (query_fw->index >= adev->sdma.num_instances) 301 return -EINVAL; 302 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 303 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 304 break; 305 case AMDGPU_INFO_FW_SOS: 306 fw_info->ver = adev->psp.sos.fw_version; 307 fw_info->feature = adev->psp.sos.feature_version; 308 break; 309 case AMDGPU_INFO_FW_ASD: 310 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 311 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 312 break; 313 case AMDGPU_INFO_FW_DMCU: 314 fw_info->ver = adev->dm.dmcu_fw_version; 315 fw_info->feature = 0; 316 break; 317 case AMDGPU_INFO_FW_DMCUB: 318 fw_info->ver = adev->dm.dmcub_fw_version; 319 fw_info->feature = 0; 320 break; 321 case AMDGPU_INFO_FW_TOC: 322 fw_info->ver = adev->psp.toc.fw_version; 323 fw_info->feature = adev->psp.toc.feature_version; 324 break; 325 case AMDGPU_INFO_FW_CAP: 326 fw_info->ver = adev->psp.cap_fw_version; 327 fw_info->feature = adev->psp.cap_feature_version; 328 break; 329 default: 330 return -EINVAL; 331 } 332 return 0; 333 } 334 335 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 336 struct drm_amdgpu_info *info, 337 struct drm_amdgpu_info_hw_ip *result) 338 { 339 uint32_t ib_start_alignment = 0; 340 uint32_t ib_size_alignment = 0; 341 enum amd_ip_block_type type; 342 unsigned int num_rings = 0; 343 unsigned int i, j; 344 345 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 346 return -EINVAL; 347 348 switch (info->query_hw_ip.type) { 349 case AMDGPU_HW_IP_GFX: 350 type = AMD_IP_BLOCK_TYPE_GFX; 351 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 352 if (adev->gfx.gfx_ring[i].sched.ready) 353 ++num_rings; 354 ib_start_alignment = 32; 355 ib_size_alignment = 32; 356 break; 357 case AMDGPU_HW_IP_COMPUTE: 358 type = AMD_IP_BLOCK_TYPE_GFX; 359 for (i = 0; i < adev->gfx.num_compute_rings; i++) 360 if (adev->gfx.compute_ring[i].sched.ready) 361 ++num_rings; 362 ib_start_alignment = 32; 363 ib_size_alignment = 32; 364 break; 365 case AMDGPU_HW_IP_DMA: 366 type = AMD_IP_BLOCK_TYPE_SDMA; 367 for (i = 0; i < adev->sdma.num_instances; i++) 368 if (adev->sdma.instance[i].ring.sched.ready) 369 ++num_rings; 370 ib_start_alignment = 256; 371 ib_size_alignment = 4; 372 break; 373 case AMDGPU_HW_IP_UVD: 374 type = AMD_IP_BLOCK_TYPE_UVD; 375 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 376 if (adev->uvd.harvest_config & (1 << i)) 377 continue; 378 379 if (adev->uvd.inst[i].ring.sched.ready) 380 ++num_rings; 381 } 382 ib_start_alignment = 64; 383 ib_size_alignment = 64; 384 break; 385 case AMDGPU_HW_IP_VCE: 386 type = AMD_IP_BLOCK_TYPE_VCE; 387 for (i = 0; i < adev->vce.num_rings; i++) 388 if (adev->vce.ring[i].sched.ready) 389 ++num_rings; 390 ib_start_alignment = 4; 391 ib_size_alignment = 1; 392 break; 393 case AMDGPU_HW_IP_UVD_ENC: 394 type = AMD_IP_BLOCK_TYPE_UVD; 395 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 396 if (adev->uvd.harvest_config & (1 << i)) 397 continue; 398 399 for (j = 0; j < adev->uvd.num_enc_rings; j++) 400 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 401 ++num_rings; 402 } 403 ib_start_alignment = 64; 404 ib_size_alignment = 64; 405 break; 406 case AMDGPU_HW_IP_VCN_DEC: 407 type = AMD_IP_BLOCK_TYPE_VCN; 408 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 409 if (adev->uvd.harvest_config & (1 << i)) 410 continue; 411 412 if (adev->vcn.inst[i].ring_dec.sched.ready) 413 ++num_rings; 414 } 415 ib_start_alignment = 16; 416 ib_size_alignment = 16; 417 break; 418 case AMDGPU_HW_IP_VCN_ENC: 419 type = AMD_IP_BLOCK_TYPE_VCN; 420 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 421 if (adev->uvd.harvest_config & (1 << i)) 422 continue; 423 424 for (j = 0; j < adev->vcn.num_enc_rings; j++) 425 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 426 ++num_rings; 427 } 428 ib_start_alignment = 64; 429 ib_size_alignment = 1; 430 break; 431 case AMDGPU_HW_IP_VCN_JPEG: 432 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 433 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 434 435 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 436 if (adev->jpeg.harvest_config & (1 << i)) 437 continue; 438 439 if (adev->jpeg.inst[i].ring_dec.sched.ready) 440 ++num_rings; 441 } 442 ib_start_alignment = 16; 443 ib_size_alignment = 16; 444 break; 445 default: 446 return -EINVAL; 447 } 448 449 for (i = 0; i < adev->num_ip_blocks; i++) 450 if (adev->ip_blocks[i].version->type == type && 451 adev->ip_blocks[i].status.valid) 452 break; 453 454 if (i == adev->num_ip_blocks) 455 return 0; 456 457 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 458 num_rings); 459 460 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 461 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 462 result->capabilities_flags = 0; 463 result->available_rings = (1 << num_rings) - 1; 464 result->ib_start_alignment = ib_start_alignment; 465 result->ib_size_alignment = ib_size_alignment; 466 return 0; 467 } 468 469 /* 470 * Userspace get information ioctl 471 */ 472 /** 473 * amdgpu_info_ioctl - answer a device specific request. 474 * 475 * @dev: drm device pointer 476 * @data: request object 477 * @filp: drm filp 478 * 479 * This function is used to pass device specific parameters to the userspace 480 * drivers. Examples include: pci device id, pipeline parms, tiling params, 481 * etc. (all asics). 482 * Returns 0 on success, -EINVAL on failure. 483 */ 484 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 485 { 486 struct amdgpu_device *adev = drm_to_adev(dev); 487 struct drm_amdgpu_info *info = data; 488 struct amdgpu_mode_info *minfo = &adev->mode_info; 489 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 490 uint32_t size = info->return_size; 491 struct drm_crtc *crtc; 492 uint32_t ui32 = 0; 493 uint64_t ui64 = 0; 494 int i, found; 495 int ui32_size = sizeof(ui32); 496 497 if (!info->return_size || !info->return_pointer) 498 return -EINVAL; 499 500 switch (info->query) { 501 case AMDGPU_INFO_ACCEL_WORKING: 502 ui32 = adev->accel_working; 503 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 504 case AMDGPU_INFO_CRTC_FROM_ID: 505 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 506 crtc = (struct drm_crtc *)minfo->crtcs[i]; 507 if (crtc && crtc->base.id == info->mode_crtc.id) { 508 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 509 ui32 = amdgpu_crtc->crtc_id; 510 found = 1; 511 break; 512 } 513 } 514 if (!found) { 515 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 516 return -EINVAL; 517 } 518 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 519 case AMDGPU_INFO_HW_IP_INFO: { 520 struct drm_amdgpu_info_hw_ip ip = {}; 521 int ret; 522 523 ret = amdgpu_hw_ip_info(adev, info, &ip); 524 if (ret) 525 return ret; 526 527 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 528 return ret ? -EFAULT : 0; 529 } 530 case AMDGPU_INFO_HW_IP_COUNT: { 531 enum amd_ip_block_type type; 532 uint32_t count = 0; 533 534 switch (info->query_hw_ip.type) { 535 case AMDGPU_HW_IP_GFX: 536 type = AMD_IP_BLOCK_TYPE_GFX; 537 break; 538 case AMDGPU_HW_IP_COMPUTE: 539 type = AMD_IP_BLOCK_TYPE_GFX; 540 break; 541 case AMDGPU_HW_IP_DMA: 542 type = AMD_IP_BLOCK_TYPE_SDMA; 543 break; 544 case AMDGPU_HW_IP_UVD: 545 type = AMD_IP_BLOCK_TYPE_UVD; 546 break; 547 case AMDGPU_HW_IP_VCE: 548 type = AMD_IP_BLOCK_TYPE_VCE; 549 break; 550 case AMDGPU_HW_IP_UVD_ENC: 551 type = AMD_IP_BLOCK_TYPE_UVD; 552 break; 553 case AMDGPU_HW_IP_VCN_DEC: 554 case AMDGPU_HW_IP_VCN_ENC: 555 type = AMD_IP_BLOCK_TYPE_VCN; 556 break; 557 case AMDGPU_HW_IP_VCN_JPEG: 558 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 559 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 for (i = 0; i < adev->num_ip_blocks; i++) 566 if (adev->ip_blocks[i].version->type == type && 567 adev->ip_blocks[i].status.valid && 568 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 569 count++; 570 571 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 572 } 573 case AMDGPU_INFO_TIMESTAMP: 574 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 575 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 576 case AMDGPU_INFO_FW_VERSION: { 577 struct drm_amdgpu_info_firmware fw_info; 578 int ret; 579 580 /* We only support one instance of each IP block right now. */ 581 if (info->query_fw.ip_instance != 0) 582 return -EINVAL; 583 584 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 585 if (ret) 586 return ret; 587 588 return copy_to_user(out, &fw_info, 589 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 590 } 591 case AMDGPU_INFO_NUM_BYTES_MOVED: 592 ui64 = atomic64_read(&adev->num_bytes_moved); 593 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 594 case AMDGPU_INFO_NUM_EVICTIONS: 595 ui64 = atomic64_read(&adev->num_evictions); 596 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 597 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 598 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 599 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 600 case AMDGPU_INFO_VRAM_USAGE: 601 ui64 = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 603 case AMDGPU_INFO_VIS_VRAM_USAGE: 604 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_GTT_USAGE: 607 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr); 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 609 case AMDGPU_INFO_GDS_CONFIG: { 610 struct drm_amdgpu_info_gds gds_info; 611 612 memset(&gds_info, 0, sizeof(gds_info)); 613 gds_info.compute_partition_size = adev->gds.gds_size; 614 gds_info.gds_total_size = adev->gds.gds_size; 615 gds_info.gws_per_compute_partition = adev->gds.gws_size; 616 gds_info.oa_per_compute_partition = adev->gds.oa_size; 617 return copy_to_user(out, &gds_info, 618 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 619 } 620 case AMDGPU_INFO_VRAM_GTT: { 621 struct drm_amdgpu_info_vram_gtt vram_gtt; 622 623 vram_gtt.vram_size = adev->gmc.real_vram_size - 624 atomic64_read(&adev->vram_pin_size) - 625 AMDGPU_VM_RESERVED_VRAM; 626 vram_gtt.vram_cpu_accessible_size = 627 min(adev->gmc.visible_vram_size - 628 atomic64_read(&adev->visible_pin_size), 629 vram_gtt.vram_size); 630 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 631 vram_gtt.gtt_size *= PAGE_SIZE; 632 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 633 return copy_to_user(out, &vram_gtt, 634 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 635 } 636 case AMDGPU_INFO_MEMORY: { 637 struct drm_amdgpu_memory_info mem; 638 struct ttm_resource_manager *gtt_man = 639 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 640 memset(&mem, 0, sizeof(mem)); 641 mem.vram.total_heap_size = adev->gmc.real_vram_size; 642 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 643 atomic64_read(&adev->vram_pin_size) - 644 AMDGPU_VM_RESERVED_VRAM; 645 mem.vram.heap_usage = 646 amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); 647 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 648 649 mem.cpu_accessible_vram.total_heap_size = 650 adev->gmc.visible_vram_size; 651 mem.cpu_accessible_vram.usable_heap_size = 652 min(adev->gmc.visible_vram_size - 653 atomic64_read(&adev->visible_pin_size), 654 mem.vram.usable_heap_size); 655 mem.cpu_accessible_vram.heap_usage = 656 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 657 mem.cpu_accessible_vram.max_allocation = 658 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 659 660 mem.gtt.total_heap_size = gtt_man->size; 661 mem.gtt.total_heap_size *= PAGE_SIZE; 662 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 663 atomic64_read(&adev->gart_pin_size); 664 mem.gtt.heap_usage = 665 amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr); 666 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 667 668 return copy_to_user(out, &mem, 669 min((size_t)size, sizeof(mem))) 670 ? -EFAULT : 0; 671 } 672 case AMDGPU_INFO_READ_MMR_REG: { 673 unsigned n, alloc_size; 674 uint32_t *regs; 675 unsigned se_num = (info->read_mmr_reg.instance >> 676 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 677 AMDGPU_INFO_MMR_SE_INDEX_MASK; 678 unsigned sh_num = (info->read_mmr_reg.instance >> 679 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 680 AMDGPU_INFO_MMR_SH_INDEX_MASK; 681 682 /* set full masks if the userspace set all bits 683 * in the bitfields */ 684 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 685 se_num = 0xffffffff; 686 else if (se_num >= AMDGPU_GFX_MAX_SE) 687 return -EINVAL; 688 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 689 sh_num = 0xffffffff; 690 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 691 return -EINVAL; 692 693 if (info->read_mmr_reg.count > 128) 694 return -EINVAL; 695 696 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 697 if (!regs) 698 return -ENOMEM; 699 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 700 701 amdgpu_gfx_off_ctrl(adev, false); 702 for (i = 0; i < info->read_mmr_reg.count; i++) { 703 if (amdgpu_asic_read_register(adev, se_num, sh_num, 704 info->read_mmr_reg.dword_offset + i, 705 ®s[i])) { 706 DRM_DEBUG_KMS("unallowed offset %#x\n", 707 info->read_mmr_reg.dword_offset + i); 708 kfree(regs); 709 amdgpu_gfx_off_ctrl(adev, true); 710 return -EFAULT; 711 } 712 } 713 amdgpu_gfx_off_ctrl(adev, true); 714 n = copy_to_user(out, regs, min(size, alloc_size)); 715 kfree(regs); 716 return n ? -EFAULT : 0; 717 } 718 case AMDGPU_INFO_DEV_INFO: { 719 struct drm_amdgpu_info_device *dev_info; 720 uint64_t vm_size; 721 int ret; 722 723 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 724 if (!dev_info) 725 return -ENOMEM; 726 727 dev_info->device_id = adev->pdev->device; 728 dev_info->chip_rev = adev->rev_id; 729 dev_info->external_rev = adev->external_rev_id; 730 dev_info->pci_rev = adev->pdev->revision; 731 dev_info->family = adev->family; 732 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 733 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 734 /* return all clocks in KHz */ 735 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 736 if (adev->pm.dpm_enabled) { 737 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 738 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 739 } else { 740 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 741 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 742 } 743 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 744 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 745 adev->gfx.config.max_shader_engines; 746 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 747 dev_info->_pad = 0; 748 dev_info->ids_flags = 0; 749 if (adev->flags & AMD_IS_APU) 750 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 751 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 752 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 753 if (amdgpu_is_tmz(adev)) 754 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 755 756 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 757 vm_size -= AMDGPU_VA_RESERVED_SIZE; 758 759 /* Older VCE FW versions are buggy and can handle only 40bits */ 760 if (adev->vce.fw_version && 761 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 762 vm_size = min(vm_size, 1ULL << 40); 763 764 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 765 dev_info->virtual_address_max = 766 min(vm_size, AMDGPU_GMC_HOLE_START); 767 768 if (vm_size > AMDGPU_GMC_HOLE_START) { 769 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 770 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 771 } 772 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 773 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 774 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 775 dev_info->cu_active_number = adev->gfx.cu_info.number; 776 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 777 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 778 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 779 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 780 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 781 sizeof(adev->gfx.cu_info.bitmap)); 782 dev_info->vram_type = adev->gmc.vram_type; 783 dev_info->vram_bit_width = adev->gmc.vram_width; 784 dev_info->vce_harvest_config = adev->vce.harvest_config; 785 dev_info->gc_double_offchip_lds_buf = 786 adev->gfx.config.double_offchip_lds_buf; 787 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 788 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 789 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 790 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 791 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 792 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 793 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 794 795 if (adev->family >= AMDGPU_FAMILY_NV) 796 dev_info->pa_sc_tile_steering_override = 797 adev->gfx.config.pa_sc_tile_steering_override; 798 799 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 800 801 ret = copy_to_user(out, dev_info, 802 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 803 kfree(dev_info); 804 return ret; 805 } 806 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 807 unsigned i; 808 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 809 struct amd_vce_state *vce_state; 810 811 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 812 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 813 if (vce_state) { 814 vce_clk_table.entries[i].sclk = vce_state->sclk; 815 vce_clk_table.entries[i].mclk = vce_state->mclk; 816 vce_clk_table.entries[i].eclk = vce_state->evclk; 817 vce_clk_table.num_valid_entries++; 818 } 819 } 820 821 return copy_to_user(out, &vce_clk_table, 822 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 823 } 824 case AMDGPU_INFO_VBIOS: { 825 uint32_t bios_size = adev->bios_size; 826 827 switch (info->vbios_info.type) { 828 case AMDGPU_INFO_VBIOS_SIZE: 829 return copy_to_user(out, &bios_size, 830 min((size_t)size, sizeof(bios_size))) 831 ? -EFAULT : 0; 832 case AMDGPU_INFO_VBIOS_IMAGE: { 833 uint8_t *bios; 834 uint32_t bios_offset = info->vbios_info.offset; 835 836 if (bios_offset >= bios_size) 837 return -EINVAL; 838 839 bios = adev->bios + bios_offset; 840 return copy_to_user(out, bios, 841 min((size_t)size, (size_t)(bios_size - bios_offset))) 842 ? -EFAULT : 0; 843 } 844 case AMDGPU_INFO_VBIOS_INFO: { 845 struct drm_amdgpu_info_vbios vbios_info = {}; 846 struct atom_context *atom_context; 847 848 atom_context = adev->mode_info.atom_context; 849 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 850 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 851 vbios_info.version = atom_context->version; 852 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 853 sizeof(atom_context->vbios_ver_str)); 854 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 855 856 return copy_to_user(out, &vbios_info, 857 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 858 } 859 default: 860 DRM_DEBUG_KMS("Invalid request %d\n", 861 info->vbios_info.type); 862 return -EINVAL; 863 } 864 } 865 case AMDGPU_INFO_NUM_HANDLES: { 866 struct drm_amdgpu_info_num_handles handle; 867 868 switch (info->query_hw_ip.type) { 869 case AMDGPU_HW_IP_UVD: 870 /* Starting Polaris, we support unlimited UVD handles */ 871 if (adev->asic_type < CHIP_POLARIS10) { 872 handle.uvd_max_handles = adev->uvd.max_handles; 873 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 874 875 return copy_to_user(out, &handle, 876 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 877 } else { 878 return -ENODATA; 879 } 880 881 break; 882 default: 883 return -EINVAL; 884 } 885 } 886 case AMDGPU_INFO_SENSOR: { 887 if (!adev->pm.dpm_enabled) 888 return -ENOENT; 889 890 switch (info->sensor_info.type) { 891 case AMDGPU_INFO_SENSOR_GFX_SCLK: 892 /* get sclk in Mhz */ 893 if (amdgpu_dpm_read_sensor(adev, 894 AMDGPU_PP_SENSOR_GFX_SCLK, 895 (void *)&ui32, &ui32_size)) { 896 return -EINVAL; 897 } 898 ui32 /= 100; 899 break; 900 case AMDGPU_INFO_SENSOR_GFX_MCLK: 901 /* get mclk in Mhz */ 902 if (amdgpu_dpm_read_sensor(adev, 903 AMDGPU_PP_SENSOR_GFX_MCLK, 904 (void *)&ui32, &ui32_size)) { 905 return -EINVAL; 906 } 907 ui32 /= 100; 908 break; 909 case AMDGPU_INFO_SENSOR_GPU_TEMP: 910 /* get temperature in millidegrees C */ 911 if (amdgpu_dpm_read_sensor(adev, 912 AMDGPU_PP_SENSOR_GPU_TEMP, 913 (void *)&ui32, &ui32_size)) { 914 return -EINVAL; 915 } 916 break; 917 case AMDGPU_INFO_SENSOR_GPU_LOAD: 918 /* get GPU load */ 919 if (amdgpu_dpm_read_sensor(adev, 920 AMDGPU_PP_SENSOR_GPU_LOAD, 921 (void *)&ui32, &ui32_size)) { 922 return -EINVAL; 923 } 924 break; 925 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 926 /* get average GPU power */ 927 if (amdgpu_dpm_read_sensor(adev, 928 AMDGPU_PP_SENSOR_GPU_POWER, 929 (void *)&ui32, &ui32_size)) { 930 return -EINVAL; 931 } 932 ui32 >>= 8; 933 break; 934 case AMDGPU_INFO_SENSOR_VDDNB: 935 /* get VDDNB in millivolts */ 936 if (amdgpu_dpm_read_sensor(adev, 937 AMDGPU_PP_SENSOR_VDDNB, 938 (void *)&ui32, &ui32_size)) { 939 return -EINVAL; 940 } 941 break; 942 case AMDGPU_INFO_SENSOR_VDDGFX: 943 /* get VDDGFX in millivolts */ 944 if (amdgpu_dpm_read_sensor(adev, 945 AMDGPU_PP_SENSOR_VDDGFX, 946 (void *)&ui32, &ui32_size)) { 947 return -EINVAL; 948 } 949 break; 950 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 951 /* get stable pstate sclk in Mhz */ 952 if (amdgpu_dpm_read_sensor(adev, 953 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 954 (void *)&ui32, &ui32_size)) { 955 return -EINVAL; 956 } 957 ui32 /= 100; 958 break; 959 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 960 /* get stable pstate mclk in Mhz */ 961 if (amdgpu_dpm_read_sensor(adev, 962 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 963 (void *)&ui32, &ui32_size)) { 964 return -EINVAL; 965 } 966 ui32 /= 100; 967 break; 968 default: 969 DRM_DEBUG_KMS("Invalid request %d\n", 970 info->sensor_info.type); 971 return -EINVAL; 972 } 973 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 974 } 975 case AMDGPU_INFO_VRAM_LOST_COUNTER: 976 ui32 = atomic_read(&adev->vram_lost_counter); 977 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 978 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 979 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 980 uint64_t ras_mask; 981 982 if (!ras) 983 return -EINVAL; 984 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 985 986 return copy_to_user(out, &ras_mask, 987 min_t(u64, size, sizeof(ras_mask))) ? 988 -EFAULT : 0; 989 } 990 case AMDGPU_INFO_VIDEO_CAPS: { 991 const struct amdgpu_video_codecs *codecs; 992 struct drm_amdgpu_info_video_caps *caps; 993 int r; 994 995 switch (info->video_cap.type) { 996 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 997 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 998 if (r) 999 return -EINVAL; 1000 break; 1001 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1002 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1003 if (r) 1004 return -EINVAL; 1005 break; 1006 default: 1007 DRM_DEBUG_KMS("Invalid request %d\n", 1008 info->video_cap.type); 1009 return -EINVAL; 1010 } 1011 1012 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1013 if (!caps) 1014 return -ENOMEM; 1015 1016 for (i = 0; i < codecs->codec_count; i++) { 1017 int idx = codecs->codec_array[i].codec_type; 1018 1019 switch (idx) { 1020 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1021 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1022 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1023 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1024 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1025 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1026 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1027 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1028 caps->codec_info[idx].valid = 1; 1029 caps->codec_info[idx].max_width = 1030 codecs->codec_array[i].max_width; 1031 caps->codec_info[idx].max_height = 1032 codecs->codec_array[i].max_height; 1033 caps->codec_info[idx].max_pixels_per_frame = 1034 codecs->codec_array[i].max_pixels_per_frame; 1035 caps->codec_info[idx].max_level = 1036 codecs->codec_array[i].max_level; 1037 break; 1038 default: 1039 break; 1040 } 1041 } 1042 r = copy_to_user(out, caps, 1043 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1044 kfree(caps); 1045 return r; 1046 } 1047 default: 1048 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1049 return -EINVAL; 1050 } 1051 return 0; 1052 } 1053 1054 1055 /* 1056 * Outdated mess for old drm with Xorg being in charge (void function now). 1057 */ 1058 /** 1059 * amdgpu_driver_lastclose_kms - drm callback for last close 1060 * 1061 * @dev: drm dev pointer 1062 * 1063 * Switch vga_switcheroo state after last close (all asics). 1064 */ 1065 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1066 { 1067 drm_fb_helper_lastclose(dev); 1068 vga_switcheroo_process_delayed_switch(); 1069 } 1070 1071 /** 1072 * amdgpu_driver_open_kms - drm callback for open 1073 * 1074 * @dev: drm dev pointer 1075 * @file_priv: drm file 1076 * 1077 * On device open, init vm on cayman+ (all asics). 1078 * Returns 0 on success, error on failure. 1079 */ 1080 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1081 { 1082 struct amdgpu_device *adev = drm_to_adev(dev); 1083 struct amdgpu_fpriv *fpriv; 1084 int r, pasid; 1085 1086 /* Ensure IB tests are run on ring */ 1087 flush_delayed_work(&adev->delayed_init_work); 1088 1089 1090 if (amdgpu_ras_intr_triggered()) { 1091 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1092 return -EHWPOISON; 1093 } 1094 1095 file_priv->driver_priv = NULL; 1096 1097 r = pm_runtime_get_sync(dev->dev); 1098 if (r < 0) 1099 goto pm_put; 1100 1101 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1102 if (unlikely(!fpriv)) { 1103 r = -ENOMEM; 1104 goto out_suspend; 1105 } 1106 1107 pasid = amdgpu_pasid_alloc(16); 1108 if (pasid < 0) { 1109 dev_warn(adev->dev, "No more PASIDs available!"); 1110 pasid = 0; 1111 } 1112 1113 r = amdgpu_vm_init(adev, &fpriv->vm); 1114 if (r) 1115 goto error_pasid; 1116 1117 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1118 if (r) 1119 goto error_vm; 1120 1121 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1122 if (!fpriv->prt_va) { 1123 r = -ENOMEM; 1124 goto error_vm; 1125 } 1126 1127 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1128 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1129 1130 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1131 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1132 if (r) 1133 goto error_vm; 1134 } 1135 1136 mutex_init(&fpriv->bo_list_lock); 1137 idr_init(&fpriv->bo_list_handles); 1138 1139 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1140 1141 file_priv->driver_priv = fpriv; 1142 goto out_suspend; 1143 1144 error_vm: 1145 amdgpu_vm_fini(adev, &fpriv->vm); 1146 1147 error_pasid: 1148 if (pasid) { 1149 amdgpu_pasid_free(pasid); 1150 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1151 } 1152 1153 kfree(fpriv); 1154 1155 out_suspend: 1156 pm_runtime_mark_last_busy(dev->dev); 1157 pm_put: 1158 pm_runtime_put_autosuspend(dev->dev); 1159 1160 return r; 1161 } 1162 1163 /** 1164 * amdgpu_driver_postclose_kms - drm callback for post close 1165 * 1166 * @dev: drm dev pointer 1167 * @file_priv: drm file 1168 * 1169 * On device post close, tear down vm on cayman+ (all asics). 1170 */ 1171 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1172 struct drm_file *file_priv) 1173 { 1174 struct amdgpu_device *adev = drm_to_adev(dev); 1175 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1176 struct amdgpu_bo_list *list; 1177 struct amdgpu_bo *pd; 1178 u32 pasid; 1179 int handle; 1180 1181 if (!fpriv) 1182 return; 1183 1184 pm_runtime_get_sync(dev->dev); 1185 1186 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1187 amdgpu_uvd_free_handles(adev, file_priv); 1188 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1189 amdgpu_vce_free_handles(adev, file_priv); 1190 1191 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1192 1193 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1194 /* TODO: how to handle reserve failure */ 1195 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1196 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1197 fpriv->csa_va = NULL; 1198 amdgpu_bo_unreserve(adev->virt.csa_obj); 1199 } 1200 1201 pasid = fpriv->vm.pasid; 1202 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1203 1204 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1205 amdgpu_vm_fini(adev, &fpriv->vm); 1206 1207 if (pasid) 1208 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1209 amdgpu_bo_unref(&pd); 1210 1211 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1212 amdgpu_bo_list_put(list); 1213 1214 idr_destroy(&fpriv->bo_list_handles); 1215 mutex_destroy(&fpriv->bo_list_lock); 1216 1217 kfree(fpriv); 1218 file_priv->driver_priv = NULL; 1219 1220 pm_runtime_mark_last_busy(dev->dev); 1221 pm_runtime_put_autosuspend(dev->dev); 1222 } 1223 1224 1225 void amdgpu_driver_release_kms(struct drm_device *dev) 1226 { 1227 struct amdgpu_device *adev = drm_to_adev(dev); 1228 1229 amdgpu_device_fini_sw(adev); 1230 pci_set_drvdata(adev->pdev, NULL); 1231 } 1232 1233 /* 1234 * VBlank related functions. 1235 */ 1236 /** 1237 * amdgpu_get_vblank_counter_kms - get frame count 1238 * 1239 * @crtc: crtc to get the frame count from 1240 * 1241 * Gets the frame count on the requested crtc (all asics). 1242 * Returns frame count on success, -EINVAL on failure. 1243 */ 1244 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1245 { 1246 struct drm_device *dev = crtc->dev; 1247 unsigned int pipe = crtc->index; 1248 struct amdgpu_device *adev = drm_to_adev(dev); 1249 int vpos, hpos, stat; 1250 u32 count; 1251 1252 if (pipe >= adev->mode_info.num_crtc) { 1253 DRM_ERROR("Invalid crtc %u\n", pipe); 1254 return -EINVAL; 1255 } 1256 1257 /* The hw increments its frame counter at start of vsync, not at start 1258 * of vblank, as is required by DRM core vblank counter handling. 1259 * Cook the hw count here to make it appear to the caller as if it 1260 * incremented at start of vblank. We measure distance to start of 1261 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1262 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1263 * result by 1 to give the proper appearance to caller. 1264 */ 1265 if (adev->mode_info.crtcs[pipe]) { 1266 /* Repeat readout if needed to provide stable result if 1267 * we cross start of vsync during the queries. 1268 */ 1269 do { 1270 count = amdgpu_display_vblank_get_counter(adev, pipe); 1271 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1272 * vpos as distance to start of vblank, instead of 1273 * regular vertical scanout pos. 1274 */ 1275 stat = amdgpu_display_get_crtc_scanoutpos( 1276 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1277 &vpos, &hpos, NULL, NULL, 1278 &adev->mode_info.crtcs[pipe]->base.hwmode); 1279 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1280 1281 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1282 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1283 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1284 } else { 1285 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1286 pipe, vpos); 1287 1288 /* Bump counter if we are at >= leading edge of vblank, 1289 * but before vsync where vpos would turn negative and 1290 * the hw counter really increments. 1291 */ 1292 if (vpos >= 0) 1293 count++; 1294 } 1295 } else { 1296 /* Fallback to use value as is. */ 1297 count = amdgpu_display_vblank_get_counter(adev, pipe); 1298 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1299 } 1300 1301 return count; 1302 } 1303 1304 /** 1305 * amdgpu_enable_vblank_kms - enable vblank interrupt 1306 * 1307 * @crtc: crtc to enable vblank interrupt for 1308 * 1309 * Enable the interrupt on the requested crtc (all asics). 1310 * Returns 0 on success, -EINVAL on failure. 1311 */ 1312 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1313 { 1314 struct drm_device *dev = crtc->dev; 1315 unsigned int pipe = crtc->index; 1316 struct amdgpu_device *adev = drm_to_adev(dev); 1317 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1318 1319 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1320 } 1321 1322 /** 1323 * amdgpu_disable_vblank_kms - disable vblank interrupt 1324 * 1325 * @crtc: crtc to disable vblank interrupt for 1326 * 1327 * Disable the interrupt on the requested crtc (all asics). 1328 */ 1329 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1330 { 1331 struct drm_device *dev = crtc->dev; 1332 unsigned int pipe = crtc->index; 1333 struct amdgpu_device *adev = drm_to_adev(dev); 1334 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1335 1336 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1337 } 1338 1339 /* 1340 * Debugfs info 1341 */ 1342 #if defined(CONFIG_DEBUG_FS) 1343 1344 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1345 { 1346 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1347 struct drm_amdgpu_info_firmware fw_info; 1348 struct drm_amdgpu_query_fw query_fw; 1349 struct atom_context *ctx = adev->mode_info.atom_context; 1350 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1351 int ret, i; 1352 1353 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1354 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1355 TA_FW_NAME(XGMI), 1356 TA_FW_NAME(RAS), 1357 TA_FW_NAME(HDCP), 1358 TA_FW_NAME(DTM), 1359 TA_FW_NAME(RAP), 1360 TA_FW_NAME(SECUREDISPLAY), 1361 #undef TA_FW_NAME 1362 }; 1363 1364 /* VCE */ 1365 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1366 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1367 if (ret) 1368 return ret; 1369 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1370 fw_info.feature, fw_info.ver); 1371 1372 /* UVD */ 1373 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1374 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1375 if (ret) 1376 return ret; 1377 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1378 fw_info.feature, fw_info.ver); 1379 1380 /* GMC */ 1381 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1382 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1383 if (ret) 1384 return ret; 1385 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1386 fw_info.feature, fw_info.ver); 1387 1388 /* ME */ 1389 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1390 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1391 if (ret) 1392 return ret; 1393 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1394 fw_info.feature, fw_info.ver); 1395 1396 /* PFP */ 1397 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1398 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1399 if (ret) 1400 return ret; 1401 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1402 fw_info.feature, fw_info.ver); 1403 1404 /* CE */ 1405 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1406 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1407 if (ret) 1408 return ret; 1409 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1410 fw_info.feature, fw_info.ver); 1411 1412 /* RLC */ 1413 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1414 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1415 if (ret) 1416 return ret; 1417 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1418 fw_info.feature, fw_info.ver); 1419 1420 /* RLC SAVE RESTORE LIST CNTL */ 1421 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1423 if (ret) 1424 return ret; 1425 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1426 fw_info.feature, fw_info.ver); 1427 1428 /* RLC SAVE RESTORE LIST GPM MEM */ 1429 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1430 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1431 if (ret) 1432 return ret; 1433 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1434 fw_info.feature, fw_info.ver); 1435 1436 /* RLC SAVE RESTORE LIST SRM MEM */ 1437 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1438 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1439 if (ret) 1440 return ret; 1441 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1442 fw_info.feature, fw_info.ver); 1443 1444 /* MEC */ 1445 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1446 query_fw.index = 0; 1447 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1448 if (ret) 1449 return ret; 1450 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1451 fw_info.feature, fw_info.ver); 1452 1453 /* MEC2 */ 1454 if (adev->gfx.mec2_fw) { 1455 query_fw.index = 1; 1456 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1457 if (ret) 1458 return ret; 1459 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1460 fw_info.feature, fw_info.ver); 1461 } 1462 1463 /* PSP SOS */ 1464 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1465 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1466 if (ret) 1467 return ret; 1468 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1469 fw_info.feature, fw_info.ver); 1470 1471 1472 /* PSP ASD */ 1473 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1474 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1475 if (ret) 1476 return ret; 1477 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1478 fw_info.feature, fw_info.ver); 1479 1480 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1481 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1482 query_fw.index = i; 1483 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1484 if (ret) 1485 continue; 1486 1487 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1488 ta_fw_name[i], fw_info.feature, fw_info.ver); 1489 } 1490 1491 /* SMC */ 1492 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1493 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1494 if (ret) 1495 return ret; 1496 smu_program = (fw_info.ver >> 24) & 0xff; 1497 smu_major = (fw_info.ver >> 16) & 0xff; 1498 smu_minor = (fw_info.ver >> 8) & 0xff; 1499 smu_debug = (fw_info.ver >> 0) & 0xff; 1500 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1501 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1502 1503 /* SDMA */ 1504 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1505 for (i = 0; i < adev->sdma.num_instances; i++) { 1506 query_fw.index = i; 1507 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1508 if (ret) 1509 return ret; 1510 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1511 i, fw_info.feature, fw_info.ver); 1512 } 1513 1514 /* VCN */ 1515 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1516 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1517 if (ret) 1518 return ret; 1519 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1520 fw_info.feature, fw_info.ver); 1521 1522 /* DMCU */ 1523 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1524 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1525 if (ret) 1526 return ret; 1527 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1528 fw_info.feature, fw_info.ver); 1529 1530 /* DMCUB */ 1531 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1532 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1533 if (ret) 1534 return ret; 1535 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1536 fw_info.feature, fw_info.ver); 1537 1538 /* TOC */ 1539 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1540 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1541 if (ret) 1542 return ret; 1543 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1544 fw_info.feature, fw_info.ver); 1545 1546 /* CAP */ 1547 if (adev->psp.cap_fw) { 1548 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1549 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1550 if (ret) 1551 return ret; 1552 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1553 fw_info.feature, fw_info.ver); 1554 } 1555 1556 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1557 1558 return 0; 1559 } 1560 1561 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1562 1563 #endif 1564 1565 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1566 { 1567 #if defined(CONFIG_DEBUG_FS) 1568 struct drm_minor *minor = adev_to_drm(adev)->primary; 1569 struct dentry *root = minor->debugfs_root; 1570 1571 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1572 adev, &amdgpu_debugfs_firmware_info_fops); 1573 1574 #endif 1575 } 1576