1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 98 amdgpu_device_fini(adev); 99 100 done_free: 101 kfree(adev); 102 dev->dev_private = NULL; 103 } 104 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 106 { 107 struct amdgpu_gpu_instance *gpu_instance; 108 109 mutex_lock(&mgpu_info.mutex); 110 111 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 112 DRM_ERROR("Cannot register more gpu instance\n"); 113 mutex_unlock(&mgpu_info.mutex); 114 return; 115 } 116 117 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 118 gpu_instance->adev = adev; 119 gpu_instance->mgpu_fan_enabled = 0; 120 121 mgpu_info.num_gpu++; 122 if (adev->flags & AMD_IS_APU) 123 mgpu_info.num_apu++; 124 else 125 mgpu_info.num_dgpu++; 126 127 mutex_unlock(&mgpu_info.mutex); 128 } 129 130 /** 131 * amdgpu_driver_load_kms - Main load function for KMS. 132 * 133 * @dev: drm dev pointer 134 * @flags: device flags 135 * 136 * This is the main load function for KMS (all asics). 137 * Returns 0 on success, error on failure. 138 */ 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 140 { 141 struct amdgpu_device *adev; 142 int r, acpi_status; 143 144 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 145 if (adev == NULL) { 146 return -ENOMEM; 147 } 148 dev->dev_private = (void *)adev; 149 150 if (amdgpu_has_atpx() && 151 (amdgpu_is_atpx_hybrid() || 152 amdgpu_has_atpx_dgpu_power_cntl()) && 153 ((flags & AMD_IS_APU) == 0) && 154 !pci_is_thunderbolt_attached(dev->pdev)) 155 flags |= AMD_IS_PX; 156 157 /* amdgpu_device_init should report only fatal error 158 * like memory allocation failure or iomapping failure, 159 * or memory manager initialization failure, it must 160 * properly initialize the GPU MC controller and permit 161 * VRAM allocation 162 */ 163 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 164 if (r) { 165 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 166 goto out; 167 } 168 169 if (amdgpu_device_supports_boco(dev) && 170 (amdgpu_runtime_pm != 0)) /* enable runpm by default for boco */ 171 adev->runpm = true; 172 else if (amdgpu_device_supports_baco(dev) && 173 (amdgpu_runtime_pm != 0) && 174 (adev->asic_type >= CHIP_TOPAZ) && 175 (adev->asic_type != CHIP_VEGA10) && 176 (adev->asic_type != CHIP_VEGA20) && 177 (adev->asic_type != CHIP_ARCTURUS)) /* enable runpm on VI+ */ 178 adev->runpm = true; 179 else if (amdgpu_device_supports_baco(dev) && 180 (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 on CI */ 181 adev->runpm = true; 182 183 /* Call ACPI methods: require modeset init 184 * but failure is not fatal 185 */ 186 187 acpi_status = amdgpu_acpi_init(adev); 188 if (acpi_status) 189 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 190 191 if (adev->runpm) { 192 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); 193 pm_runtime_use_autosuspend(dev->dev); 194 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 195 pm_runtime_set_active(dev->dev); 196 pm_runtime_allow(dev->dev); 197 pm_runtime_mark_last_busy(dev->dev); 198 pm_runtime_put_autosuspend(dev->dev); 199 } 200 201 out: 202 if (r) { 203 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 204 if (adev->rmmio && adev->runpm) 205 pm_runtime_put_noidle(dev->dev); 206 amdgpu_driver_unload_kms(dev); 207 } 208 209 return r; 210 } 211 212 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 213 struct drm_amdgpu_query_fw *query_fw, 214 struct amdgpu_device *adev) 215 { 216 switch (query_fw->fw_type) { 217 case AMDGPU_INFO_FW_VCE: 218 fw_info->ver = adev->vce.fw_version; 219 fw_info->feature = adev->vce.fb_version; 220 break; 221 case AMDGPU_INFO_FW_UVD: 222 fw_info->ver = adev->uvd.fw_version; 223 fw_info->feature = 0; 224 break; 225 case AMDGPU_INFO_FW_VCN: 226 fw_info->ver = adev->vcn.fw_version; 227 fw_info->feature = 0; 228 break; 229 case AMDGPU_INFO_FW_GMC: 230 fw_info->ver = adev->gmc.fw_version; 231 fw_info->feature = 0; 232 break; 233 case AMDGPU_INFO_FW_GFX_ME: 234 fw_info->ver = adev->gfx.me_fw_version; 235 fw_info->feature = adev->gfx.me_feature_version; 236 break; 237 case AMDGPU_INFO_FW_GFX_PFP: 238 fw_info->ver = adev->gfx.pfp_fw_version; 239 fw_info->feature = adev->gfx.pfp_feature_version; 240 break; 241 case AMDGPU_INFO_FW_GFX_CE: 242 fw_info->ver = adev->gfx.ce_fw_version; 243 fw_info->feature = adev->gfx.ce_feature_version; 244 break; 245 case AMDGPU_INFO_FW_GFX_RLC: 246 fw_info->ver = adev->gfx.rlc_fw_version; 247 fw_info->feature = adev->gfx.rlc_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 250 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 251 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 254 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 255 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 258 fw_info->ver = adev->gfx.rlc_srls_fw_version; 259 fw_info->feature = adev->gfx.rlc_srls_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_MEC: 262 if (query_fw->index == 0) { 263 fw_info->ver = adev->gfx.mec_fw_version; 264 fw_info->feature = adev->gfx.mec_feature_version; 265 } else if (query_fw->index == 1) { 266 fw_info->ver = adev->gfx.mec2_fw_version; 267 fw_info->feature = adev->gfx.mec2_feature_version; 268 } else 269 return -EINVAL; 270 break; 271 case AMDGPU_INFO_FW_SMC: 272 fw_info->ver = adev->pm.fw_version; 273 fw_info->feature = 0; 274 break; 275 case AMDGPU_INFO_FW_TA: 276 if (query_fw->index > 1) 277 return -EINVAL; 278 if (query_fw->index == 0) { 279 fw_info->ver = adev->psp.ta_fw_version; 280 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 281 } else { 282 fw_info->ver = adev->psp.ta_fw_version; 283 fw_info->feature = adev->psp.ta_ras_ucode_version; 284 } 285 break; 286 case AMDGPU_INFO_FW_SDMA: 287 if (query_fw->index >= adev->sdma.num_instances) 288 return -EINVAL; 289 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 290 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 291 break; 292 case AMDGPU_INFO_FW_SOS: 293 fw_info->ver = adev->psp.sos_fw_version; 294 fw_info->feature = adev->psp.sos_feature_version; 295 break; 296 case AMDGPU_INFO_FW_ASD: 297 fw_info->ver = adev->psp.asd_fw_version; 298 fw_info->feature = adev->psp.asd_feature_version; 299 break; 300 case AMDGPU_INFO_FW_DMCU: 301 fw_info->ver = adev->dm.dmcu_fw_version; 302 fw_info->feature = 0; 303 break; 304 case AMDGPU_INFO_FW_DMCUB: 305 fw_info->ver = adev->dm.dmcub_fw_version; 306 fw_info->feature = 0; 307 break; 308 default: 309 return -EINVAL; 310 } 311 return 0; 312 } 313 314 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 315 struct drm_amdgpu_info *info, 316 struct drm_amdgpu_info_hw_ip *result) 317 { 318 uint32_t ib_start_alignment = 0; 319 uint32_t ib_size_alignment = 0; 320 enum amd_ip_block_type type; 321 unsigned int num_rings = 0; 322 unsigned int i, j; 323 324 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 325 return -EINVAL; 326 327 switch (info->query_hw_ip.type) { 328 case AMDGPU_HW_IP_GFX: 329 type = AMD_IP_BLOCK_TYPE_GFX; 330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 331 if (adev->gfx.gfx_ring[i].sched.ready) 332 ++num_rings; 333 ib_start_alignment = 32; 334 ib_size_alignment = 32; 335 break; 336 case AMDGPU_HW_IP_COMPUTE: 337 type = AMD_IP_BLOCK_TYPE_GFX; 338 for (i = 0; i < adev->gfx.num_compute_rings; i++) 339 if (adev->gfx.compute_ring[i].sched.ready) 340 ++num_rings; 341 ib_start_alignment = 32; 342 ib_size_alignment = 32; 343 break; 344 case AMDGPU_HW_IP_DMA: 345 type = AMD_IP_BLOCK_TYPE_SDMA; 346 for (i = 0; i < adev->sdma.num_instances; i++) 347 if (adev->sdma.instance[i].ring.sched.ready) 348 ++num_rings; 349 ib_start_alignment = 256; 350 ib_size_alignment = 4; 351 break; 352 case AMDGPU_HW_IP_UVD: 353 type = AMD_IP_BLOCK_TYPE_UVD; 354 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 355 if (adev->uvd.harvest_config & (1 << i)) 356 continue; 357 358 if (adev->uvd.inst[i].ring.sched.ready) 359 ++num_rings; 360 } 361 ib_start_alignment = 64; 362 ib_size_alignment = 64; 363 break; 364 case AMDGPU_HW_IP_VCE: 365 type = AMD_IP_BLOCK_TYPE_VCE; 366 for (i = 0; i < adev->vce.num_rings; i++) 367 if (adev->vce.ring[i].sched.ready) 368 ++num_rings; 369 ib_start_alignment = 4; 370 ib_size_alignment = 1; 371 break; 372 case AMDGPU_HW_IP_UVD_ENC: 373 type = AMD_IP_BLOCK_TYPE_UVD; 374 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 375 if (adev->uvd.harvest_config & (1 << i)) 376 continue; 377 378 for (j = 0; j < adev->uvd.num_enc_rings; j++) 379 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 380 ++num_rings; 381 } 382 ib_start_alignment = 64; 383 ib_size_alignment = 64; 384 break; 385 case AMDGPU_HW_IP_VCN_DEC: 386 type = AMD_IP_BLOCK_TYPE_VCN; 387 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 388 if (adev->uvd.harvest_config & (1 << i)) 389 continue; 390 391 if (adev->vcn.inst[i].ring_dec.sched.ready) 392 ++num_rings; 393 } 394 ib_start_alignment = 16; 395 ib_size_alignment = 16; 396 break; 397 case AMDGPU_HW_IP_VCN_ENC: 398 type = AMD_IP_BLOCK_TYPE_VCN; 399 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 400 if (adev->uvd.harvest_config & (1 << i)) 401 continue; 402 403 for (j = 0; j < adev->vcn.num_enc_rings; j++) 404 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 405 ++num_rings; 406 } 407 ib_start_alignment = 64; 408 ib_size_alignment = 1; 409 break; 410 case AMDGPU_HW_IP_VCN_JPEG: 411 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 412 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 413 414 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 415 if (adev->jpeg.harvest_config & (1 << i)) 416 continue; 417 418 if (adev->jpeg.inst[i].ring_dec.sched.ready) 419 ++num_rings; 420 } 421 ib_start_alignment = 16; 422 ib_size_alignment = 16; 423 break; 424 default: 425 return -EINVAL; 426 } 427 428 for (i = 0; i < adev->num_ip_blocks; i++) 429 if (adev->ip_blocks[i].version->type == type && 430 adev->ip_blocks[i].status.valid) 431 break; 432 433 if (i == adev->num_ip_blocks) 434 return 0; 435 436 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 437 num_rings); 438 439 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 440 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 441 result->capabilities_flags = 0; 442 result->available_rings = (1 << num_rings) - 1; 443 result->ib_start_alignment = ib_start_alignment; 444 result->ib_size_alignment = ib_size_alignment; 445 return 0; 446 } 447 448 /* 449 * Userspace get information ioctl 450 */ 451 /** 452 * amdgpu_info_ioctl - answer a device specific request. 453 * 454 * @adev: amdgpu device pointer 455 * @data: request object 456 * @filp: drm filp 457 * 458 * This function is used to pass device specific parameters to the userspace 459 * drivers. Examples include: pci device id, pipeline parms, tiling params, 460 * etc. (all asics). 461 * Returns 0 on success, -EINVAL on failure. 462 */ 463 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 464 { 465 struct amdgpu_device *adev = dev->dev_private; 466 struct drm_amdgpu_info *info = data; 467 struct amdgpu_mode_info *minfo = &adev->mode_info; 468 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 469 uint32_t size = info->return_size; 470 struct drm_crtc *crtc; 471 uint32_t ui32 = 0; 472 uint64_t ui64 = 0; 473 int i, found; 474 int ui32_size = sizeof(ui32); 475 476 if (!info->return_size || !info->return_pointer) 477 return -EINVAL; 478 479 switch (info->query) { 480 case AMDGPU_INFO_ACCEL_WORKING: 481 ui32 = adev->accel_working; 482 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 483 case AMDGPU_INFO_CRTC_FROM_ID: 484 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 485 crtc = (struct drm_crtc *)minfo->crtcs[i]; 486 if (crtc && crtc->base.id == info->mode_crtc.id) { 487 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 488 ui32 = amdgpu_crtc->crtc_id; 489 found = 1; 490 break; 491 } 492 } 493 if (!found) { 494 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 495 return -EINVAL; 496 } 497 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 498 case AMDGPU_INFO_HW_IP_INFO: { 499 struct drm_amdgpu_info_hw_ip ip = {}; 500 int ret; 501 502 ret = amdgpu_hw_ip_info(adev, info, &ip); 503 if (ret) 504 return ret; 505 506 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 507 return ret ? -EFAULT : 0; 508 } 509 case AMDGPU_INFO_HW_IP_COUNT: { 510 enum amd_ip_block_type type; 511 uint32_t count = 0; 512 513 switch (info->query_hw_ip.type) { 514 case AMDGPU_HW_IP_GFX: 515 type = AMD_IP_BLOCK_TYPE_GFX; 516 break; 517 case AMDGPU_HW_IP_COMPUTE: 518 type = AMD_IP_BLOCK_TYPE_GFX; 519 break; 520 case AMDGPU_HW_IP_DMA: 521 type = AMD_IP_BLOCK_TYPE_SDMA; 522 break; 523 case AMDGPU_HW_IP_UVD: 524 type = AMD_IP_BLOCK_TYPE_UVD; 525 break; 526 case AMDGPU_HW_IP_VCE: 527 type = AMD_IP_BLOCK_TYPE_VCE; 528 break; 529 case AMDGPU_HW_IP_UVD_ENC: 530 type = AMD_IP_BLOCK_TYPE_UVD; 531 break; 532 case AMDGPU_HW_IP_VCN_DEC: 533 case AMDGPU_HW_IP_VCN_ENC: 534 type = AMD_IP_BLOCK_TYPE_VCN; 535 break; 536 case AMDGPU_HW_IP_VCN_JPEG: 537 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 538 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 539 break; 540 default: 541 return -EINVAL; 542 } 543 544 for (i = 0; i < adev->num_ip_blocks; i++) 545 if (adev->ip_blocks[i].version->type == type && 546 adev->ip_blocks[i].status.valid && 547 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 548 count++; 549 550 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 551 } 552 case AMDGPU_INFO_TIMESTAMP: 553 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 554 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 555 case AMDGPU_INFO_FW_VERSION: { 556 struct drm_amdgpu_info_firmware fw_info; 557 int ret; 558 559 /* We only support one instance of each IP block right now. */ 560 if (info->query_fw.ip_instance != 0) 561 return -EINVAL; 562 563 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 564 if (ret) 565 return ret; 566 567 return copy_to_user(out, &fw_info, 568 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 569 } 570 case AMDGPU_INFO_NUM_BYTES_MOVED: 571 ui64 = atomic64_read(&adev->num_bytes_moved); 572 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 573 case AMDGPU_INFO_NUM_EVICTIONS: 574 ui64 = atomic64_read(&adev->num_evictions); 575 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 576 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 577 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 578 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 579 case AMDGPU_INFO_VRAM_USAGE: 580 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 581 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 582 case AMDGPU_INFO_VIS_VRAM_USAGE: 583 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 584 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 585 case AMDGPU_INFO_GTT_USAGE: 586 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 587 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 588 case AMDGPU_INFO_GDS_CONFIG: { 589 struct drm_amdgpu_info_gds gds_info; 590 591 memset(&gds_info, 0, sizeof(gds_info)); 592 gds_info.compute_partition_size = adev->gds.gds_size; 593 gds_info.gds_total_size = adev->gds.gds_size; 594 gds_info.gws_per_compute_partition = adev->gds.gws_size; 595 gds_info.oa_per_compute_partition = adev->gds.oa_size; 596 return copy_to_user(out, &gds_info, 597 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 598 } 599 case AMDGPU_INFO_VRAM_GTT: { 600 struct drm_amdgpu_info_vram_gtt vram_gtt; 601 602 vram_gtt.vram_size = adev->gmc.real_vram_size - 603 atomic64_read(&adev->vram_pin_size) - 604 AMDGPU_VM_RESERVED_VRAM; 605 vram_gtt.vram_cpu_accessible_size = 606 min(adev->gmc.visible_vram_size - 607 atomic64_read(&adev->visible_pin_size), 608 vram_gtt.vram_size); 609 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 610 vram_gtt.gtt_size *= PAGE_SIZE; 611 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 612 return copy_to_user(out, &vram_gtt, 613 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 614 } 615 case AMDGPU_INFO_MEMORY: { 616 struct drm_amdgpu_memory_info mem; 617 618 memset(&mem, 0, sizeof(mem)); 619 mem.vram.total_heap_size = adev->gmc.real_vram_size; 620 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 621 atomic64_read(&adev->vram_pin_size) - 622 AMDGPU_VM_RESERVED_VRAM; 623 mem.vram.heap_usage = 624 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 625 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 626 627 mem.cpu_accessible_vram.total_heap_size = 628 adev->gmc.visible_vram_size; 629 mem.cpu_accessible_vram.usable_heap_size = 630 min(adev->gmc.visible_vram_size - 631 atomic64_read(&adev->visible_pin_size), 632 mem.vram.usable_heap_size); 633 mem.cpu_accessible_vram.heap_usage = 634 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 635 mem.cpu_accessible_vram.max_allocation = 636 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 637 638 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 639 mem.gtt.total_heap_size *= PAGE_SIZE; 640 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 641 atomic64_read(&adev->gart_pin_size); 642 mem.gtt.heap_usage = 643 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 644 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 645 646 return copy_to_user(out, &mem, 647 min((size_t)size, sizeof(mem))) 648 ? -EFAULT : 0; 649 } 650 case AMDGPU_INFO_READ_MMR_REG: { 651 unsigned n, alloc_size; 652 uint32_t *regs; 653 unsigned se_num = (info->read_mmr_reg.instance >> 654 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 655 AMDGPU_INFO_MMR_SE_INDEX_MASK; 656 unsigned sh_num = (info->read_mmr_reg.instance >> 657 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 658 AMDGPU_INFO_MMR_SH_INDEX_MASK; 659 660 /* set full masks if the userspace set all bits 661 * in the bitfields */ 662 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 663 se_num = 0xffffffff; 664 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 665 sh_num = 0xffffffff; 666 667 if (info->read_mmr_reg.count > 128) 668 return -EINVAL; 669 670 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 671 if (!regs) 672 return -ENOMEM; 673 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 674 675 amdgpu_gfx_off_ctrl(adev, false); 676 for (i = 0; i < info->read_mmr_reg.count; i++) { 677 if (amdgpu_asic_read_register(adev, se_num, sh_num, 678 info->read_mmr_reg.dword_offset + i, 679 ®s[i])) { 680 DRM_DEBUG_KMS("unallowed offset %#x\n", 681 info->read_mmr_reg.dword_offset + i); 682 kfree(regs); 683 amdgpu_gfx_off_ctrl(adev, true); 684 return -EFAULT; 685 } 686 } 687 amdgpu_gfx_off_ctrl(adev, true); 688 n = copy_to_user(out, regs, min(size, alloc_size)); 689 kfree(regs); 690 return n ? -EFAULT : 0; 691 } 692 case AMDGPU_INFO_DEV_INFO: { 693 struct drm_amdgpu_info_device dev_info = {}; 694 uint64_t vm_size; 695 696 dev_info.device_id = dev->pdev->device; 697 dev_info.chip_rev = adev->rev_id; 698 dev_info.external_rev = adev->external_rev_id; 699 dev_info.pci_rev = dev->pdev->revision; 700 dev_info.family = adev->family; 701 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 702 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 703 /* return all clocks in KHz */ 704 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 705 if (adev->pm.dpm_enabled) { 706 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 707 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 708 } else { 709 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 710 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 711 } 712 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 713 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 714 adev->gfx.config.max_shader_engines; 715 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 716 dev_info._pad = 0; 717 dev_info.ids_flags = 0; 718 if (adev->flags & AMD_IS_APU) 719 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 720 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 721 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 722 723 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 724 vm_size -= AMDGPU_VA_RESERVED_SIZE; 725 726 /* Older VCE FW versions are buggy and can handle only 40bits */ 727 if (adev->vce.fw_version && 728 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 729 vm_size = min(vm_size, 1ULL << 40); 730 731 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 732 dev_info.virtual_address_max = 733 min(vm_size, AMDGPU_GMC_HOLE_START); 734 735 if (vm_size > AMDGPU_GMC_HOLE_START) { 736 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 737 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 738 } 739 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 740 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 741 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 742 dev_info.cu_active_number = adev->gfx.cu_info.number; 743 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 744 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 745 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 746 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 747 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 748 sizeof(adev->gfx.cu_info.bitmap)); 749 dev_info.vram_type = adev->gmc.vram_type; 750 dev_info.vram_bit_width = adev->gmc.vram_width; 751 dev_info.vce_harvest_config = adev->vce.harvest_config; 752 dev_info.gc_double_offchip_lds_buf = 753 adev->gfx.config.double_offchip_lds_buf; 754 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 755 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 756 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 757 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 758 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 759 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 760 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 761 762 if (adev->family >= AMDGPU_FAMILY_NV) 763 dev_info.pa_sc_tile_steering_override = 764 adev->gfx.config.pa_sc_tile_steering_override; 765 766 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 767 768 return copy_to_user(out, &dev_info, 769 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 770 } 771 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 772 unsigned i; 773 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 774 struct amd_vce_state *vce_state; 775 776 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 777 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 778 if (vce_state) { 779 vce_clk_table.entries[i].sclk = vce_state->sclk; 780 vce_clk_table.entries[i].mclk = vce_state->mclk; 781 vce_clk_table.entries[i].eclk = vce_state->evclk; 782 vce_clk_table.num_valid_entries++; 783 } 784 } 785 786 return copy_to_user(out, &vce_clk_table, 787 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 788 } 789 case AMDGPU_INFO_VBIOS: { 790 uint32_t bios_size = adev->bios_size; 791 792 switch (info->vbios_info.type) { 793 case AMDGPU_INFO_VBIOS_SIZE: 794 return copy_to_user(out, &bios_size, 795 min((size_t)size, sizeof(bios_size))) 796 ? -EFAULT : 0; 797 case AMDGPU_INFO_VBIOS_IMAGE: { 798 uint8_t *bios; 799 uint32_t bios_offset = info->vbios_info.offset; 800 801 if (bios_offset >= bios_size) 802 return -EINVAL; 803 804 bios = adev->bios + bios_offset; 805 return copy_to_user(out, bios, 806 min((size_t)size, (size_t)(bios_size - bios_offset))) 807 ? -EFAULT : 0; 808 } 809 default: 810 DRM_DEBUG_KMS("Invalid request %d\n", 811 info->vbios_info.type); 812 return -EINVAL; 813 } 814 } 815 case AMDGPU_INFO_NUM_HANDLES: { 816 struct drm_amdgpu_info_num_handles handle; 817 818 switch (info->query_hw_ip.type) { 819 case AMDGPU_HW_IP_UVD: 820 /* Starting Polaris, we support unlimited UVD handles */ 821 if (adev->asic_type < CHIP_POLARIS10) { 822 handle.uvd_max_handles = adev->uvd.max_handles; 823 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 824 825 return copy_to_user(out, &handle, 826 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 827 } else { 828 return -ENODATA; 829 } 830 831 break; 832 default: 833 return -EINVAL; 834 } 835 } 836 case AMDGPU_INFO_SENSOR: { 837 if (!adev->pm.dpm_enabled) 838 return -ENOENT; 839 840 switch (info->sensor_info.type) { 841 case AMDGPU_INFO_SENSOR_GFX_SCLK: 842 /* get sclk in Mhz */ 843 if (amdgpu_dpm_read_sensor(adev, 844 AMDGPU_PP_SENSOR_GFX_SCLK, 845 (void *)&ui32, &ui32_size)) { 846 return -EINVAL; 847 } 848 ui32 /= 100; 849 break; 850 case AMDGPU_INFO_SENSOR_GFX_MCLK: 851 /* get mclk in Mhz */ 852 if (amdgpu_dpm_read_sensor(adev, 853 AMDGPU_PP_SENSOR_GFX_MCLK, 854 (void *)&ui32, &ui32_size)) { 855 return -EINVAL; 856 } 857 ui32 /= 100; 858 break; 859 case AMDGPU_INFO_SENSOR_GPU_TEMP: 860 /* get temperature in millidegrees C */ 861 if (amdgpu_dpm_read_sensor(adev, 862 AMDGPU_PP_SENSOR_GPU_TEMP, 863 (void *)&ui32, &ui32_size)) { 864 return -EINVAL; 865 } 866 break; 867 case AMDGPU_INFO_SENSOR_GPU_LOAD: 868 /* get GPU load */ 869 if (amdgpu_dpm_read_sensor(adev, 870 AMDGPU_PP_SENSOR_GPU_LOAD, 871 (void *)&ui32, &ui32_size)) { 872 return -EINVAL; 873 } 874 break; 875 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 876 /* get average GPU power */ 877 if (amdgpu_dpm_read_sensor(adev, 878 AMDGPU_PP_SENSOR_GPU_POWER, 879 (void *)&ui32, &ui32_size)) { 880 return -EINVAL; 881 } 882 ui32 >>= 8; 883 break; 884 case AMDGPU_INFO_SENSOR_VDDNB: 885 /* get VDDNB in millivolts */ 886 if (amdgpu_dpm_read_sensor(adev, 887 AMDGPU_PP_SENSOR_VDDNB, 888 (void *)&ui32, &ui32_size)) { 889 return -EINVAL; 890 } 891 break; 892 case AMDGPU_INFO_SENSOR_VDDGFX: 893 /* get VDDGFX in millivolts */ 894 if (amdgpu_dpm_read_sensor(adev, 895 AMDGPU_PP_SENSOR_VDDGFX, 896 (void *)&ui32, &ui32_size)) { 897 return -EINVAL; 898 } 899 break; 900 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 901 /* get stable pstate sclk in Mhz */ 902 if (amdgpu_dpm_read_sensor(adev, 903 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 904 (void *)&ui32, &ui32_size)) { 905 return -EINVAL; 906 } 907 ui32 /= 100; 908 break; 909 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 910 /* get stable pstate mclk in Mhz */ 911 if (amdgpu_dpm_read_sensor(adev, 912 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 913 (void *)&ui32, &ui32_size)) { 914 return -EINVAL; 915 } 916 ui32 /= 100; 917 break; 918 default: 919 DRM_DEBUG_KMS("Invalid request %d\n", 920 info->sensor_info.type); 921 return -EINVAL; 922 } 923 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 924 } 925 case AMDGPU_INFO_VRAM_LOST_COUNTER: 926 ui32 = atomic_read(&adev->vram_lost_counter); 927 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 928 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 929 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 930 uint64_t ras_mask; 931 932 if (!ras) 933 return -EINVAL; 934 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 935 936 return copy_to_user(out, &ras_mask, 937 min_t(u64, size, sizeof(ras_mask))) ? 938 -EFAULT : 0; 939 } 940 default: 941 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 942 return -EINVAL; 943 } 944 return 0; 945 } 946 947 948 /* 949 * Outdated mess for old drm with Xorg being in charge (void function now). 950 */ 951 /** 952 * amdgpu_driver_lastclose_kms - drm callback for last close 953 * 954 * @dev: drm dev pointer 955 * 956 * Switch vga_switcheroo state after last close (all asics). 957 */ 958 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 959 { 960 drm_fb_helper_lastclose(dev); 961 vga_switcheroo_process_delayed_switch(); 962 } 963 964 /** 965 * amdgpu_driver_open_kms - drm callback for open 966 * 967 * @dev: drm dev pointer 968 * @file_priv: drm file 969 * 970 * On device open, init vm on cayman+ (all asics). 971 * Returns 0 on success, error on failure. 972 */ 973 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 974 { 975 struct amdgpu_device *adev = dev->dev_private; 976 struct amdgpu_fpriv *fpriv; 977 int r, pasid; 978 979 /* Ensure IB tests are run on ring */ 980 flush_delayed_work(&adev->delayed_init_work); 981 982 983 if (amdgpu_ras_intr_triggered()) { 984 DRM_ERROR("RAS Intr triggered, device disabled!!"); 985 return -EHWPOISON; 986 } 987 988 file_priv->driver_priv = NULL; 989 990 r = pm_runtime_get_sync(dev->dev); 991 if (r < 0) 992 return r; 993 994 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 995 if (unlikely(!fpriv)) { 996 r = -ENOMEM; 997 goto out_suspend; 998 } 999 1000 pasid = amdgpu_pasid_alloc(16); 1001 if (pasid < 0) { 1002 dev_warn(adev->dev, "No more PASIDs available!"); 1003 pasid = 0; 1004 } 1005 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1006 if (r) 1007 goto error_pasid; 1008 1009 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1010 if (!fpriv->prt_va) { 1011 r = -ENOMEM; 1012 goto error_vm; 1013 } 1014 1015 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1016 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1017 1018 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1019 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1020 if (r) 1021 goto error_vm; 1022 } 1023 1024 mutex_init(&fpriv->bo_list_lock); 1025 idr_init(&fpriv->bo_list_handles); 1026 1027 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1028 1029 file_priv->driver_priv = fpriv; 1030 goto out_suspend; 1031 1032 error_vm: 1033 amdgpu_vm_fini(adev, &fpriv->vm); 1034 1035 error_pasid: 1036 if (pasid) 1037 amdgpu_pasid_free(pasid); 1038 1039 kfree(fpriv); 1040 1041 out_suspend: 1042 pm_runtime_mark_last_busy(dev->dev); 1043 pm_runtime_put_autosuspend(dev->dev); 1044 1045 return r; 1046 } 1047 1048 /** 1049 * amdgpu_driver_postclose_kms - drm callback for post close 1050 * 1051 * @dev: drm dev pointer 1052 * @file_priv: drm file 1053 * 1054 * On device post close, tear down vm on cayman+ (all asics). 1055 */ 1056 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1057 struct drm_file *file_priv) 1058 { 1059 struct amdgpu_device *adev = dev->dev_private; 1060 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1061 struct amdgpu_bo_list *list; 1062 struct amdgpu_bo *pd; 1063 unsigned int pasid; 1064 int handle; 1065 1066 if (!fpriv) 1067 return; 1068 1069 pm_runtime_get_sync(dev->dev); 1070 1071 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1072 amdgpu_uvd_free_handles(adev, file_priv); 1073 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1074 amdgpu_vce_free_handles(adev, file_priv); 1075 1076 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1077 1078 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1079 /* TODO: how to handle reserve failure */ 1080 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1081 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1082 fpriv->csa_va = NULL; 1083 amdgpu_bo_unreserve(adev->virt.csa_obj); 1084 } 1085 1086 pasid = fpriv->vm.pasid; 1087 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1088 1089 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1090 amdgpu_vm_fini(adev, &fpriv->vm); 1091 1092 if (pasid) 1093 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1094 amdgpu_bo_unref(&pd); 1095 1096 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1097 amdgpu_bo_list_put(list); 1098 1099 idr_destroy(&fpriv->bo_list_handles); 1100 mutex_destroy(&fpriv->bo_list_lock); 1101 1102 kfree(fpriv); 1103 file_priv->driver_priv = NULL; 1104 1105 pm_runtime_mark_last_busy(dev->dev); 1106 pm_runtime_put_autosuspend(dev->dev); 1107 } 1108 1109 /* 1110 * VBlank related functions. 1111 */ 1112 /** 1113 * amdgpu_get_vblank_counter_kms - get frame count 1114 * 1115 * @crtc: crtc to get the frame count from 1116 * 1117 * Gets the frame count on the requested crtc (all asics). 1118 * Returns frame count on success, -EINVAL on failure. 1119 */ 1120 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1121 { 1122 struct drm_device *dev = crtc->dev; 1123 unsigned int pipe = crtc->index; 1124 struct amdgpu_device *adev = dev->dev_private; 1125 int vpos, hpos, stat; 1126 u32 count; 1127 1128 if (pipe >= adev->mode_info.num_crtc) { 1129 DRM_ERROR("Invalid crtc %u\n", pipe); 1130 return -EINVAL; 1131 } 1132 1133 /* The hw increments its frame counter at start of vsync, not at start 1134 * of vblank, as is required by DRM core vblank counter handling. 1135 * Cook the hw count here to make it appear to the caller as if it 1136 * incremented at start of vblank. We measure distance to start of 1137 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1138 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1139 * result by 1 to give the proper appearance to caller. 1140 */ 1141 if (adev->mode_info.crtcs[pipe]) { 1142 /* Repeat readout if needed to provide stable result if 1143 * we cross start of vsync during the queries. 1144 */ 1145 do { 1146 count = amdgpu_display_vblank_get_counter(adev, pipe); 1147 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1148 * vpos as distance to start of vblank, instead of 1149 * regular vertical scanout pos. 1150 */ 1151 stat = amdgpu_display_get_crtc_scanoutpos( 1152 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1153 &vpos, &hpos, NULL, NULL, 1154 &adev->mode_info.crtcs[pipe]->base.hwmode); 1155 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1156 1157 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1158 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1159 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1160 } else { 1161 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1162 pipe, vpos); 1163 1164 /* Bump counter if we are at >= leading edge of vblank, 1165 * but before vsync where vpos would turn negative and 1166 * the hw counter really increments. 1167 */ 1168 if (vpos >= 0) 1169 count++; 1170 } 1171 } else { 1172 /* Fallback to use value as is. */ 1173 count = amdgpu_display_vblank_get_counter(adev, pipe); 1174 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1175 } 1176 1177 return count; 1178 } 1179 1180 /** 1181 * amdgpu_enable_vblank_kms - enable vblank interrupt 1182 * 1183 * @crtc: crtc to enable vblank interrupt for 1184 * 1185 * Enable the interrupt on the requested crtc (all asics). 1186 * Returns 0 on success, -EINVAL on failure. 1187 */ 1188 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1189 { 1190 struct drm_device *dev = crtc->dev; 1191 unsigned int pipe = crtc->index; 1192 struct amdgpu_device *adev = dev->dev_private; 1193 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1194 1195 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1196 } 1197 1198 /** 1199 * amdgpu_disable_vblank_kms - disable vblank interrupt 1200 * 1201 * @crtc: crtc to disable vblank interrupt for 1202 * 1203 * Disable the interrupt on the requested crtc (all asics). 1204 */ 1205 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1206 { 1207 struct drm_device *dev = crtc->dev; 1208 unsigned int pipe = crtc->index; 1209 struct amdgpu_device *adev = dev->dev_private; 1210 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1211 1212 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1213 } 1214 1215 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1216 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1217 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1218 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1219 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1220 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1221 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1222 /* KMS */ 1223 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1224 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1225 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1226 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1227 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1228 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1229 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1230 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1231 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1232 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1233 }; 1234 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1235 1236 /* 1237 * Debugfs info 1238 */ 1239 #if defined(CONFIG_DEBUG_FS) 1240 1241 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1242 { 1243 struct drm_info_node *node = (struct drm_info_node *) m->private; 1244 struct drm_device *dev = node->minor->dev; 1245 struct amdgpu_device *adev = dev->dev_private; 1246 struct drm_amdgpu_info_firmware fw_info; 1247 struct drm_amdgpu_query_fw query_fw; 1248 struct atom_context *ctx = adev->mode_info.atom_context; 1249 int ret, i; 1250 1251 /* VCE */ 1252 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1253 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1254 if (ret) 1255 return ret; 1256 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1257 fw_info.feature, fw_info.ver); 1258 1259 /* UVD */ 1260 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1261 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1262 if (ret) 1263 return ret; 1264 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1265 fw_info.feature, fw_info.ver); 1266 1267 /* GMC */ 1268 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1269 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1270 if (ret) 1271 return ret; 1272 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1273 fw_info.feature, fw_info.ver); 1274 1275 /* ME */ 1276 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1277 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1278 if (ret) 1279 return ret; 1280 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1281 fw_info.feature, fw_info.ver); 1282 1283 /* PFP */ 1284 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1285 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1286 if (ret) 1287 return ret; 1288 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1289 fw_info.feature, fw_info.ver); 1290 1291 /* CE */ 1292 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1293 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1294 if (ret) 1295 return ret; 1296 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1297 fw_info.feature, fw_info.ver); 1298 1299 /* RLC */ 1300 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1301 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1302 if (ret) 1303 return ret; 1304 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1305 fw_info.feature, fw_info.ver); 1306 1307 /* RLC SAVE RESTORE LIST CNTL */ 1308 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1309 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1310 if (ret) 1311 return ret; 1312 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1313 fw_info.feature, fw_info.ver); 1314 1315 /* RLC SAVE RESTORE LIST GPM MEM */ 1316 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1317 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1318 if (ret) 1319 return ret; 1320 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1321 fw_info.feature, fw_info.ver); 1322 1323 /* RLC SAVE RESTORE LIST SRM MEM */ 1324 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1325 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1326 if (ret) 1327 return ret; 1328 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1329 fw_info.feature, fw_info.ver); 1330 1331 /* MEC */ 1332 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1333 query_fw.index = 0; 1334 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1335 if (ret) 1336 return ret; 1337 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1338 fw_info.feature, fw_info.ver); 1339 1340 /* MEC2 */ 1341 if (adev->asic_type == CHIP_KAVERI || 1342 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1343 query_fw.index = 1; 1344 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1345 if (ret) 1346 return ret; 1347 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1348 fw_info.feature, fw_info.ver); 1349 } 1350 1351 /* PSP SOS */ 1352 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1353 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1354 if (ret) 1355 return ret; 1356 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1357 fw_info.feature, fw_info.ver); 1358 1359 1360 /* PSP ASD */ 1361 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1362 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1363 if (ret) 1364 return ret; 1365 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1366 fw_info.feature, fw_info.ver); 1367 1368 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1369 for (i = 0; i < 2; i++) { 1370 query_fw.index = i; 1371 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1372 if (ret) 1373 continue; 1374 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1375 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1376 } 1377 1378 /* SMC */ 1379 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1380 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1381 if (ret) 1382 return ret; 1383 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1384 fw_info.feature, fw_info.ver); 1385 1386 /* SDMA */ 1387 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1388 for (i = 0; i < adev->sdma.num_instances; i++) { 1389 query_fw.index = i; 1390 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1391 if (ret) 1392 return ret; 1393 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1394 i, fw_info.feature, fw_info.ver); 1395 } 1396 1397 /* VCN */ 1398 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1399 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1400 if (ret) 1401 return ret; 1402 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1403 fw_info.feature, fw_info.ver); 1404 1405 /* DMCU */ 1406 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1407 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1408 if (ret) 1409 return ret; 1410 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1411 fw_info.feature, fw_info.ver); 1412 1413 /* DMCUB */ 1414 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1415 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1416 if (ret) 1417 return ret; 1418 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1419 fw_info.feature, fw_info.ver); 1420 1421 1422 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1423 1424 return 0; 1425 } 1426 1427 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1428 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1429 }; 1430 #endif 1431 1432 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1433 { 1434 #if defined(CONFIG_DEBUG_FS) 1435 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1436 ARRAY_SIZE(amdgpu_firmware_info_list)); 1437 #else 1438 return 0; 1439 #endif 1440 } 1441