1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 98 amdgpu_device_fini(adev); 99 100 done_free: 101 kfree(adev); 102 dev->dev_private = NULL; 103 } 104 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 106 { 107 struct amdgpu_gpu_instance *gpu_instance; 108 109 mutex_lock(&mgpu_info.mutex); 110 111 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 112 DRM_ERROR("Cannot register more gpu instance\n"); 113 mutex_unlock(&mgpu_info.mutex); 114 return; 115 } 116 117 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 118 gpu_instance->adev = adev; 119 gpu_instance->mgpu_fan_enabled = 0; 120 121 mgpu_info.num_gpu++; 122 if (adev->flags & AMD_IS_APU) 123 mgpu_info.num_apu++; 124 else 125 mgpu_info.num_dgpu++; 126 127 mutex_unlock(&mgpu_info.mutex); 128 } 129 130 /** 131 * amdgpu_driver_load_kms - Main load function for KMS. 132 * 133 * @dev: drm dev pointer 134 * @flags: device flags 135 * 136 * This is the main load function for KMS (all asics). 137 * Returns 0 on success, error on failure. 138 */ 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 140 { 141 struct amdgpu_device *adev; 142 int r, acpi_status; 143 144 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 145 if (adev == NULL) { 146 return -ENOMEM; 147 } 148 dev->dev_private = (void *)adev; 149 150 if (amdgpu_has_atpx() && 151 (amdgpu_is_atpx_hybrid() || 152 amdgpu_has_atpx_dgpu_power_cntl()) && 153 ((flags & AMD_IS_APU) == 0) && 154 !pci_is_thunderbolt_attached(dev->pdev)) 155 flags |= AMD_IS_PX; 156 157 /* amdgpu_device_init should report only fatal error 158 * like memory allocation failure or iomapping failure, 159 * or memory manager initialization failure, it must 160 * properly initialize the GPU MC controller and permit 161 * VRAM allocation 162 */ 163 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 164 if (r) { 165 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 166 goto out; 167 } 168 169 if (amdgpu_device_supports_boco(dev) && 170 (amdgpu_runtime_pm != 0)) /* enable runpm by default for boco */ 171 adev->runpm = true; 172 else if (amdgpu_device_supports_baco(dev) && 173 (amdgpu_runtime_pm != 0) && 174 (adev->asic_type >= CHIP_TOPAZ) && 175 (adev->asic_type != CHIP_VEGA10) && 176 (adev->asic_type != CHIP_VEGA20) && 177 (adev->asic_type != CHIP_ARCTURUS)) /* enable runpm on VI+ */ 178 adev->runpm = true; 179 else if (amdgpu_device_supports_baco(dev) && 180 (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 on CI */ 181 adev->runpm = true; 182 183 /* Call ACPI methods: require modeset init 184 * but failure is not fatal 185 */ 186 187 acpi_status = amdgpu_acpi_init(adev); 188 if (acpi_status) 189 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 190 191 if (adev->runpm) { 192 /* only need to skip on ATPX */ 193 if (amdgpu_device_supports_boco(dev) && 194 !amdgpu_is_atpx_hybrid()) 195 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 196 pm_runtime_use_autosuspend(dev->dev); 197 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 198 pm_runtime_allow(dev->dev); 199 pm_runtime_mark_last_busy(dev->dev); 200 pm_runtime_put_autosuspend(dev->dev); 201 } 202 203 out: 204 if (r) { 205 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 206 if (adev->rmmio && adev->runpm) 207 pm_runtime_put_noidle(dev->dev); 208 amdgpu_driver_unload_kms(dev); 209 } 210 211 return r; 212 } 213 214 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 215 struct drm_amdgpu_query_fw *query_fw, 216 struct amdgpu_device *adev) 217 { 218 switch (query_fw->fw_type) { 219 case AMDGPU_INFO_FW_VCE: 220 fw_info->ver = adev->vce.fw_version; 221 fw_info->feature = adev->vce.fb_version; 222 break; 223 case AMDGPU_INFO_FW_UVD: 224 fw_info->ver = adev->uvd.fw_version; 225 fw_info->feature = 0; 226 break; 227 case AMDGPU_INFO_FW_VCN: 228 fw_info->ver = adev->vcn.fw_version; 229 fw_info->feature = 0; 230 break; 231 case AMDGPU_INFO_FW_GMC: 232 fw_info->ver = adev->gmc.fw_version; 233 fw_info->feature = 0; 234 break; 235 case AMDGPU_INFO_FW_GFX_ME: 236 fw_info->ver = adev->gfx.me_fw_version; 237 fw_info->feature = adev->gfx.me_feature_version; 238 break; 239 case AMDGPU_INFO_FW_GFX_PFP: 240 fw_info->ver = adev->gfx.pfp_fw_version; 241 fw_info->feature = adev->gfx.pfp_feature_version; 242 break; 243 case AMDGPU_INFO_FW_GFX_CE: 244 fw_info->ver = adev->gfx.ce_fw_version; 245 fw_info->feature = adev->gfx.ce_feature_version; 246 break; 247 case AMDGPU_INFO_FW_GFX_RLC: 248 fw_info->ver = adev->gfx.rlc_fw_version; 249 fw_info->feature = adev->gfx.rlc_feature_version; 250 break; 251 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 252 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 253 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 256 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 257 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 260 fw_info->ver = adev->gfx.rlc_srls_fw_version; 261 fw_info->feature = adev->gfx.rlc_srls_feature_version; 262 break; 263 case AMDGPU_INFO_FW_GFX_MEC: 264 if (query_fw->index == 0) { 265 fw_info->ver = adev->gfx.mec_fw_version; 266 fw_info->feature = adev->gfx.mec_feature_version; 267 } else if (query_fw->index == 1) { 268 fw_info->ver = adev->gfx.mec2_fw_version; 269 fw_info->feature = adev->gfx.mec2_feature_version; 270 } else 271 return -EINVAL; 272 break; 273 case AMDGPU_INFO_FW_SMC: 274 fw_info->ver = adev->pm.fw_version; 275 fw_info->feature = 0; 276 break; 277 case AMDGPU_INFO_FW_TA: 278 if (query_fw->index > 1) 279 return -EINVAL; 280 if (query_fw->index == 0) { 281 fw_info->ver = adev->psp.ta_fw_version; 282 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 283 } else { 284 fw_info->ver = adev->psp.ta_fw_version; 285 fw_info->feature = adev->psp.ta_ras_ucode_version; 286 } 287 break; 288 case AMDGPU_INFO_FW_SDMA: 289 if (query_fw->index >= adev->sdma.num_instances) 290 return -EINVAL; 291 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 292 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 293 break; 294 case AMDGPU_INFO_FW_SOS: 295 fw_info->ver = adev->psp.sos_fw_version; 296 fw_info->feature = adev->psp.sos_feature_version; 297 break; 298 case AMDGPU_INFO_FW_ASD: 299 fw_info->ver = adev->psp.asd_fw_version; 300 fw_info->feature = adev->psp.asd_feature_version; 301 break; 302 case AMDGPU_INFO_FW_DMCU: 303 fw_info->ver = adev->dm.dmcu_fw_version; 304 fw_info->feature = 0; 305 break; 306 case AMDGPU_INFO_FW_DMCUB: 307 fw_info->ver = adev->dm.dmcub_fw_version; 308 fw_info->feature = 0; 309 break; 310 default: 311 return -EINVAL; 312 } 313 return 0; 314 } 315 316 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 317 struct drm_amdgpu_info *info, 318 struct drm_amdgpu_info_hw_ip *result) 319 { 320 uint32_t ib_start_alignment = 0; 321 uint32_t ib_size_alignment = 0; 322 enum amd_ip_block_type type; 323 unsigned int num_rings = 0; 324 unsigned int i, j; 325 326 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 327 return -EINVAL; 328 329 switch (info->query_hw_ip.type) { 330 case AMDGPU_HW_IP_GFX: 331 type = AMD_IP_BLOCK_TYPE_GFX; 332 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 333 if (adev->gfx.gfx_ring[i].sched.ready) 334 ++num_rings; 335 ib_start_alignment = 32; 336 ib_size_alignment = 32; 337 break; 338 case AMDGPU_HW_IP_COMPUTE: 339 type = AMD_IP_BLOCK_TYPE_GFX; 340 for (i = 0; i < adev->gfx.num_compute_rings; i++) 341 if (adev->gfx.compute_ring[i].sched.ready) 342 ++num_rings; 343 ib_start_alignment = 32; 344 ib_size_alignment = 32; 345 break; 346 case AMDGPU_HW_IP_DMA: 347 type = AMD_IP_BLOCK_TYPE_SDMA; 348 for (i = 0; i < adev->sdma.num_instances; i++) 349 if (adev->sdma.instance[i].ring.sched.ready) 350 ++num_rings; 351 ib_start_alignment = 256; 352 ib_size_alignment = 4; 353 break; 354 case AMDGPU_HW_IP_UVD: 355 type = AMD_IP_BLOCK_TYPE_UVD; 356 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 357 if (adev->uvd.harvest_config & (1 << i)) 358 continue; 359 360 if (adev->uvd.inst[i].ring.sched.ready) 361 ++num_rings; 362 } 363 ib_start_alignment = 64; 364 ib_size_alignment = 64; 365 break; 366 case AMDGPU_HW_IP_VCE: 367 type = AMD_IP_BLOCK_TYPE_VCE; 368 for (i = 0; i < adev->vce.num_rings; i++) 369 if (adev->vce.ring[i].sched.ready) 370 ++num_rings; 371 ib_start_alignment = 4; 372 ib_size_alignment = 1; 373 break; 374 case AMDGPU_HW_IP_UVD_ENC: 375 type = AMD_IP_BLOCK_TYPE_UVD; 376 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 377 if (adev->uvd.harvest_config & (1 << i)) 378 continue; 379 380 for (j = 0; j < adev->uvd.num_enc_rings; j++) 381 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 382 ++num_rings; 383 } 384 ib_start_alignment = 64; 385 ib_size_alignment = 64; 386 break; 387 case AMDGPU_HW_IP_VCN_DEC: 388 type = AMD_IP_BLOCK_TYPE_VCN; 389 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 390 if (adev->uvd.harvest_config & (1 << i)) 391 continue; 392 393 if (adev->vcn.inst[i].ring_dec.sched.ready) 394 ++num_rings; 395 } 396 ib_start_alignment = 16; 397 ib_size_alignment = 16; 398 break; 399 case AMDGPU_HW_IP_VCN_ENC: 400 type = AMD_IP_BLOCK_TYPE_VCN; 401 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 402 if (adev->uvd.harvest_config & (1 << i)) 403 continue; 404 405 for (j = 0; j < adev->vcn.num_enc_rings; j++) 406 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 407 ++num_rings; 408 } 409 ib_start_alignment = 64; 410 ib_size_alignment = 1; 411 break; 412 case AMDGPU_HW_IP_VCN_JPEG: 413 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 414 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 415 416 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 417 if (adev->jpeg.harvest_config & (1 << i)) 418 continue; 419 420 if (adev->jpeg.inst[i].ring_dec.sched.ready) 421 ++num_rings; 422 } 423 ib_start_alignment = 16; 424 ib_size_alignment = 16; 425 break; 426 default: 427 return -EINVAL; 428 } 429 430 for (i = 0; i < adev->num_ip_blocks; i++) 431 if (adev->ip_blocks[i].version->type == type && 432 adev->ip_blocks[i].status.valid) 433 break; 434 435 if (i == adev->num_ip_blocks) 436 return 0; 437 438 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 439 num_rings); 440 441 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 442 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 443 result->capabilities_flags = 0; 444 result->available_rings = (1 << num_rings) - 1; 445 result->ib_start_alignment = ib_start_alignment; 446 result->ib_size_alignment = ib_size_alignment; 447 return 0; 448 } 449 450 /* 451 * Userspace get information ioctl 452 */ 453 /** 454 * amdgpu_info_ioctl - answer a device specific request. 455 * 456 * @adev: amdgpu device pointer 457 * @data: request object 458 * @filp: drm filp 459 * 460 * This function is used to pass device specific parameters to the userspace 461 * drivers. Examples include: pci device id, pipeline parms, tiling params, 462 * etc. (all asics). 463 * Returns 0 on success, -EINVAL on failure. 464 */ 465 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 466 { 467 struct amdgpu_device *adev = dev->dev_private; 468 struct drm_amdgpu_info *info = data; 469 struct amdgpu_mode_info *minfo = &adev->mode_info; 470 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 471 uint32_t size = info->return_size; 472 struct drm_crtc *crtc; 473 uint32_t ui32 = 0; 474 uint64_t ui64 = 0; 475 int i, found; 476 int ui32_size = sizeof(ui32); 477 478 if (!info->return_size || !info->return_pointer) 479 return -EINVAL; 480 481 switch (info->query) { 482 case AMDGPU_INFO_ACCEL_WORKING: 483 ui32 = adev->accel_working; 484 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 485 case AMDGPU_INFO_CRTC_FROM_ID: 486 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 487 crtc = (struct drm_crtc *)minfo->crtcs[i]; 488 if (crtc && crtc->base.id == info->mode_crtc.id) { 489 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 490 ui32 = amdgpu_crtc->crtc_id; 491 found = 1; 492 break; 493 } 494 } 495 if (!found) { 496 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 497 return -EINVAL; 498 } 499 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 500 case AMDGPU_INFO_HW_IP_INFO: { 501 struct drm_amdgpu_info_hw_ip ip = {}; 502 int ret; 503 504 ret = amdgpu_hw_ip_info(adev, info, &ip); 505 if (ret) 506 return ret; 507 508 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 509 return ret ? -EFAULT : 0; 510 } 511 case AMDGPU_INFO_HW_IP_COUNT: { 512 enum amd_ip_block_type type; 513 uint32_t count = 0; 514 515 switch (info->query_hw_ip.type) { 516 case AMDGPU_HW_IP_GFX: 517 type = AMD_IP_BLOCK_TYPE_GFX; 518 break; 519 case AMDGPU_HW_IP_COMPUTE: 520 type = AMD_IP_BLOCK_TYPE_GFX; 521 break; 522 case AMDGPU_HW_IP_DMA: 523 type = AMD_IP_BLOCK_TYPE_SDMA; 524 break; 525 case AMDGPU_HW_IP_UVD: 526 type = AMD_IP_BLOCK_TYPE_UVD; 527 break; 528 case AMDGPU_HW_IP_VCE: 529 type = AMD_IP_BLOCK_TYPE_VCE; 530 break; 531 case AMDGPU_HW_IP_UVD_ENC: 532 type = AMD_IP_BLOCK_TYPE_UVD; 533 break; 534 case AMDGPU_HW_IP_VCN_DEC: 535 case AMDGPU_HW_IP_VCN_ENC: 536 type = AMD_IP_BLOCK_TYPE_VCN; 537 break; 538 case AMDGPU_HW_IP_VCN_JPEG: 539 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 540 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 541 break; 542 default: 543 return -EINVAL; 544 } 545 546 for (i = 0; i < adev->num_ip_blocks; i++) 547 if (adev->ip_blocks[i].version->type == type && 548 adev->ip_blocks[i].status.valid && 549 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 550 count++; 551 552 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 553 } 554 case AMDGPU_INFO_TIMESTAMP: 555 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 556 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 557 case AMDGPU_INFO_FW_VERSION: { 558 struct drm_amdgpu_info_firmware fw_info; 559 int ret; 560 561 /* We only support one instance of each IP block right now. */ 562 if (info->query_fw.ip_instance != 0) 563 return -EINVAL; 564 565 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 566 if (ret) 567 return ret; 568 569 return copy_to_user(out, &fw_info, 570 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 571 } 572 case AMDGPU_INFO_NUM_BYTES_MOVED: 573 ui64 = atomic64_read(&adev->num_bytes_moved); 574 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 575 case AMDGPU_INFO_NUM_EVICTIONS: 576 ui64 = atomic64_read(&adev->num_evictions); 577 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 578 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 579 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 580 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 581 case AMDGPU_INFO_VRAM_USAGE: 582 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 583 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 584 case AMDGPU_INFO_VIS_VRAM_USAGE: 585 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 586 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 587 case AMDGPU_INFO_GTT_USAGE: 588 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 589 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 590 case AMDGPU_INFO_GDS_CONFIG: { 591 struct drm_amdgpu_info_gds gds_info; 592 593 memset(&gds_info, 0, sizeof(gds_info)); 594 gds_info.compute_partition_size = adev->gds.gds_size; 595 gds_info.gds_total_size = adev->gds.gds_size; 596 gds_info.gws_per_compute_partition = adev->gds.gws_size; 597 gds_info.oa_per_compute_partition = adev->gds.oa_size; 598 return copy_to_user(out, &gds_info, 599 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 600 } 601 case AMDGPU_INFO_VRAM_GTT: { 602 struct drm_amdgpu_info_vram_gtt vram_gtt; 603 604 vram_gtt.vram_size = adev->gmc.real_vram_size - 605 atomic64_read(&adev->vram_pin_size) - 606 AMDGPU_VM_RESERVED_VRAM; 607 vram_gtt.vram_cpu_accessible_size = 608 min(adev->gmc.visible_vram_size - 609 atomic64_read(&adev->visible_pin_size), 610 vram_gtt.vram_size); 611 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 612 vram_gtt.gtt_size *= PAGE_SIZE; 613 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 614 return copy_to_user(out, &vram_gtt, 615 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 616 } 617 case AMDGPU_INFO_MEMORY: { 618 struct drm_amdgpu_memory_info mem; 619 620 memset(&mem, 0, sizeof(mem)); 621 mem.vram.total_heap_size = adev->gmc.real_vram_size; 622 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 623 atomic64_read(&adev->vram_pin_size) - 624 AMDGPU_VM_RESERVED_VRAM; 625 mem.vram.heap_usage = 626 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 627 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 628 629 mem.cpu_accessible_vram.total_heap_size = 630 adev->gmc.visible_vram_size; 631 mem.cpu_accessible_vram.usable_heap_size = 632 min(adev->gmc.visible_vram_size - 633 atomic64_read(&adev->visible_pin_size), 634 mem.vram.usable_heap_size); 635 mem.cpu_accessible_vram.heap_usage = 636 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 637 mem.cpu_accessible_vram.max_allocation = 638 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 639 640 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 641 mem.gtt.total_heap_size *= PAGE_SIZE; 642 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 643 atomic64_read(&adev->gart_pin_size); 644 mem.gtt.heap_usage = 645 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 646 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 647 648 return copy_to_user(out, &mem, 649 min((size_t)size, sizeof(mem))) 650 ? -EFAULT : 0; 651 } 652 case AMDGPU_INFO_READ_MMR_REG: { 653 unsigned n, alloc_size; 654 uint32_t *regs; 655 unsigned se_num = (info->read_mmr_reg.instance >> 656 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 657 AMDGPU_INFO_MMR_SE_INDEX_MASK; 658 unsigned sh_num = (info->read_mmr_reg.instance >> 659 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 660 AMDGPU_INFO_MMR_SH_INDEX_MASK; 661 662 /* set full masks if the userspace set all bits 663 * in the bitfields */ 664 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 665 se_num = 0xffffffff; 666 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 667 sh_num = 0xffffffff; 668 669 if (info->read_mmr_reg.count > 128) 670 return -EINVAL; 671 672 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 673 if (!regs) 674 return -ENOMEM; 675 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 676 677 amdgpu_gfx_off_ctrl(adev, false); 678 for (i = 0; i < info->read_mmr_reg.count; i++) { 679 if (amdgpu_asic_read_register(adev, se_num, sh_num, 680 info->read_mmr_reg.dword_offset + i, 681 ®s[i])) { 682 DRM_DEBUG_KMS("unallowed offset %#x\n", 683 info->read_mmr_reg.dword_offset + i); 684 kfree(regs); 685 amdgpu_gfx_off_ctrl(adev, true); 686 return -EFAULT; 687 } 688 } 689 amdgpu_gfx_off_ctrl(adev, true); 690 n = copy_to_user(out, regs, min(size, alloc_size)); 691 kfree(regs); 692 return n ? -EFAULT : 0; 693 } 694 case AMDGPU_INFO_DEV_INFO: { 695 struct drm_amdgpu_info_device dev_info = {}; 696 uint64_t vm_size; 697 698 dev_info.device_id = dev->pdev->device; 699 dev_info.chip_rev = adev->rev_id; 700 dev_info.external_rev = adev->external_rev_id; 701 dev_info.pci_rev = dev->pdev->revision; 702 dev_info.family = adev->family; 703 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 704 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 705 /* return all clocks in KHz */ 706 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 707 if (adev->pm.dpm_enabled) { 708 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 709 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 710 } else { 711 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 712 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 713 } 714 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 715 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 716 adev->gfx.config.max_shader_engines; 717 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 718 dev_info._pad = 0; 719 dev_info.ids_flags = 0; 720 if (adev->flags & AMD_IS_APU) 721 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 722 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 723 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 724 725 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 726 vm_size -= AMDGPU_VA_RESERVED_SIZE; 727 728 /* Older VCE FW versions are buggy and can handle only 40bits */ 729 if (adev->vce.fw_version && 730 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 731 vm_size = min(vm_size, 1ULL << 40); 732 733 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 734 dev_info.virtual_address_max = 735 min(vm_size, AMDGPU_GMC_HOLE_START); 736 737 if (vm_size > AMDGPU_GMC_HOLE_START) { 738 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 739 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 740 } 741 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 742 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 743 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 744 dev_info.cu_active_number = adev->gfx.cu_info.number; 745 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 746 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 747 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 748 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 749 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 750 sizeof(adev->gfx.cu_info.bitmap)); 751 dev_info.vram_type = adev->gmc.vram_type; 752 dev_info.vram_bit_width = adev->gmc.vram_width; 753 dev_info.vce_harvest_config = adev->vce.harvest_config; 754 dev_info.gc_double_offchip_lds_buf = 755 adev->gfx.config.double_offchip_lds_buf; 756 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 757 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 758 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 759 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 760 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 761 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 762 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 763 764 if (adev->family >= AMDGPU_FAMILY_NV) 765 dev_info.pa_sc_tile_steering_override = 766 adev->gfx.config.pa_sc_tile_steering_override; 767 768 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 769 770 return copy_to_user(out, &dev_info, 771 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 772 } 773 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 774 unsigned i; 775 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 776 struct amd_vce_state *vce_state; 777 778 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 779 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 780 if (vce_state) { 781 vce_clk_table.entries[i].sclk = vce_state->sclk; 782 vce_clk_table.entries[i].mclk = vce_state->mclk; 783 vce_clk_table.entries[i].eclk = vce_state->evclk; 784 vce_clk_table.num_valid_entries++; 785 } 786 } 787 788 return copy_to_user(out, &vce_clk_table, 789 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 790 } 791 case AMDGPU_INFO_VBIOS: { 792 uint32_t bios_size = adev->bios_size; 793 794 switch (info->vbios_info.type) { 795 case AMDGPU_INFO_VBIOS_SIZE: 796 return copy_to_user(out, &bios_size, 797 min((size_t)size, sizeof(bios_size))) 798 ? -EFAULT : 0; 799 case AMDGPU_INFO_VBIOS_IMAGE: { 800 uint8_t *bios; 801 uint32_t bios_offset = info->vbios_info.offset; 802 803 if (bios_offset >= bios_size) 804 return -EINVAL; 805 806 bios = adev->bios + bios_offset; 807 return copy_to_user(out, bios, 808 min((size_t)size, (size_t)(bios_size - bios_offset))) 809 ? -EFAULT : 0; 810 } 811 default: 812 DRM_DEBUG_KMS("Invalid request %d\n", 813 info->vbios_info.type); 814 return -EINVAL; 815 } 816 } 817 case AMDGPU_INFO_NUM_HANDLES: { 818 struct drm_amdgpu_info_num_handles handle; 819 820 switch (info->query_hw_ip.type) { 821 case AMDGPU_HW_IP_UVD: 822 /* Starting Polaris, we support unlimited UVD handles */ 823 if (adev->asic_type < CHIP_POLARIS10) { 824 handle.uvd_max_handles = adev->uvd.max_handles; 825 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 826 827 return copy_to_user(out, &handle, 828 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 829 } else { 830 return -ENODATA; 831 } 832 833 break; 834 default: 835 return -EINVAL; 836 } 837 } 838 case AMDGPU_INFO_SENSOR: { 839 if (!adev->pm.dpm_enabled) 840 return -ENOENT; 841 842 switch (info->sensor_info.type) { 843 case AMDGPU_INFO_SENSOR_GFX_SCLK: 844 /* get sclk in Mhz */ 845 if (amdgpu_dpm_read_sensor(adev, 846 AMDGPU_PP_SENSOR_GFX_SCLK, 847 (void *)&ui32, &ui32_size)) { 848 return -EINVAL; 849 } 850 ui32 /= 100; 851 break; 852 case AMDGPU_INFO_SENSOR_GFX_MCLK: 853 /* get mclk in Mhz */ 854 if (amdgpu_dpm_read_sensor(adev, 855 AMDGPU_PP_SENSOR_GFX_MCLK, 856 (void *)&ui32, &ui32_size)) { 857 return -EINVAL; 858 } 859 ui32 /= 100; 860 break; 861 case AMDGPU_INFO_SENSOR_GPU_TEMP: 862 /* get temperature in millidegrees C */ 863 if (amdgpu_dpm_read_sensor(adev, 864 AMDGPU_PP_SENSOR_GPU_TEMP, 865 (void *)&ui32, &ui32_size)) { 866 return -EINVAL; 867 } 868 break; 869 case AMDGPU_INFO_SENSOR_GPU_LOAD: 870 /* get GPU load */ 871 if (amdgpu_dpm_read_sensor(adev, 872 AMDGPU_PP_SENSOR_GPU_LOAD, 873 (void *)&ui32, &ui32_size)) { 874 return -EINVAL; 875 } 876 break; 877 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 878 /* get average GPU power */ 879 if (amdgpu_dpm_read_sensor(adev, 880 AMDGPU_PP_SENSOR_GPU_POWER, 881 (void *)&ui32, &ui32_size)) { 882 return -EINVAL; 883 } 884 ui32 >>= 8; 885 break; 886 case AMDGPU_INFO_SENSOR_VDDNB: 887 /* get VDDNB in millivolts */ 888 if (amdgpu_dpm_read_sensor(adev, 889 AMDGPU_PP_SENSOR_VDDNB, 890 (void *)&ui32, &ui32_size)) { 891 return -EINVAL; 892 } 893 break; 894 case AMDGPU_INFO_SENSOR_VDDGFX: 895 /* get VDDGFX in millivolts */ 896 if (amdgpu_dpm_read_sensor(adev, 897 AMDGPU_PP_SENSOR_VDDGFX, 898 (void *)&ui32, &ui32_size)) { 899 return -EINVAL; 900 } 901 break; 902 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 903 /* get stable pstate sclk in Mhz */ 904 if (amdgpu_dpm_read_sensor(adev, 905 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 906 (void *)&ui32, &ui32_size)) { 907 return -EINVAL; 908 } 909 ui32 /= 100; 910 break; 911 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 912 /* get stable pstate mclk in Mhz */ 913 if (amdgpu_dpm_read_sensor(adev, 914 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 915 (void *)&ui32, &ui32_size)) { 916 return -EINVAL; 917 } 918 ui32 /= 100; 919 break; 920 default: 921 DRM_DEBUG_KMS("Invalid request %d\n", 922 info->sensor_info.type); 923 return -EINVAL; 924 } 925 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 926 } 927 case AMDGPU_INFO_VRAM_LOST_COUNTER: 928 ui32 = atomic_read(&adev->vram_lost_counter); 929 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 930 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 931 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 932 uint64_t ras_mask; 933 934 if (!ras) 935 return -EINVAL; 936 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 937 938 return copy_to_user(out, &ras_mask, 939 min_t(u64, size, sizeof(ras_mask))) ? 940 -EFAULT : 0; 941 } 942 default: 943 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 944 return -EINVAL; 945 } 946 return 0; 947 } 948 949 950 /* 951 * Outdated mess for old drm with Xorg being in charge (void function now). 952 */ 953 /** 954 * amdgpu_driver_lastclose_kms - drm callback for last close 955 * 956 * @dev: drm dev pointer 957 * 958 * Switch vga_switcheroo state after last close (all asics). 959 */ 960 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 961 { 962 drm_fb_helper_lastclose(dev); 963 vga_switcheroo_process_delayed_switch(); 964 } 965 966 /** 967 * amdgpu_driver_open_kms - drm callback for open 968 * 969 * @dev: drm dev pointer 970 * @file_priv: drm file 971 * 972 * On device open, init vm on cayman+ (all asics). 973 * Returns 0 on success, error on failure. 974 */ 975 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 976 { 977 struct amdgpu_device *adev = dev->dev_private; 978 struct amdgpu_fpriv *fpriv; 979 int r, pasid; 980 981 /* Ensure IB tests are run on ring */ 982 flush_delayed_work(&adev->delayed_init_work); 983 984 985 if (amdgpu_ras_intr_triggered()) { 986 DRM_ERROR("RAS Intr triggered, device disabled!!"); 987 return -EHWPOISON; 988 } 989 990 file_priv->driver_priv = NULL; 991 992 r = pm_runtime_get_sync(dev->dev); 993 if (r < 0) 994 return r; 995 996 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 997 if (unlikely(!fpriv)) { 998 r = -ENOMEM; 999 goto out_suspend; 1000 } 1001 1002 pasid = amdgpu_pasid_alloc(16); 1003 if (pasid < 0) { 1004 dev_warn(adev->dev, "No more PASIDs available!"); 1005 pasid = 0; 1006 } 1007 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1008 if (r) 1009 goto error_pasid; 1010 1011 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1012 if (!fpriv->prt_va) { 1013 r = -ENOMEM; 1014 goto error_vm; 1015 } 1016 1017 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1018 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1019 1020 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1021 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1022 if (r) 1023 goto error_vm; 1024 } 1025 1026 mutex_init(&fpriv->bo_list_lock); 1027 idr_init(&fpriv->bo_list_handles); 1028 1029 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1030 1031 file_priv->driver_priv = fpriv; 1032 goto out_suspend; 1033 1034 error_vm: 1035 amdgpu_vm_fini(adev, &fpriv->vm); 1036 1037 error_pasid: 1038 if (pasid) 1039 amdgpu_pasid_free(pasid); 1040 1041 kfree(fpriv); 1042 1043 out_suspend: 1044 pm_runtime_mark_last_busy(dev->dev); 1045 pm_runtime_put_autosuspend(dev->dev); 1046 1047 return r; 1048 } 1049 1050 /** 1051 * amdgpu_driver_postclose_kms - drm callback for post close 1052 * 1053 * @dev: drm dev pointer 1054 * @file_priv: drm file 1055 * 1056 * On device post close, tear down vm on cayman+ (all asics). 1057 */ 1058 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1059 struct drm_file *file_priv) 1060 { 1061 struct amdgpu_device *adev = dev->dev_private; 1062 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1063 struct amdgpu_bo_list *list; 1064 struct amdgpu_bo *pd; 1065 unsigned int pasid; 1066 int handle; 1067 1068 if (!fpriv) 1069 return; 1070 1071 pm_runtime_get_sync(dev->dev); 1072 1073 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1074 amdgpu_uvd_free_handles(adev, file_priv); 1075 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1076 amdgpu_vce_free_handles(adev, file_priv); 1077 1078 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1079 1080 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1081 /* TODO: how to handle reserve failure */ 1082 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1083 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1084 fpriv->csa_va = NULL; 1085 amdgpu_bo_unreserve(adev->virt.csa_obj); 1086 } 1087 1088 pasid = fpriv->vm.pasid; 1089 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1090 1091 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1092 amdgpu_vm_fini(adev, &fpriv->vm); 1093 1094 if (pasid) 1095 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1096 amdgpu_bo_unref(&pd); 1097 1098 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1099 amdgpu_bo_list_put(list); 1100 1101 idr_destroy(&fpriv->bo_list_handles); 1102 mutex_destroy(&fpriv->bo_list_lock); 1103 1104 kfree(fpriv); 1105 file_priv->driver_priv = NULL; 1106 1107 pm_runtime_mark_last_busy(dev->dev); 1108 pm_runtime_put_autosuspend(dev->dev); 1109 } 1110 1111 /* 1112 * VBlank related functions. 1113 */ 1114 /** 1115 * amdgpu_get_vblank_counter_kms - get frame count 1116 * 1117 * @crtc: crtc to get the frame count from 1118 * 1119 * Gets the frame count on the requested crtc (all asics). 1120 * Returns frame count on success, -EINVAL on failure. 1121 */ 1122 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1123 { 1124 struct drm_device *dev = crtc->dev; 1125 unsigned int pipe = crtc->index; 1126 struct amdgpu_device *adev = dev->dev_private; 1127 int vpos, hpos, stat; 1128 u32 count; 1129 1130 if (pipe >= adev->mode_info.num_crtc) { 1131 DRM_ERROR("Invalid crtc %u\n", pipe); 1132 return -EINVAL; 1133 } 1134 1135 /* The hw increments its frame counter at start of vsync, not at start 1136 * of vblank, as is required by DRM core vblank counter handling. 1137 * Cook the hw count here to make it appear to the caller as if it 1138 * incremented at start of vblank. We measure distance to start of 1139 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1140 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1141 * result by 1 to give the proper appearance to caller. 1142 */ 1143 if (adev->mode_info.crtcs[pipe]) { 1144 /* Repeat readout if needed to provide stable result if 1145 * we cross start of vsync during the queries. 1146 */ 1147 do { 1148 count = amdgpu_display_vblank_get_counter(adev, pipe); 1149 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1150 * vpos as distance to start of vblank, instead of 1151 * regular vertical scanout pos. 1152 */ 1153 stat = amdgpu_display_get_crtc_scanoutpos( 1154 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1155 &vpos, &hpos, NULL, NULL, 1156 &adev->mode_info.crtcs[pipe]->base.hwmode); 1157 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1158 1159 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1160 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1161 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1162 } else { 1163 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1164 pipe, vpos); 1165 1166 /* Bump counter if we are at >= leading edge of vblank, 1167 * but before vsync where vpos would turn negative and 1168 * the hw counter really increments. 1169 */ 1170 if (vpos >= 0) 1171 count++; 1172 } 1173 } else { 1174 /* Fallback to use value as is. */ 1175 count = amdgpu_display_vblank_get_counter(adev, pipe); 1176 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1177 } 1178 1179 return count; 1180 } 1181 1182 /** 1183 * amdgpu_enable_vblank_kms - enable vblank interrupt 1184 * 1185 * @crtc: crtc to enable vblank interrupt for 1186 * 1187 * Enable the interrupt on the requested crtc (all asics). 1188 * Returns 0 on success, -EINVAL on failure. 1189 */ 1190 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1191 { 1192 struct drm_device *dev = crtc->dev; 1193 unsigned int pipe = crtc->index; 1194 struct amdgpu_device *adev = dev->dev_private; 1195 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1196 1197 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1198 } 1199 1200 /** 1201 * amdgpu_disable_vblank_kms - disable vblank interrupt 1202 * 1203 * @crtc: crtc to disable vblank interrupt for 1204 * 1205 * Disable the interrupt on the requested crtc (all asics). 1206 */ 1207 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1208 { 1209 struct drm_device *dev = crtc->dev; 1210 unsigned int pipe = crtc->index; 1211 struct amdgpu_device *adev = dev->dev_private; 1212 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1213 1214 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1215 } 1216 1217 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1218 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1219 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1220 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1221 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1222 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1223 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1224 /* KMS */ 1225 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1226 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1227 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1228 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1229 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1230 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1231 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1232 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1233 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1234 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1235 }; 1236 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1237 1238 /* 1239 * Debugfs info 1240 */ 1241 #if defined(CONFIG_DEBUG_FS) 1242 1243 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1244 { 1245 struct drm_info_node *node = (struct drm_info_node *) m->private; 1246 struct drm_device *dev = node->minor->dev; 1247 struct amdgpu_device *adev = dev->dev_private; 1248 struct drm_amdgpu_info_firmware fw_info; 1249 struct drm_amdgpu_query_fw query_fw; 1250 struct atom_context *ctx = adev->mode_info.atom_context; 1251 int ret, i; 1252 1253 /* VCE */ 1254 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1255 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1256 if (ret) 1257 return ret; 1258 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1259 fw_info.feature, fw_info.ver); 1260 1261 /* UVD */ 1262 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1263 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1264 if (ret) 1265 return ret; 1266 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1267 fw_info.feature, fw_info.ver); 1268 1269 /* GMC */ 1270 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1271 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1272 if (ret) 1273 return ret; 1274 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1275 fw_info.feature, fw_info.ver); 1276 1277 /* ME */ 1278 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1279 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1280 if (ret) 1281 return ret; 1282 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1283 fw_info.feature, fw_info.ver); 1284 1285 /* PFP */ 1286 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1287 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1288 if (ret) 1289 return ret; 1290 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1291 fw_info.feature, fw_info.ver); 1292 1293 /* CE */ 1294 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1295 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1296 if (ret) 1297 return ret; 1298 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1299 fw_info.feature, fw_info.ver); 1300 1301 /* RLC */ 1302 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1303 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1304 if (ret) 1305 return ret; 1306 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1307 fw_info.feature, fw_info.ver); 1308 1309 /* RLC SAVE RESTORE LIST CNTL */ 1310 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1311 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1312 if (ret) 1313 return ret; 1314 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1315 fw_info.feature, fw_info.ver); 1316 1317 /* RLC SAVE RESTORE LIST GPM MEM */ 1318 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1319 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1320 if (ret) 1321 return ret; 1322 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1323 fw_info.feature, fw_info.ver); 1324 1325 /* RLC SAVE RESTORE LIST SRM MEM */ 1326 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1327 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1328 if (ret) 1329 return ret; 1330 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1331 fw_info.feature, fw_info.ver); 1332 1333 /* MEC */ 1334 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1335 query_fw.index = 0; 1336 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1337 if (ret) 1338 return ret; 1339 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1340 fw_info.feature, fw_info.ver); 1341 1342 /* MEC2 */ 1343 if (adev->asic_type == CHIP_KAVERI || 1344 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1345 query_fw.index = 1; 1346 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1347 if (ret) 1348 return ret; 1349 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1350 fw_info.feature, fw_info.ver); 1351 } 1352 1353 /* PSP SOS */ 1354 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1355 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1356 if (ret) 1357 return ret; 1358 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1359 fw_info.feature, fw_info.ver); 1360 1361 1362 /* PSP ASD */ 1363 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1364 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1365 if (ret) 1366 return ret; 1367 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1368 fw_info.feature, fw_info.ver); 1369 1370 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1371 for (i = 0; i < 2; i++) { 1372 query_fw.index = i; 1373 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1374 if (ret) 1375 continue; 1376 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1377 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1378 } 1379 1380 /* SMC */ 1381 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1382 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1383 if (ret) 1384 return ret; 1385 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1386 fw_info.feature, fw_info.ver); 1387 1388 /* SDMA */ 1389 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1390 for (i = 0; i < adev->sdma.num_instances; i++) { 1391 query_fw.index = i; 1392 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1393 if (ret) 1394 return ret; 1395 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1396 i, fw_info.feature, fw_info.ver); 1397 } 1398 1399 /* VCN */ 1400 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1401 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1402 if (ret) 1403 return ret; 1404 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1405 fw_info.feature, fw_info.ver); 1406 1407 /* DMCU */ 1408 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1409 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1410 if (ret) 1411 return ret; 1412 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1413 fw_info.feature, fw_info.ver); 1414 1415 /* DMCUB */ 1416 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1417 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1418 if (ret) 1419 return ret; 1420 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1421 fw_info.feature, fw_info.ver); 1422 1423 1424 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1425 1426 return 0; 1427 } 1428 1429 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1430 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1431 }; 1432 #endif 1433 1434 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1435 { 1436 #if defined(CONFIG_DEBUG_FS) 1437 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1438 ARRAY_SIZE(amdgpu_firmware_info_list)); 1439 #else 1440 return 0; 1441 #endif 1442 } 1443