1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (adev->runpm) { 91 pm_runtime_get_sync(dev->dev); 92 pm_runtime_forbid(dev->dev); 93 } 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 if (amdgpu_has_atpx() && 141 (amdgpu_is_atpx_hybrid() || 142 amdgpu_has_atpx_dgpu_power_cntl()) && 143 ((flags & AMD_IS_APU) == 0) && 144 !pci_is_thunderbolt_attached(dev->pdev)) 145 flags |= AMD_IS_PX; 146 147 /* amdgpu_device_init should report only fatal error 148 * like memory allocation failure or iomapping failure, 149 * or memory manager initialization failure, it must 150 * properly initialize the GPU MC controller and permit 151 * VRAM allocation 152 */ 153 r = amdgpu_device_init(adev, flags); 154 if (r) { 155 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 156 goto out; 157 } 158 159 if (amdgpu_device_supports_boco(dev) && 160 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 161 adev->runpm = true; 162 } else if (amdgpu_device_supports_baco(dev) && 163 (amdgpu_runtime_pm != 0)) { 164 switch (adev->asic_type) { 165 #ifdef CONFIG_DRM_AMDGPU_CIK 166 case CHIP_BONAIRE: 167 case CHIP_HAWAII: 168 #endif 169 case CHIP_VEGA20: 170 case CHIP_ARCTURUS: 171 case CHIP_SIENNA_CICHLID: 172 case CHIP_NAVY_FLOUNDER: 173 /* enable runpm if runpm=1 */ 174 if (amdgpu_runtime_pm > 0) 175 adev->runpm = true; 176 break; 177 case CHIP_VEGA10: 178 /* turn runpm on if noretry=0 */ 179 if (!adev->gmc.noretry) 180 adev->runpm = true; 181 break; 182 default: 183 /* enable runpm on VI+ */ 184 adev->runpm = true; 185 break; 186 } 187 } 188 189 /* Call ACPI methods: require modeset init 190 * but failure is not fatal 191 */ 192 193 acpi_status = amdgpu_acpi_init(adev); 194 if (acpi_status) 195 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 196 197 if (adev->runpm) { 198 /* only need to skip on ATPX */ 199 if (amdgpu_device_supports_boco(dev) && 200 !amdgpu_is_atpx_hybrid()) 201 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 202 pm_runtime_use_autosuspend(dev->dev); 203 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 204 pm_runtime_allow(dev->dev); 205 pm_runtime_mark_last_busy(dev->dev); 206 pm_runtime_put_autosuspend(dev->dev); 207 } 208 209 out: 210 if (r) { 211 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 212 if (adev->rmmio && adev->runpm) 213 pm_runtime_put_noidle(dev->dev); 214 amdgpu_driver_unload_kms(dev); 215 } 216 217 return r; 218 } 219 220 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 221 struct drm_amdgpu_query_fw *query_fw, 222 struct amdgpu_device *adev) 223 { 224 switch (query_fw->fw_type) { 225 case AMDGPU_INFO_FW_VCE: 226 fw_info->ver = adev->vce.fw_version; 227 fw_info->feature = adev->vce.fb_version; 228 break; 229 case AMDGPU_INFO_FW_UVD: 230 fw_info->ver = adev->uvd.fw_version; 231 fw_info->feature = 0; 232 break; 233 case AMDGPU_INFO_FW_VCN: 234 fw_info->ver = adev->vcn.fw_version; 235 fw_info->feature = 0; 236 break; 237 case AMDGPU_INFO_FW_GMC: 238 fw_info->ver = adev->gmc.fw_version; 239 fw_info->feature = 0; 240 break; 241 case AMDGPU_INFO_FW_GFX_ME: 242 fw_info->ver = adev->gfx.me_fw_version; 243 fw_info->feature = adev->gfx.me_feature_version; 244 break; 245 case AMDGPU_INFO_FW_GFX_PFP: 246 fw_info->ver = adev->gfx.pfp_fw_version; 247 fw_info->feature = adev->gfx.pfp_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_CE: 250 fw_info->ver = adev->gfx.ce_fw_version; 251 fw_info->feature = adev->gfx.ce_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_RLC: 254 fw_info->ver = adev->gfx.rlc_fw_version; 255 fw_info->feature = adev->gfx.rlc_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 258 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 259 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 262 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 263 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 264 break; 265 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 266 fw_info->ver = adev->gfx.rlc_srls_fw_version; 267 fw_info->feature = adev->gfx.rlc_srls_feature_version; 268 break; 269 case AMDGPU_INFO_FW_GFX_MEC: 270 if (query_fw->index == 0) { 271 fw_info->ver = adev->gfx.mec_fw_version; 272 fw_info->feature = adev->gfx.mec_feature_version; 273 } else if (query_fw->index == 1) { 274 fw_info->ver = adev->gfx.mec2_fw_version; 275 fw_info->feature = adev->gfx.mec2_feature_version; 276 } else 277 return -EINVAL; 278 break; 279 case AMDGPU_INFO_FW_SMC: 280 fw_info->ver = adev->pm.fw_version; 281 fw_info->feature = 0; 282 break; 283 case AMDGPU_INFO_FW_TA: 284 switch (query_fw->index) { 285 case 0: 286 fw_info->ver = adev->psp.ta_fw_version; 287 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 288 break; 289 case 1: 290 fw_info->ver = adev->psp.ta_fw_version; 291 fw_info->feature = adev->psp.ta_ras_ucode_version; 292 break; 293 case 2: 294 fw_info->ver = adev->psp.ta_fw_version; 295 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 296 break; 297 case 3: 298 fw_info->ver = adev->psp.ta_fw_version; 299 fw_info->feature = adev->psp.ta_dtm_ucode_version; 300 break; 301 default: 302 return -EINVAL; 303 } 304 break; 305 case AMDGPU_INFO_FW_SDMA: 306 if (query_fw->index >= adev->sdma.num_instances) 307 return -EINVAL; 308 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 309 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 310 break; 311 case AMDGPU_INFO_FW_SOS: 312 fw_info->ver = adev->psp.sos_fw_version; 313 fw_info->feature = adev->psp.sos_feature_version; 314 break; 315 case AMDGPU_INFO_FW_ASD: 316 fw_info->ver = adev->psp.asd_fw_version; 317 fw_info->feature = adev->psp.asd_feature_version; 318 break; 319 case AMDGPU_INFO_FW_DMCU: 320 fw_info->ver = adev->dm.dmcu_fw_version; 321 fw_info->feature = 0; 322 break; 323 case AMDGPU_INFO_FW_DMCUB: 324 fw_info->ver = adev->dm.dmcub_fw_version; 325 fw_info->feature = 0; 326 break; 327 case AMDGPU_INFO_FW_TOC: 328 fw_info->ver = adev->psp.toc_fw_version; 329 fw_info->feature = adev->psp.toc_feature_version; 330 break; 331 default: 332 return -EINVAL; 333 } 334 return 0; 335 } 336 337 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 338 struct drm_amdgpu_info *info, 339 struct drm_amdgpu_info_hw_ip *result) 340 { 341 uint32_t ib_start_alignment = 0; 342 uint32_t ib_size_alignment = 0; 343 enum amd_ip_block_type type; 344 unsigned int num_rings = 0; 345 unsigned int i, j; 346 347 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 348 return -EINVAL; 349 350 switch (info->query_hw_ip.type) { 351 case AMDGPU_HW_IP_GFX: 352 type = AMD_IP_BLOCK_TYPE_GFX; 353 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 354 if (adev->gfx.gfx_ring[i].sched.ready) 355 ++num_rings; 356 ib_start_alignment = 32; 357 ib_size_alignment = 32; 358 break; 359 case AMDGPU_HW_IP_COMPUTE: 360 type = AMD_IP_BLOCK_TYPE_GFX; 361 for (i = 0; i < adev->gfx.num_compute_rings; i++) 362 if (adev->gfx.compute_ring[i].sched.ready) 363 ++num_rings; 364 ib_start_alignment = 32; 365 ib_size_alignment = 32; 366 break; 367 case AMDGPU_HW_IP_DMA: 368 type = AMD_IP_BLOCK_TYPE_SDMA; 369 for (i = 0; i < adev->sdma.num_instances; i++) 370 if (adev->sdma.instance[i].ring.sched.ready) 371 ++num_rings; 372 ib_start_alignment = 256; 373 ib_size_alignment = 4; 374 break; 375 case AMDGPU_HW_IP_UVD: 376 type = AMD_IP_BLOCK_TYPE_UVD; 377 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 378 if (adev->uvd.harvest_config & (1 << i)) 379 continue; 380 381 if (adev->uvd.inst[i].ring.sched.ready) 382 ++num_rings; 383 } 384 ib_start_alignment = 64; 385 ib_size_alignment = 64; 386 break; 387 case AMDGPU_HW_IP_VCE: 388 type = AMD_IP_BLOCK_TYPE_VCE; 389 for (i = 0; i < adev->vce.num_rings; i++) 390 if (adev->vce.ring[i].sched.ready) 391 ++num_rings; 392 ib_start_alignment = 4; 393 ib_size_alignment = 1; 394 break; 395 case AMDGPU_HW_IP_UVD_ENC: 396 type = AMD_IP_BLOCK_TYPE_UVD; 397 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 398 if (adev->uvd.harvest_config & (1 << i)) 399 continue; 400 401 for (j = 0; j < adev->uvd.num_enc_rings; j++) 402 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 403 ++num_rings; 404 } 405 ib_start_alignment = 64; 406 ib_size_alignment = 64; 407 break; 408 case AMDGPU_HW_IP_VCN_DEC: 409 type = AMD_IP_BLOCK_TYPE_VCN; 410 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 411 if (adev->uvd.harvest_config & (1 << i)) 412 continue; 413 414 if (adev->vcn.inst[i].ring_dec.sched.ready) 415 ++num_rings; 416 } 417 ib_start_alignment = 16; 418 ib_size_alignment = 16; 419 break; 420 case AMDGPU_HW_IP_VCN_ENC: 421 type = AMD_IP_BLOCK_TYPE_VCN; 422 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 423 if (adev->uvd.harvest_config & (1 << i)) 424 continue; 425 426 for (j = 0; j < adev->vcn.num_enc_rings; j++) 427 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 428 ++num_rings; 429 } 430 ib_start_alignment = 64; 431 ib_size_alignment = 1; 432 break; 433 case AMDGPU_HW_IP_VCN_JPEG: 434 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 435 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 436 437 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 438 if (adev->jpeg.harvest_config & (1 << i)) 439 continue; 440 441 if (adev->jpeg.inst[i].ring_dec.sched.ready) 442 ++num_rings; 443 } 444 ib_start_alignment = 16; 445 ib_size_alignment = 16; 446 break; 447 default: 448 return -EINVAL; 449 } 450 451 for (i = 0; i < adev->num_ip_blocks; i++) 452 if (adev->ip_blocks[i].version->type == type && 453 adev->ip_blocks[i].status.valid) 454 break; 455 456 if (i == adev->num_ip_blocks) 457 return 0; 458 459 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 460 num_rings); 461 462 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 463 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 464 result->capabilities_flags = 0; 465 result->available_rings = (1 << num_rings) - 1; 466 result->ib_start_alignment = ib_start_alignment; 467 result->ib_size_alignment = ib_size_alignment; 468 return 0; 469 } 470 471 /* 472 * Userspace get information ioctl 473 */ 474 /** 475 * amdgpu_info_ioctl - answer a device specific request. 476 * 477 * @adev: amdgpu device pointer 478 * @data: request object 479 * @filp: drm filp 480 * 481 * This function is used to pass device specific parameters to the userspace 482 * drivers. Examples include: pci device id, pipeline parms, tiling params, 483 * etc. (all asics). 484 * Returns 0 on success, -EINVAL on failure. 485 */ 486 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 487 { 488 struct amdgpu_device *adev = drm_to_adev(dev); 489 struct drm_amdgpu_info *info = data; 490 struct amdgpu_mode_info *minfo = &adev->mode_info; 491 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 492 uint32_t size = info->return_size; 493 struct drm_crtc *crtc; 494 uint32_t ui32 = 0; 495 uint64_t ui64 = 0; 496 int i, found; 497 int ui32_size = sizeof(ui32); 498 499 if (!info->return_size || !info->return_pointer) 500 return -EINVAL; 501 502 switch (info->query) { 503 case AMDGPU_INFO_ACCEL_WORKING: 504 ui32 = adev->accel_working; 505 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 506 case AMDGPU_INFO_CRTC_FROM_ID: 507 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 508 crtc = (struct drm_crtc *)minfo->crtcs[i]; 509 if (crtc && crtc->base.id == info->mode_crtc.id) { 510 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 511 ui32 = amdgpu_crtc->crtc_id; 512 found = 1; 513 break; 514 } 515 } 516 if (!found) { 517 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 518 return -EINVAL; 519 } 520 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 521 case AMDGPU_INFO_HW_IP_INFO: { 522 struct drm_amdgpu_info_hw_ip ip = {}; 523 int ret; 524 525 ret = amdgpu_hw_ip_info(adev, info, &ip); 526 if (ret) 527 return ret; 528 529 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 530 return ret ? -EFAULT : 0; 531 } 532 case AMDGPU_INFO_HW_IP_COUNT: { 533 enum amd_ip_block_type type; 534 uint32_t count = 0; 535 536 switch (info->query_hw_ip.type) { 537 case AMDGPU_HW_IP_GFX: 538 type = AMD_IP_BLOCK_TYPE_GFX; 539 break; 540 case AMDGPU_HW_IP_COMPUTE: 541 type = AMD_IP_BLOCK_TYPE_GFX; 542 break; 543 case AMDGPU_HW_IP_DMA: 544 type = AMD_IP_BLOCK_TYPE_SDMA; 545 break; 546 case AMDGPU_HW_IP_UVD: 547 type = AMD_IP_BLOCK_TYPE_UVD; 548 break; 549 case AMDGPU_HW_IP_VCE: 550 type = AMD_IP_BLOCK_TYPE_VCE; 551 break; 552 case AMDGPU_HW_IP_UVD_ENC: 553 type = AMD_IP_BLOCK_TYPE_UVD; 554 break; 555 case AMDGPU_HW_IP_VCN_DEC: 556 case AMDGPU_HW_IP_VCN_ENC: 557 type = AMD_IP_BLOCK_TYPE_VCN; 558 break; 559 case AMDGPU_HW_IP_VCN_JPEG: 560 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 561 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 for (i = 0; i < adev->num_ip_blocks; i++) 568 if (adev->ip_blocks[i].version->type == type && 569 adev->ip_blocks[i].status.valid && 570 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 571 count++; 572 573 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 574 } 575 case AMDGPU_INFO_TIMESTAMP: 576 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 577 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 578 case AMDGPU_INFO_FW_VERSION: { 579 struct drm_amdgpu_info_firmware fw_info; 580 int ret; 581 582 /* We only support one instance of each IP block right now. */ 583 if (info->query_fw.ip_instance != 0) 584 return -EINVAL; 585 586 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 587 if (ret) 588 return ret; 589 590 return copy_to_user(out, &fw_info, 591 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 592 } 593 case AMDGPU_INFO_NUM_BYTES_MOVED: 594 ui64 = atomic64_read(&adev->num_bytes_moved); 595 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 596 case AMDGPU_INFO_NUM_EVICTIONS: 597 ui64 = atomic64_read(&adev->num_evictions); 598 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 599 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 600 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 601 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 602 case AMDGPU_INFO_VRAM_USAGE: 603 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 604 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 605 case AMDGPU_INFO_VIS_VRAM_USAGE: 606 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 607 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 608 case AMDGPU_INFO_GTT_USAGE: 609 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 610 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 611 case AMDGPU_INFO_GDS_CONFIG: { 612 struct drm_amdgpu_info_gds gds_info; 613 614 memset(&gds_info, 0, sizeof(gds_info)); 615 gds_info.compute_partition_size = adev->gds.gds_size; 616 gds_info.gds_total_size = adev->gds.gds_size; 617 gds_info.gws_per_compute_partition = adev->gds.gws_size; 618 gds_info.oa_per_compute_partition = adev->gds.oa_size; 619 return copy_to_user(out, &gds_info, 620 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 621 } 622 case AMDGPU_INFO_VRAM_GTT: { 623 struct drm_amdgpu_info_vram_gtt vram_gtt; 624 625 vram_gtt.vram_size = adev->gmc.real_vram_size - 626 atomic64_read(&adev->vram_pin_size) - 627 AMDGPU_VM_RESERVED_VRAM; 628 vram_gtt.vram_cpu_accessible_size = 629 min(adev->gmc.visible_vram_size - 630 atomic64_read(&adev->visible_pin_size), 631 vram_gtt.vram_size); 632 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 633 vram_gtt.gtt_size *= PAGE_SIZE; 634 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 635 return copy_to_user(out, &vram_gtt, 636 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 637 } 638 case AMDGPU_INFO_MEMORY: { 639 struct drm_amdgpu_memory_info mem; 640 struct ttm_resource_manager *vram_man = 641 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 642 struct ttm_resource_manager *gtt_man = 643 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 644 memset(&mem, 0, sizeof(mem)); 645 mem.vram.total_heap_size = adev->gmc.real_vram_size; 646 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 647 atomic64_read(&adev->vram_pin_size) - 648 AMDGPU_VM_RESERVED_VRAM; 649 mem.vram.heap_usage = 650 amdgpu_vram_mgr_usage(vram_man); 651 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 652 653 mem.cpu_accessible_vram.total_heap_size = 654 adev->gmc.visible_vram_size; 655 mem.cpu_accessible_vram.usable_heap_size = 656 min(adev->gmc.visible_vram_size - 657 atomic64_read(&adev->visible_pin_size), 658 mem.vram.usable_heap_size); 659 mem.cpu_accessible_vram.heap_usage = 660 amdgpu_vram_mgr_vis_usage(vram_man); 661 mem.cpu_accessible_vram.max_allocation = 662 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 663 664 mem.gtt.total_heap_size = gtt_man->size; 665 mem.gtt.total_heap_size *= PAGE_SIZE; 666 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 667 atomic64_read(&adev->gart_pin_size); 668 mem.gtt.heap_usage = 669 amdgpu_gtt_mgr_usage(gtt_man); 670 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 671 672 return copy_to_user(out, &mem, 673 min((size_t)size, sizeof(mem))) 674 ? -EFAULT : 0; 675 } 676 case AMDGPU_INFO_READ_MMR_REG: { 677 unsigned n, alloc_size; 678 uint32_t *regs; 679 unsigned se_num = (info->read_mmr_reg.instance >> 680 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 681 AMDGPU_INFO_MMR_SE_INDEX_MASK; 682 unsigned sh_num = (info->read_mmr_reg.instance >> 683 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 684 AMDGPU_INFO_MMR_SH_INDEX_MASK; 685 686 /* set full masks if the userspace set all bits 687 * in the bitfields */ 688 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 689 se_num = 0xffffffff; 690 else if (se_num >= AMDGPU_GFX_MAX_SE) 691 return -EINVAL; 692 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 693 sh_num = 0xffffffff; 694 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 695 return -EINVAL; 696 697 if (info->read_mmr_reg.count > 128) 698 return -EINVAL; 699 700 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 701 if (!regs) 702 return -ENOMEM; 703 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 704 705 amdgpu_gfx_off_ctrl(adev, false); 706 for (i = 0; i < info->read_mmr_reg.count; i++) { 707 if (amdgpu_asic_read_register(adev, se_num, sh_num, 708 info->read_mmr_reg.dword_offset + i, 709 ®s[i])) { 710 DRM_DEBUG_KMS("unallowed offset %#x\n", 711 info->read_mmr_reg.dword_offset + i); 712 kfree(regs); 713 amdgpu_gfx_off_ctrl(adev, true); 714 return -EFAULT; 715 } 716 } 717 amdgpu_gfx_off_ctrl(adev, true); 718 n = copy_to_user(out, regs, min(size, alloc_size)); 719 kfree(regs); 720 return n ? -EFAULT : 0; 721 } 722 case AMDGPU_INFO_DEV_INFO: { 723 struct drm_amdgpu_info_device dev_info; 724 uint64_t vm_size; 725 726 memset(&dev_info, 0, sizeof(dev_info)); 727 dev_info.device_id = dev->pdev->device; 728 dev_info.chip_rev = adev->rev_id; 729 dev_info.external_rev = adev->external_rev_id; 730 dev_info.pci_rev = dev->pdev->revision; 731 dev_info.family = adev->family; 732 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 733 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 734 /* return all clocks in KHz */ 735 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 736 if (adev->pm.dpm_enabled) { 737 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 738 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 739 } else { 740 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 741 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 742 } 743 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 744 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 745 adev->gfx.config.max_shader_engines; 746 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 747 dev_info._pad = 0; 748 dev_info.ids_flags = 0; 749 if (adev->flags & AMD_IS_APU) 750 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 751 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 752 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 753 if (amdgpu_is_tmz(adev)) 754 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 755 756 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 757 vm_size -= AMDGPU_VA_RESERVED_SIZE; 758 759 /* Older VCE FW versions are buggy and can handle only 40bits */ 760 if (adev->vce.fw_version && 761 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 762 vm_size = min(vm_size, 1ULL << 40); 763 764 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 765 dev_info.virtual_address_max = 766 min(vm_size, AMDGPU_GMC_HOLE_START); 767 768 if (vm_size > AMDGPU_GMC_HOLE_START) { 769 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 770 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 771 } 772 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 773 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 774 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 775 dev_info.cu_active_number = adev->gfx.cu_info.number; 776 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 777 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 778 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 779 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 780 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 781 sizeof(adev->gfx.cu_info.bitmap)); 782 dev_info.vram_type = adev->gmc.vram_type; 783 dev_info.vram_bit_width = adev->gmc.vram_width; 784 dev_info.vce_harvest_config = adev->vce.harvest_config; 785 dev_info.gc_double_offchip_lds_buf = 786 adev->gfx.config.double_offchip_lds_buf; 787 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 788 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 789 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 790 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 791 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 792 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 793 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 794 795 if (adev->family >= AMDGPU_FAMILY_NV) 796 dev_info.pa_sc_tile_steering_override = 797 adev->gfx.config.pa_sc_tile_steering_override; 798 799 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 800 801 return copy_to_user(out, &dev_info, 802 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 803 } 804 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 805 unsigned i; 806 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 807 struct amd_vce_state *vce_state; 808 809 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 810 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 811 if (vce_state) { 812 vce_clk_table.entries[i].sclk = vce_state->sclk; 813 vce_clk_table.entries[i].mclk = vce_state->mclk; 814 vce_clk_table.entries[i].eclk = vce_state->evclk; 815 vce_clk_table.num_valid_entries++; 816 } 817 } 818 819 return copy_to_user(out, &vce_clk_table, 820 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 821 } 822 case AMDGPU_INFO_VBIOS: { 823 uint32_t bios_size = adev->bios_size; 824 825 switch (info->vbios_info.type) { 826 case AMDGPU_INFO_VBIOS_SIZE: 827 return copy_to_user(out, &bios_size, 828 min((size_t)size, sizeof(bios_size))) 829 ? -EFAULT : 0; 830 case AMDGPU_INFO_VBIOS_IMAGE: { 831 uint8_t *bios; 832 uint32_t bios_offset = info->vbios_info.offset; 833 834 if (bios_offset >= bios_size) 835 return -EINVAL; 836 837 bios = adev->bios + bios_offset; 838 return copy_to_user(out, bios, 839 min((size_t)size, (size_t)(bios_size - bios_offset))) 840 ? -EFAULT : 0; 841 } 842 default: 843 DRM_DEBUG_KMS("Invalid request %d\n", 844 info->vbios_info.type); 845 return -EINVAL; 846 } 847 } 848 case AMDGPU_INFO_NUM_HANDLES: { 849 struct drm_amdgpu_info_num_handles handle; 850 851 switch (info->query_hw_ip.type) { 852 case AMDGPU_HW_IP_UVD: 853 /* Starting Polaris, we support unlimited UVD handles */ 854 if (adev->asic_type < CHIP_POLARIS10) { 855 handle.uvd_max_handles = adev->uvd.max_handles; 856 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 857 858 return copy_to_user(out, &handle, 859 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 860 } else { 861 return -ENODATA; 862 } 863 864 break; 865 default: 866 return -EINVAL; 867 } 868 } 869 case AMDGPU_INFO_SENSOR: { 870 if (!adev->pm.dpm_enabled) 871 return -ENOENT; 872 873 switch (info->sensor_info.type) { 874 case AMDGPU_INFO_SENSOR_GFX_SCLK: 875 /* get sclk in Mhz */ 876 if (amdgpu_dpm_read_sensor(adev, 877 AMDGPU_PP_SENSOR_GFX_SCLK, 878 (void *)&ui32, &ui32_size)) { 879 return -EINVAL; 880 } 881 ui32 /= 100; 882 break; 883 case AMDGPU_INFO_SENSOR_GFX_MCLK: 884 /* get mclk in Mhz */ 885 if (amdgpu_dpm_read_sensor(adev, 886 AMDGPU_PP_SENSOR_GFX_MCLK, 887 (void *)&ui32, &ui32_size)) { 888 return -EINVAL; 889 } 890 ui32 /= 100; 891 break; 892 case AMDGPU_INFO_SENSOR_GPU_TEMP: 893 /* get temperature in millidegrees C */ 894 if (amdgpu_dpm_read_sensor(adev, 895 AMDGPU_PP_SENSOR_GPU_TEMP, 896 (void *)&ui32, &ui32_size)) { 897 return -EINVAL; 898 } 899 break; 900 case AMDGPU_INFO_SENSOR_GPU_LOAD: 901 /* get GPU load */ 902 if (amdgpu_dpm_read_sensor(adev, 903 AMDGPU_PP_SENSOR_GPU_LOAD, 904 (void *)&ui32, &ui32_size)) { 905 return -EINVAL; 906 } 907 break; 908 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 909 /* get average GPU power */ 910 if (amdgpu_dpm_read_sensor(adev, 911 AMDGPU_PP_SENSOR_GPU_POWER, 912 (void *)&ui32, &ui32_size)) { 913 return -EINVAL; 914 } 915 ui32 >>= 8; 916 break; 917 case AMDGPU_INFO_SENSOR_VDDNB: 918 /* get VDDNB in millivolts */ 919 if (amdgpu_dpm_read_sensor(adev, 920 AMDGPU_PP_SENSOR_VDDNB, 921 (void *)&ui32, &ui32_size)) { 922 return -EINVAL; 923 } 924 break; 925 case AMDGPU_INFO_SENSOR_VDDGFX: 926 /* get VDDGFX in millivolts */ 927 if (amdgpu_dpm_read_sensor(adev, 928 AMDGPU_PP_SENSOR_VDDGFX, 929 (void *)&ui32, &ui32_size)) { 930 return -EINVAL; 931 } 932 break; 933 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 934 /* get stable pstate sclk in Mhz */ 935 if (amdgpu_dpm_read_sensor(adev, 936 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 937 (void *)&ui32, &ui32_size)) { 938 return -EINVAL; 939 } 940 ui32 /= 100; 941 break; 942 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 943 /* get stable pstate mclk in Mhz */ 944 if (amdgpu_dpm_read_sensor(adev, 945 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 946 (void *)&ui32, &ui32_size)) { 947 return -EINVAL; 948 } 949 ui32 /= 100; 950 break; 951 default: 952 DRM_DEBUG_KMS("Invalid request %d\n", 953 info->sensor_info.type); 954 return -EINVAL; 955 } 956 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 957 } 958 case AMDGPU_INFO_VRAM_LOST_COUNTER: 959 ui32 = atomic_read(&adev->vram_lost_counter); 960 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 961 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 962 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 963 uint64_t ras_mask; 964 965 if (!ras) 966 return -EINVAL; 967 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 968 969 return copy_to_user(out, &ras_mask, 970 min_t(u64, size, sizeof(ras_mask))) ? 971 -EFAULT : 0; 972 } 973 default: 974 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 975 return -EINVAL; 976 } 977 return 0; 978 } 979 980 981 /* 982 * Outdated mess for old drm with Xorg being in charge (void function now). 983 */ 984 /** 985 * amdgpu_driver_lastclose_kms - drm callback for last close 986 * 987 * @dev: drm dev pointer 988 * 989 * Switch vga_switcheroo state after last close (all asics). 990 */ 991 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 992 { 993 drm_fb_helper_lastclose(dev); 994 vga_switcheroo_process_delayed_switch(); 995 } 996 997 /** 998 * amdgpu_driver_open_kms - drm callback for open 999 * 1000 * @dev: drm dev pointer 1001 * @file_priv: drm file 1002 * 1003 * On device open, init vm on cayman+ (all asics). 1004 * Returns 0 on success, error on failure. 1005 */ 1006 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1007 { 1008 struct amdgpu_device *adev = drm_to_adev(dev); 1009 struct amdgpu_fpriv *fpriv; 1010 int r, pasid; 1011 1012 /* Ensure IB tests are run on ring */ 1013 flush_delayed_work(&adev->delayed_init_work); 1014 1015 1016 if (amdgpu_ras_intr_triggered()) { 1017 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1018 return -EHWPOISON; 1019 } 1020 1021 file_priv->driver_priv = NULL; 1022 1023 r = pm_runtime_get_sync(dev->dev); 1024 if (r < 0) 1025 goto pm_put; 1026 1027 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1028 if (unlikely(!fpriv)) { 1029 r = -ENOMEM; 1030 goto out_suspend; 1031 } 1032 1033 pasid = amdgpu_pasid_alloc(16); 1034 if (pasid < 0) { 1035 dev_warn(adev->dev, "No more PASIDs available!"); 1036 pasid = 0; 1037 } 1038 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1039 if (r) 1040 goto error_pasid; 1041 1042 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1043 if (!fpriv->prt_va) { 1044 r = -ENOMEM; 1045 goto error_vm; 1046 } 1047 1048 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1049 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1050 1051 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1052 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1053 if (r) 1054 goto error_vm; 1055 } 1056 1057 mutex_init(&fpriv->bo_list_lock); 1058 idr_init(&fpriv->bo_list_handles); 1059 1060 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1061 1062 file_priv->driver_priv = fpriv; 1063 goto out_suspend; 1064 1065 error_vm: 1066 amdgpu_vm_fini(adev, &fpriv->vm); 1067 1068 error_pasid: 1069 if (pasid) 1070 amdgpu_pasid_free(pasid); 1071 1072 kfree(fpriv); 1073 1074 out_suspend: 1075 pm_runtime_mark_last_busy(dev->dev); 1076 pm_put: 1077 pm_runtime_put_autosuspend(dev->dev); 1078 1079 return r; 1080 } 1081 1082 /** 1083 * amdgpu_driver_postclose_kms - drm callback for post close 1084 * 1085 * @dev: drm dev pointer 1086 * @file_priv: drm file 1087 * 1088 * On device post close, tear down vm on cayman+ (all asics). 1089 */ 1090 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1091 struct drm_file *file_priv) 1092 { 1093 struct amdgpu_device *adev = drm_to_adev(dev); 1094 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1095 struct amdgpu_bo_list *list; 1096 struct amdgpu_bo *pd; 1097 u32 pasid; 1098 int handle; 1099 1100 if (!fpriv) 1101 return; 1102 1103 pm_runtime_get_sync(dev->dev); 1104 1105 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1106 amdgpu_uvd_free_handles(adev, file_priv); 1107 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1108 amdgpu_vce_free_handles(adev, file_priv); 1109 1110 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1111 1112 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1113 /* TODO: how to handle reserve failure */ 1114 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1115 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1116 fpriv->csa_va = NULL; 1117 amdgpu_bo_unreserve(adev->virt.csa_obj); 1118 } 1119 1120 pasid = fpriv->vm.pasid; 1121 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1122 1123 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1124 amdgpu_vm_fini(adev, &fpriv->vm); 1125 1126 if (pasid) 1127 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1128 amdgpu_bo_unref(&pd); 1129 1130 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1131 amdgpu_bo_list_put(list); 1132 1133 idr_destroy(&fpriv->bo_list_handles); 1134 mutex_destroy(&fpriv->bo_list_lock); 1135 1136 kfree(fpriv); 1137 file_priv->driver_priv = NULL; 1138 1139 pm_runtime_mark_last_busy(dev->dev); 1140 pm_runtime_put_autosuspend(dev->dev); 1141 } 1142 1143 /* 1144 * VBlank related functions. 1145 */ 1146 /** 1147 * amdgpu_get_vblank_counter_kms - get frame count 1148 * 1149 * @crtc: crtc to get the frame count from 1150 * 1151 * Gets the frame count on the requested crtc (all asics). 1152 * Returns frame count on success, -EINVAL on failure. 1153 */ 1154 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1155 { 1156 struct drm_device *dev = crtc->dev; 1157 unsigned int pipe = crtc->index; 1158 struct amdgpu_device *adev = drm_to_adev(dev); 1159 int vpos, hpos, stat; 1160 u32 count; 1161 1162 if (pipe >= adev->mode_info.num_crtc) { 1163 DRM_ERROR("Invalid crtc %u\n", pipe); 1164 return -EINVAL; 1165 } 1166 1167 /* The hw increments its frame counter at start of vsync, not at start 1168 * of vblank, as is required by DRM core vblank counter handling. 1169 * Cook the hw count here to make it appear to the caller as if it 1170 * incremented at start of vblank. We measure distance to start of 1171 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1172 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1173 * result by 1 to give the proper appearance to caller. 1174 */ 1175 if (adev->mode_info.crtcs[pipe]) { 1176 /* Repeat readout if needed to provide stable result if 1177 * we cross start of vsync during the queries. 1178 */ 1179 do { 1180 count = amdgpu_display_vblank_get_counter(adev, pipe); 1181 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1182 * vpos as distance to start of vblank, instead of 1183 * regular vertical scanout pos. 1184 */ 1185 stat = amdgpu_display_get_crtc_scanoutpos( 1186 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1187 &vpos, &hpos, NULL, NULL, 1188 &adev->mode_info.crtcs[pipe]->base.hwmode); 1189 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1190 1191 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1192 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1193 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1194 } else { 1195 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1196 pipe, vpos); 1197 1198 /* Bump counter if we are at >= leading edge of vblank, 1199 * but before vsync where vpos would turn negative and 1200 * the hw counter really increments. 1201 */ 1202 if (vpos >= 0) 1203 count++; 1204 } 1205 } else { 1206 /* Fallback to use value as is. */ 1207 count = amdgpu_display_vblank_get_counter(adev, pipe); 1208 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1209 } 1210 1211 return count; 1212 } 1213 1214 /** 1215 * amdgpu_enable_vblank_kms - enable vblank interrupt 1216 * 1217 * @crtc: crtc to enable vblank interrupt for 1218 * 1219 * Enable the interrupt on the requested crtc (all asics). 1220 * Returns 0 on success, -EINVAL on failure. 1221 */ 1222 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1223 { 1224 struct drm_device *dev = crtc->dev; 1225 unsigned int pipe = crtc->index; 1226 struct amdgpu_device *adev = drm_to_adev(dev); 1227 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1228 1229 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1230 } 1231 1232 /** 1233 * amdgpu_disable_vblank_kms - disable vblank interrupt 1234 * 1235 * @crtc: crtc to disable vblank interrupt for 1236 * 1237 * Disable the interrupt on the requested crtc (all asics). 1238 */ 1239 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1240 { 1241 struct drm_device *dev = crtc->dev; 1242 unsigned int pipe = crtc->index; 1243 struct amdgpu_device *adev = drm_to_adev(dev); 1244 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1245 1246 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1247 } 1248 1249 /* 1250 * Debugfs info 1251 */ 1252 #if defined(CONFIG_DEBUG_FS) 1253 1254 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1255 { 1256 struct drm_info_node *node = (struct drm_info_node *) m->private; 1257 struct drm_device *dev = node->minor->dev; 1258 struct amdgpu_device *adev = drm_to_adev(dev); 1259 struct drm_amdgpu_info_firmware fw_info; 1260 struct drm_amdgpu_query_fw query_fw; 1261 struct atom_context *ctx = adev->mode_info.atom_context; 1262 int ret, i; 1263 1264 /* VCE */ 1265 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1266 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1267 if (ret) 1268 return ret; 1269 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1270 fw_info.feature, fw_info.ver); 1271 1272 /* UVD */ 1273 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1274 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1275 if (ret) 1276 return ret; 1277 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1278 fw_info.feature, fw_info.ver); 1279 1280 /* GMC */ 1281 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1282 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1283 if (ret) 1284 return ret; 1285 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1286 fw_info.feature, fw_info.ver); 1287 1288 /* ME */ 1289 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1290 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1291 if (ret) 1292 return ret; 1293 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1294 fw_info.feature, fw_info.ver); 1295 1296 /* PFP */ 1297 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1298 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1299 if (ret) 1300 return ret; 1301 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1302 fw_info.feature, fw_info.ver); 1303 1304 /* CE */ 1305 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1306 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1307 if (ret) 1308 return ret; 1309 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1310 fw_info.feature, fw_info.ver); 1311 1312 /* RLC */ 1313 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1314 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1315 if (ret) 1316 return ret; 1317 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1318 fw_info.feature, fw_info.ver); 1319 1320 /* RLC SAVE RESTORE LIST CNTL */ 1321 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1322 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1323 if (ret) 1324 return ret; 1325 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1326 fw_info.feature, fw_info.ver); 1327 1328 /* RLC SAVE RESTORE LIST GPM MEM */ 1329 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1330 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1331 if (ret) 1332 return ret; 1333 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1334 fw_info.feature, fw_info.ver); 1335 1336 /* RLC SAVE RESTORE LIST SRM MEM */ 1337 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1338 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1339 if (ret) 1340 return ret; 1341 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1342 fw_info.feature, fw_info.ver); 1343 1344 /* MEC */ 1345 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1346 query_fw.index = 0; 1347 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1348 if (ret) 1349 return ret; 1350 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1351 fw_info.feature, fw_info.ver); 1352 1353 /* MEC2 */ 1354 if (adev->gfx.mec2_fw) { 1355 query_fw.index = 1; 1356 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1357 if (ret) 1358 return ret; 1359 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1360 fw_info.feature, fw_info.ver); 1361 } 1362 1363 /* PSP SOS */ 1364 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1365 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1366 if (ret) 1367 return ret; 1368 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1369 fw_info.feature, fw_info.ver); 1370 1371 1372 /* PSP ASD */ 1373 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1374 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1375 if (ret) 1376 return ret; 1377 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1378 fw_info.feature, fw_info.ver); 1379 1380 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1381 for (i = 0; i < 4; i++) { 1382 query_fw.index = i; 1383 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1384 if (ret) 1385 continue; 1386 switch (query_fw.index) { 1387 case 0: 1388 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1389 "RAS", fw_info.feature, fw_info.ver); 1390 break; 1391 case 1: 1392 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1393 "XGMI", fw_info.feature, fw_info.ver); 1394 break; 1395 case 2: 1396 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1397 "HDCP", fw_info.feature, fw_info.ver); 1398 break; 1399 case 3: 1400 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1401 "DTM", fw_info.feature, fw_info.ver); 1402 break; 1403 default: 1404 return -EINVAL; 1405 } 1406 } 1407 1408 /* SMC */ 1409 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1410 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1411 if (ret) 1412 return ret; 1413 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1414 fw_info.feature, fw_info.ver); 1415 1416 /* SDMA */ 1417 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1418 for (i = 0; i < adev->sdma.num_instances; i++) { 1419 query_fw.index = i; 1420 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1421 if (ret) 1422 return ret; 1423 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1424 i, fw_info.feature, fw_info.ver); 1425 } 1426 1427 /* VCN */ 1428 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1429 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1430 if (ret) 1431 return ret; 1432 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1433 fw_info.feature, fw_info.ver); 1434 1435 /* DMCU */ 1436 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1437 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1438 if (ret) 1439 return ret; 1440 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1441 fw_info.feature, fw_info.ver); 1442 1443 /* DMCUB */ 1444 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1445 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1446 if (ret) 1447 return ret; 1448 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1449 fw_info.feature, fw_info.ver); 1450 1451 /* TOC */ 1452 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1453 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1454 if (ret) 1455 return ret; 1456 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1457 fw_info.feature, fw_info.ver); 1458 1459 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1460 1461 return 0; 1462 } 1463 1464 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1465 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1466 }; 1467 #endif 1468 1469 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1470 { 1471 #if defined(CONFIG_DEBUG_FS) 1472 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1473 ARRAY_SIZE(amdgpu_firmware_info_list)); 1474 #else 1475 return 0; 1476 #endif 1477 } 1478