1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 34 #include <linux/vga_switcheroo.h> 35 #include <linux/slab.h> 36 #include <linux/pm_runtime.h> 37 #include "amdgpu_amdkfd.h" 38 39 /** 40 * amdgpu_driver_unload_kms - Main unload function for KMS. 41 * 42 * @dev: drm dev pointer 43 * 44 * This is the main unload function for KMS (all asics). 45 * Returns 0 on success. 46 */ 47 void amdgpu_driver_unload_kms(struct drm_device *dev) 48 { 49 struct amdgpu_device *adev = dev->dev_private; 50 51 if (adev == NULL) 52 return; 53 54 if (adev->rmmio == NULL) 55 goto done_free; 56 57 if (amdgpu_sriov_vf(adev)) 58 amdgpu_virt_request_full_gpu(adev, false); 59 60 if (amdgpu_device_is_px(dev)) { 61 pm_runtime_get_sync(dev->dev); 62 pm_runtime_forbid(dev->dev); 63 } 64 65 amdgpu_amdkfd_device_fini(adev); 66 67 amdgpu_acpi_fini(adev); 68 69 amdgpu_device_fini(adev); 70 71 done_free: 72 kfree(adev); 73 dev->dev_private = NULL; 74 } 75 76 /** 77 * amdgpu_driver_load_kms - Main load function for KMS. 78 * 79 * @dev: drm dev pointer 80 * @flags: device flags 81 * 82 * This is the main load function for KMS (all asics). 83 * Returns 0 on success, error on failure. 84 */ 85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 86 { 87 struct amdgpu_device *adev; 88 int r, acpi_status; 89 90 #ifdef CONFIG_DRM_AMDGPU_SI 91 if (!amdgpu_si_support) { 92 switch (flags & AMD_ASIC_MASK) { 93 case CHIP_TAHITI: 94 case CHIP_PITCAIRN: 95 case CHIP_VERDE: 96 case CHIP_OLAND: 97 case CHIP_HAINAN: 98 dev_info(dev->dev, 99 "SI support provided by radeon.\n"); 100 dev_info(dev->dev, 101 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 102 ); 103 return -ENODEV; 104 } 105 } 106 #endif 107 #ifdef CONFIG_DRM_AMDGPU_CIK 108 if (!amdgpu_cik_support) { 109 switch (flags & AMD_ASIC_MASK) { 110 case CHIP_KAVERI: 111 case CHIP_BONAIRE: 112 case CHIP_HAWAII: 113 case CHIP_KABINI: 114 case CHIP_MULLINS: 115 dev_info(dev->dev, 116 "CIK support provided by radeon.\n"); 117 dev_info(dev->dev, 118 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 119 ); 120 return -ENODEV; 121 } 122 } 123 #endif 124 125 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 126 if (adev == NULL) { 127 return -ENOMEM; 128 } 129 dev->dev_private = (void *)adev; 130 131 if ((amdgpu_runtime_pm != 0) && 132 amdgpu_has_atpx() && 133 (amdgpu_is_atpx_hybrid() || 134 amdgpu_has_atpx_dgpu_power_cntl()) && 135 ((flags & AMD_IS_APU) == 0) && 136 !pci_is_thunderbolt_attached(dev->pdev)) 137 flags |= AMD_IS_PX; 138 139 /* amdgpu_device_init should report only fatal error 140 * like memory allocation failure or iomapping failure, 141 * or memory manager initialization failure, it must 142 * properly initialize the GPU MC controller and permit 143 * VRAM allocation 144 */ 145 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 146 if (r) { 147 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 148 goto out; 149 } 150 151 /* Call ACPI methods: require modeset init 152 * but failure is not fatal 153 */ 154 if (!r) { 155 acpi_status = amdgpu_acpi_init(adev); 156 if (acpi_status) 157 dev_dbg(&dev->pdev->dev, 158 "Error during ACPI methods call\n"); 159 } 160 161 amdgpu_amdkfd_load_interface(adev); 162 amdgpu_amdkfd_device_probe(adev); 163 amdgpu_amdkfd_device_init(adev); 164 165 if (amdgpu_device_is_px(dev)) { 166 pm_runtime_use_autosuspend(dev->dev); 167 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 168 pm_runtime_set_active(dev->dev); 169 pm_runtime_allow(dev->dev); 170 pm_runtime_mark_last_busy(dev->dev); 171 pm_runtime_put_autosuspend(dev->dev); 172 } 173 174 if (amdgpu_sriov_vf(adev)) 175 amdgpu_virt_release_full_gpu(adev, true); 176 177 out: 178 if (r) { 179 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 180 if (adev->rmmio && amdgpu_device_is_px(dev)) 181 pm_runtime_put_noidle(dev->dev); 182 amdgpu_driver_unload_kms(dev); 183 } 184 185 return r; 186 } 187 188 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 189 struct drm_amdgpu_query_fw *query_fw, 190 struct amdgpu_device *adev) 191 { 192 switch (query_fw->fw_type) { 193 case AMDGPU_INFO_FW_VCE: 194 fw_info->ver = adev->vce.fw_version; 195 fw_info->feature = adev->vce.fb_version; 196 break; 197 case AMDGPU_INFO_FW_UVD: 198 fw_info->ver = adev->uvd.fw_version; 199 fw_info->feature = 0; 200 break; 201 case AMDGPU_INFO_FW_GMC: 202 fw_info->ver = adev->mc.fw_version; 203 fw_info->feature = 0; 204 break; 205 case AMDGPU_INFO_FW_GFX_ME: 206 fw_info->ver = adev->gfx.me_fw_version; 207 fw_info->feature = adev->gfx.me_feature_version; 208 break; 209 case AMDGPU_INFO_FW_GFX_PFP: 210 fw_info->ver = adev->gfx.pfp_fw_version; 211 fw_info->feature = adev->gfx.pfp_feature_version; 212 break; 213 case AMDGPU_INFO_FW_GFX_CE: 214 fw_info->ver = adev->gfx.ce_fw_version; 215 fw_info->feature = adev->gfx.ce_feature_version; 216 break; 217 case AMDGPU_INFO_FW_GFX_RLC: 218 fw_info->ver = adev->gfx.rlc_fw_version; 219 fw_info->feature = adev->gfx.rlc_feature_version; 220 break; 221 case AMDGPU_INFO_FW_GFX_MEC: 222 if (query_fw->index == 0) { 223 fw_info->ver = adev->gfx.mec_fw_version; 224 fw_info->feature = adev->gfx.mec_feature_version; 225 } else if (query_fw->index == 1) { 226 fw_info->ver = adev->gfx.mec2_fw_version; 227 fw_info->feature = adev->gfx.mec2_feature_version; 228 } else 229 return -EINVAL; 230 break; 231 case AMDGPU_INFO_FW_SMC: 232 fw_info->ver = adev->pm.fw_version; 233 fw_info->feature = 0; 234 break; 235 case AMDGPU_INFO_FW_SDMA: 236 if (query_fw->index >= adev->sdma.num_instances) 237 return -EINVAL; 238 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 239 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 240 break; 241 case AMDGPU_INFO_FW_SOS: 242 fw_info->ver = adev->psp.sos_fw_version; 243 fw_info->feature = adev->psp.sos_feature_version; 244 break; 245 case AMDGPU_INFO_FW_ASD: 246 fw_info->ver = adev->psp.asd_fw_version; 247 fw_info->feature = adev->psp.asd_feature_version; 248 break; 249 default: 250 return -EINVAL; 251 } 252 return 0; 253 } 254 255 /* 256 * Userspace get information ioctl 257 */ 258 /** 259 * amdgpu_info_ioctl - answer a device specific request. 260 * 261 * @adev: amdgpu device pointer 262 * @data: request object 263 * @filp: drm filp 264 * 265 * This function is used to pass device specific parameters to the userspace 266 * drivers. Examples include: pci device id, pipeline parms, tiling params, 267 * etc. (all asics). 268 * Returns 0 on success, -EINVAL on failure. 269 */ 270 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 271 { 272 struct amdgpu_device *adev = dev->dev_private; 273 struct amdgpu_fpriv *fpriv = filp->driver_priv; 274 struct drm_amdgpu_info *info = data; 275 struct amdgpu_mode_info *minfo = &adev->mode_info; 276 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 277 uint32_t size = info->return_size; 278 struct drm_crtc *crtc; 279 uint32_t ui32 = 0; 280 uint64_t ui64 = 0; 281 int i, found; 282 int ui32_size = sizeof(ui32); 283 284 if (!info->return_size || !info->return_pointer) 285 return -EINVAL; 286 if (amdgpu_kms_vram_lost(adev, fpriv)) 287 return -ENODEV; 288 289 switch (info->query) { 290 case AMDGPU_INFO_ACCEL_WORKING: 291 ui32 = adev->accel_working; 292 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 293 case AMDGPU_INFO_CRTC_FROM_ID: 294 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 295 crtc = (struct drm_crtc *)minfo->crtcs[i]; 296 if (crtc && crtc->base.id == info->mode_crtc.id) { 297 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 298 ui32 = amdgpu_crtc->crtc_id; 299 found = 1; 300 break; 301 } 302 } 303 if (!found) { 304 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 305 return -EINVAL; 306 } 307 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 308 case AMDGPU_INFO_HW_IP_INFO: { 309 struct drm_amdgpu_info_hw_ip ip = {}; 310 enum amd_ip_block_type type; 311 uint32_t ring_mask = 0; 312 uint32_t ib_start_alignment = 0; 313 uint32_t ib_size_alignment = 0; 314 315 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 316 return -EINVAL; 317 318 switch (info->query_hw_ip.type) { 319 case AMDGPU_HW_IP_GFX: 320 type = AMD_IP_BLOCK_TYPE_GFX; 321 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 322 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 323 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 324 ib_size_alignment = 8; 325 break; 326 case AMDGPU_HW_IP_COMPUTE: 327 type = AMD_IP_BLOCK_TYPE_GFX; 328 for (i = 0; i < adev->gfx.num_compute_rings; i++) 329 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 330 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 331 ib_size_alignment = 8; 332 break; 333 case AMDGPU_HW_IP_DMA: 334 type = AMD_IP_BLOCK_TYPE_SDMA; 335 for (i = 0; i < adev->sdma.num_instances; i++) 336 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 337 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 338 ib_size_alignment = 1; 339 break; 340 case AMDGPU_HW_IP_UVD: 341 type = AMD_IP_BLOCK_TYPE_UVD; 342 ring_mask = adev->uvd.ring.ready ? 1 : 0; 343 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 344 ib_size_alignment = 16; 345 break; 346 case AMDGPU_HW_IP_VCE: 347 type = AMD_IP_BLOCK_TYPE_VCE; 348 for (i = 0; i < adev->vce.num_rings; i++) 349 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 350 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 351 ib_size_alignment = 1; 352 break; 353 case AMDGPU_HW_IP_UVD_ENC: 354 type = AMD_IP_BLOCK_TYPE_UVD; 355 for (i = 0; i < adev->uvd.num_enc_rings; i++) 356 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 357 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 358 ib_size_alignment = 1; 359 break; 360 case AMDGPU_HW_IP_VCN_DEC: 361 type = AMD_IP_BLOCK_TYPE_VCN; 362 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 363 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 364 ib_size_alignment = 16; 365 break; 366 case AMDGPU_HW_IP_VCN_ENC: 367 type = AMD_IP_BLOCK_TYPE_VCN; 368 for (i = 0; i < adev->vcn.num_enc_rings; i++) 369 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 370 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 371 ib_size_alignment = 1; 372 break; 373 default: 374 return -EINVAL; 375 } 376 377 for (i = 0; i < adev->num_ip_blocks; i++) { 378 if (adev->ip_blocks[i].version->type == type && 379 adev->ip_blocks[i].status.valid) { 380 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 381 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 382 ip.capabilities_flags = 0; 383 ip.available_rings = ring_mask; 384 ip.ib_start_alignment = ib_start_alignment; 385 ip.ib_size_alignment = ib_size_alignment; 386 break; 387 } 388 } 389 return copy_to_user(out, &ip, 390 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 391 } 392 case AMDGPU_INFO_HW_IP_COUNT: { 393 enum amd_ip_block_type type; 394 uint32_t count = 0; 395 396 switch (info->query_hw_ip.type) { 397 case AMDGPU_HW_IP_GFX: 398 type = AMD_IP_BLOCK_TYPE_GFX; 399 break; 400 case AMDGPU_HW_IP_COMPUTE: 401 type = AMD_IP_BLOCK_TYPE_GFX; 402 break; 403 case AMDGPU_HW_IP_DMA: 404 type = AMD_IP_BLOCK_TYPE_SDMA; 405 break; 406 case AMDGPU_HW_IP_UVD: 407 type = AMD_IP_BLOCK_TYPE_UVD; 408 break; 409 case AMDGPU_HW_IP_VCE: 410 type = AMD_IP_BLOCK_TYPE_VCE; 411 break; 412 case AMDGPU_HW_IP_UVD_ENC: 413 type = AMD_IP_BLOCK_TYPE_UVD; 414 break; 415 case AMDGPU_HW_IP_VCN_DEC: 416 case AMDGPU_HW_IP_VCN_ENC: 417 type = AMD_IP_BLOCK_TYPE_VCN; 418 break; 419 default: 420 return -EINVAL; 421 } 422 423 for (i = 0; i < adev->num_ip_blocks; i++) 424 if (adev->ip_blocks[i].version->type == type && 425 adev->ip_blocks[i].status.valid && 426 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 427 count++; 428 429 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 430 } 431 case AMDGPU_INFO_TIMESTAMP: 432 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 433 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 434 case AMDGPU_INFO_FW_VERSION: { 435 struct drm_amdgpu_info_firmware fw_info; 436 int ret; 437 438 /* We only support one instance of each IP block right now. */ 439 if (info->query_fw.ip_instance != 0) 440 return -EINVAL; 441 442 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 443 if (ret) 444 return ret; 445 446 return copy_to_user(out, &fw_info, 447 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 448 } 449 case AMDGPU_INFO_NUM_BYTES_MOVED: 450 ui64 = atomic64_read(&adev->num_bytes_moved); 451 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 452 case AMDGPU_INFO_NUM_EVICTIONS: 453 ui64 = atomic64_read(&adev->num_evictions); 454 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 455 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 456 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 457 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 458 case AMDGPU_INFO_VRAM_USAGE: 459 ui64 = atomic64_read(&adev->vram_usage); 460 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 461 case AMDGPU_INFO_VIS_VRAM_USAGE: 462 ui64 = atomic64_read(&adev->vram_vis_usage); 463 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 464 case AMDGPU_INFO_GTT_USAGE: 465 ui64 = atomic64_read(&adev->gtt_usage); 466 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 467 case AMDGPU_INFO_GDS_CONFIG: { 468 struct drm_amdgpu_info_gds gds_info; 469 470 memset(&gds_info, 0, sizeof(gds_info)); 471 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 472 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 473 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 474 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 475 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 476 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 477 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 478 return copy_to_user(out, &gds_info, 479 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 480 } 481 case AMDGPU_INFO_VRAM_GTT: { 482 struct drm_amdgpu_info_vram_gtt vram_gtt; 483 484 vram_gtt.vram_size = adev->mc.real_vram_size; 485 vram_gtt.vram_size -= adev->vram_pin_size; 486 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 487 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 488 vram_gtt.gtt_size = adev->mc.gtt_size; 489 vram_gtt.gtt_size -= adev->gart_pin_size; 490 return copy_to_user(out, &vram_gtt, 491 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 492 } 493 case AMDGPU_INFO_MEMORY: { 494 struct drm_amdgpu_memory_info mem; 495 496 memset(&mem, 0, sizeof(mem)); 497 mem.vram.total_heap_size = adev->mc.real_vram_size; 498 mem.vram.usable_heap_size = 499 adev->mc.real_vram_size - adev->vram_pin_size; 500 mem.vram.heap_usage = atomic64_read(&adev->vram_usage); 501 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 502 503 mem.cpu_accessible_vram.total_heap_size = 504 adev->mc.visible_vram_size; 505 mem.cpu_accessible_vram.usable_heap_size = 506 adev->mc.visible_vram_size - 507 (adev->vram_pin_size - adev->invisible_pin_size); 508 mem.cpu_accessible_vram.heap_usage = 509 atomic64_read(&adev->vram_vis_usage); 510 mem.cpu_accessible_vram.max_allocation = 511 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 512 513 mem.gtt.total_heap_size = adev->mc.gtt_size; 514 mem.gtt.usable_heap_size = 515 adev->mc.gtt_size - adev->gart_pin_size; 516 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); 517 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 518 519 return copy_to_user(out, &mem, 520 min((size_t)size, sizeof(mem))) 521 ? -EFAULT : 0; 522 } 523 case AMDGPU_INFO_READ_MMR_REG: { 524 unsigned n, alloc_size; 525 uint32_t *regs; 526 unsigned se_num = (info->read_mmr_reg.instance >> 527 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 528 AMDGPU_INFO_MMR_SE_INDEX_MASK; 529 unsigned sh_num = (info->read_mmr_reg.instance >> 530 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 531 AMDGPU_INFO_MMR_SH_INDEX_MASK; 532 533 /* set full masks if the userspace set all bits 534 * in the bitfields */ 535 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 536 se_num = 0xffffffff; 537 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 538 sh_num = 0xffffffff; 539 540 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 541 if (!regs) 542 return -ENOMEM; 543 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 544 545 for (i = 0; i < info->read_mmr_reg.count; i++) 546 if (amdgpu_asic_read_register(adev, se_num, sh_num, 547 info->read_mmr_reg.dword_offset + i, 548 ®s[i])) { 549 DRM_DEBUG_KMS("unallowed offset %#x\n", 550 info->read_mmr_reg.dword_offset + i); 551 kfree(regs); 552 return -EFAULT; 553 } 554 n = copy_to_user(out, regs, min(size, alloc_size)); 555 kfree(regs); 556 return n ? -EFAULT : 0; 557 } 558 case AMDGPU_INFO_DEV_INFO: { 559 struct drm_amdgpu_info_device dev_info = {}; 560 561 dev_info.device_id = dev->pdev->device; 562 dev_info.chip_rev = adev->rev_id; 563 dev_info.external_rev = adev->external_rev_id; 564 dev_info.pci_rev = dev->pdev->revision; 565 dev_info.family = adev->family; 566 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 567 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 568 /* return all clocks in KHz */ 569 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 570 if (adev->pm.dpm_enabled) { 571 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 572 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 573 } else { 574 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 575 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 576 } 577 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 578 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 579 adev->gfx.config.max_shader_engines; 580 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 581 dev_info._pad = 0; 582 dev_info.ids_flags = 0; 583 if (adev->flags & AMD_IS_APU) 584 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 585 if (amdgpu_sriov_vf(adev)) 586 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 587 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 588 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 589 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 590 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 591 AMDGPU_GPU_PAGE_SIZE; 592 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 593 594 dev_info.cu_active_number = adev->gfx.cu_info.number; 595 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 596 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 597 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 598 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 599 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 600 sizeof(adev->gfx.cu_info.bitmap)); 601 dev_info.vram_type = adev->mc.vram_type; 602 dev_info.vram_bit_width = adev->mc.vram_width; 603 dev_info.vce_harvest_config = adev->vce.harvest_config; 604 dev_info.gc_double_offchip_lds_buf = 605 adev->gfx.config.double_offchip_lds_buf; 606 607 if (amdgpu_ngg) { 608 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 609 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 610 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 611 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 612 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 613 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 614 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 615 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 616 } 617 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 618 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 619 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 620 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 621 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 622 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 623 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 624 625 return copy_to_user(out, &dev_info, 626 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 627 } 628 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 629 unsigned i; 630 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 631 struct amd_vce_state *vce_state; 632 633 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 634 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 635 if (vce_state) { 636 vce_clk_table.entries[i].sclk = vce_state->sclk; 637 vce_clk_table.entries[i].mclk = vce_state->mclk; 638 vce_clk_table.entries[i].eclk = vce_state->evclk; 639 vce_clk_table.num_valid_entries++; 640 } 641 } 642 643 return copy_to_user(out, &vce_clk_table, 644 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 645 } 646 case AMDGPU_INFO_VBIOS: { 647 uint32_t bios_size = adev->bios_size; 648 649 switch (info->vbios_info.type) { 650 case AMDGPU_INFO_VBIOS_SIZE: 651 return copy_to_user(out, &bios_size, 652 min((size_t)size, sizeof(bios_size))) 653 ? -EFAULT : 0; 654 case AMDGPU_INFO_VBIOS_IMAGE: { 655 uint8_t *bios; 656 uint32_t bios_offset = info->vbios_info.offset; 657 658 if (bios_offset >= bios_size) 659 return -EINVAL; 660 661 bios = adev->bios + bios_offset; 662 return copy_to_user(out, bios, 663 min((size_t)size, (size_t)(bios_size - bios_offset))) 664 ? -EFAULT : 0; 665 } 666 default: 667 DRM_DEBUG_KMS("Invalid request %d\n", 668 info->vbios_info.type); 669 return -EINVAL; 670 } 671 } 672 case AMDGPU_INFO_NUM_HANDLES: { 673 struct drm_amdgpu_info_num_handles handle; 674 675 switch (info->query_hw_ip.type) { 676 case AMDGPU_HW_IP_UVD: 677 /* Starting Polaris, we support unlimited UVD handles */ 678 if (adev->asic_type < CHIP_POLARIS10) { 679 handle.uvd_max_handles = adev->uvd.max_handles; 680 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 681 682 return copy_to_user(out, &handle, 683 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 684 } else { 685 return -ENODATA; 686 } 687 688 break; 689 default: 690 return -EINVAL; 691 } 692 } 693 case AMDGPU_INFO_SENSOR: { 694 struct pp_gpu_power query = {0}; 695 int query_size = sizeof(query); 696 697 if (amdgpu_dpm == 0) 698 return -ENOENT; 699 700 switch (info->sensor_info.type) { 701 case AMDGPU_INFO_SENSOR_GFX_SCLK: 702 /* get sclk in Mhz */ 703 if (amdgpu_dpm_read_sensor(adev, 704 AMDGPU_PP_SENSOR_GFX_SCLK, 705 (void *)&ui32, &ui32_size)) { 706 return -EINVAL; 707 } 708 ui32 /= 100; 709 break; 710 case AMDGPU_INFO_SENSOR_GFX_MCLK: 711 /* get mclk in Mhz */ 712 if (amdgpu_dpm_read_sensor(adev, 713 AMDGPU_PP_SENSOR_GFX_MCLK, 714 (void *)&ui32, &ui32_size)) { 715 return -EINVAL; 716 } 717 ui32 /= 100; 718 break; 719 case AMDGPU_INFO_SENSOR_GPU_TEMP: 720 /* get temperature in millidegrees C */ 721 if (amdgpu_dpm_read_sensor(adev, 722 AMDGPU_PP_SENSOR_GPU_TEMP, 723 (void *)&ui32, &ui32_size)) { 724 return -EINVAL; 725 } 726 break; 727 case AMDGPU_INFO_SENSOR_GPU_LOAD: 728 /* get GPU load */ 729 if (amdgpu_dpm_read_sensor(adev, 730 AMDGPU_PP_SENSOR_GPU_LOAD, 731 (void *)&ui32, &ui32_size)) { 732 return -EINVAL; 733 } 734 break; 735 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 736 /* get average GPU power */ 737 if (amdgpu_dpm_read_sensor(adev, 738 AMDGPU_PP_SENSOR_GPU_POWER, 739 (void *)&query, &query_size)) { 740 return -EINVAL; 741 } 742 ui32 = query.average_gpu_power >> 8; 743 break; 744 case AMDGPU_INFO_SENSOR_VDDNB: 745 /* get VDDNB in millivolts */ 746 if (amdgpu_dpm_read_sensor(adev, 747 AMDGPU_PP_SENSOR_VDDNB, 748 (void *)&ui32, &ui32_size)) { 749 return -EINVAL; 750 } 751 break; 752 case AMDGPU_INFO_SENSOR_VDDGFX: 753 /* get VDDGFX in millivolts */ 754 if (amdgpu_dpm_read_sensor(adev, 755 AMDGPU_PP_SENSOR_VDDGFX, 756 (void *)&ui32, &ui32_size)) { 757 return -EINVAL; 758 } 759 break; 760 default: 761 DRM_DEBUG_KMS("Invalid request %d\n", 762 info->sensor_info.type); 763 return -EINVAL; 764 } 765 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 766 } 767 default: 768 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 769 return -EINVAL; 770 } 771 return 0; 772 } 773 774 775 /* 776 * Outdated mess for old drm with Xorg being in charge (void function now). 777 */ 778 /** 779 * amdgpu_driver_lastclose_kms - drm callback for last close 780 * 781 * @dev: drm dev pointer 782 * 783 * Switch vga_switcheroo state after last close (all asics). 784 */ 785 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 786 { 787 struct amdgpu_device *adev = dev->dev_private; 788 789 amdgpu_fbdev_restore_mode(adev); 790 vga_switcheroo_process_delayed_switch(); 791 } 792 793 bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, 794 struct amdgpu_fpriv *fpriv) 795 { 796 return fpriv->vram_lost_counter != atomic_read(&adev->vram_lost_counter); 797 } 798 799 /** 800 * amdgpu_driver_open_kms - drm callback for open 801 * 802 * @dev: drm dev pointer 803 * @file_priv: drm file 804 * 805 * On device open, init vm on cayman+ (all asics). 806 * Returns 0 on success, error on failure. 807 */ 808 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 809 { 810 struct amdgpu_device *adev = dev->dev_private; 811 struct amdgpu_fpriv *fpriv; 812 int r; 813 814 file_priv->driver_priv = NULL; 815 816 r = pm_runtime_get_sync(dev->dev); 817 if (r < 0) 818 return r; 819 820 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 821 if (unlikely(!fpriv)) { 822 r = -ENOMEM; 823 goto out_suspend; 824 } 825 826 r = amdgpu_vm_init(adev, &fpriv->vm, 827 AMDGPU_VM_CONTEXT_GFX); 828 if (r) { 829 kfree(fpriv); 830 goto out_suspend; 831 } 832 833 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 834 if (!fpriv->prt_va) { 835 r = -ENOMEM; 836 amdgpu_vm_fini(adev, &fpriv->vm); 837 kfree(fpriv); 838 goto out_suspend; 839 } 840 841 if (amdgpu_sriov_vf(adev)) { 842 r = amdgpu_map_static_csa(adev, &fpriv->vm); 843 if (r) 844 goto out_suspend; 845 } 846 847 mutex_init(&fpriv->bo_list_lock); 848 idr_init(&fpriv->bo_list_handles); 849 850 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 851 852 fpriv->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 853 file_priv->driver_priv = fpriv; 854 855 out_suspend: 856 pm_runtime_mark_last_busy(dev->dev); 857 pm_runtime_put_autosuspend(dev->dev); 858 859 return r; 860 } 861 862 /** 863 * amdgpu_driver_postclose_kms - drm callback for post close 864 * 865 * @dev: drm dev pointer 866 * @file_priv: drm file 867 * 868 * On device post close, tear down vm on cayman+ (all asics). 869 */ 870 void amdgpu_driver_postclose_kms(struct drm_device *dev, 871 struct drm_file *file_priv) 872 { 873 struct amdgpu_device *adev = dev->dev_private; 874 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 875 struct amdgpu_bo_list *list; 876 int handle; 877 878 if (!fpriv) 879 return; 880 881 pm_runtime_get_sync(dev->dev); 882 883 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 884 885 if (adev->asic_type != CHIP_RAVEN) { 886 amdgpu_uvd_free_handles(adev, file_priv); 887 amdgpu_vce_free_handles(adev, file_priv); 888 } 889 890 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 891 892 if (amdgpu_sriov_vf(adev)) { 893 /* TODO: how to handle reserve failure */ 894 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 895 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va); 896 fpriv->vm.csa_bo_va = NULL; 897 amdgpu_bo_unreserve(adev->virt.csa_obj); 898 } 899 900 amdgpu_vm_fini(adev, &fpriv->vm); 901 902 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 903 amdgpu_bo_list_free(list); 904 905 idr_destroy(&fpriv->bo_list_handles); 906 mutex_destroy(&fpriv->bo_list_lock); 907 908 kfree(fpriv); 909 file_priv->driver_priv = NULL; 910 911 pm_runtime_mark_last_busy(dev->dev); 912 pm_runtime_put_autosuspend(dev->dev); 913 } 914 915 /* 916 * VBlank related functions. 917 */ 918 /** 919 * amdgpu_get_vblank_counter_kms - get frame count 920 * 921 * @dev: drm dev pointer 922 * @pipe: crtc to get the frame count from 923 * 924 * Gets the frame count on the requested crtc (all asics). 925 * Returns frame count on success, -EINVAL on failure. 926 */ 927 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 928 { 929 struct amdgpu_device *adev = dev->dev_private; 930 int vpos, hpos, stat; 931 u32 count; 932 933 if (pipe >= adev->mode_info.num_crtc) { 934 DRM_ERROR("Invalid crtc %u\n", pipe); 935 return -EINVAL; 936 } 937 938 /* The hw increments its frame counter at start of vsync, not at start 939 * of vblank, as is required by DRM core vblank counter handling. 940 * Cook the hw count here to make it appear to the caller as if it 941 * incremented at start of vblank. We measure distance to start of 942 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 943 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 944 * result by 1 to give the proper appearance to caller. 945 */ 946 if (adev->mode_info.crtcs[pipe]) { 947 /* Repeat readout if needed to provide stable result if 948 * we cross start of vsync during the queries. 949 */ 950 do { 951 count = amdgpu_display_vblank_get_counter(adev, pipe); 952 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 953 * distance to start of vblank, instead of regular 954 * vertical scanout pos. 955 */ 956 stat = amdgpu_get_crtc_scanoutpos( 957 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 958 &vpos, &hpos, NULL, NULL, 959 &adev->mode_info.crtcs[pipe]->base.hwmode); 960 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 961 962 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 963 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 964 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 965 } else { 966 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 967 pipe, vpos); 968 969 /* Bump counter if we are at >= leading edge of vblank, 970 * but before vsync where vpos would turn negative and 971 * the hw counter really increments. 972 */ 973 if (vpos >= 0) 974 count++; 975 } 976 } else { 977 /* Fallback to use value as is. */ 978 count = amdgpu_display_vblank_get_counter(adev, pipe); 979 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 980 } 981 982 return count; 983 } 984 985 /** 986 * amdgpu_enable_vblank_kms - enable vblank interrupt 987 * 988 * @dev: drm dev pointer 989 * @pipe: crtc to enable vblank interrupt for 990 * 991 * Enable the interrupt on the requested crtc (all asics). 992 * Returns 0 on success, -EINVAL on failure. 993 */ 994 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 995 { 996 struct amdgpu_device *adev = dev->dev_private; 997 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 998 999 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1000 } 1001 1002 /** 1003 * amdgpu_disable_vblank_kms - disable vblank interrupt 1004 * 1005 * @dev: drm dev pointer 1006 * @pipe: crtc to disable vblank interrupt for 1007 * 1008 * Disable the interrupt on the requested crtc (all asics). 1009 */ 1010 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1011 { 1012 struct amdgpu_device *adev = dev->dev_private; 1013 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 1014 1015 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1016 } 1017 1018 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1019 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1020 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1021 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1022 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1023 /* KMS */ 1024 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1025 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1026 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1027 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1028 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1029 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1030 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1031 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1032 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1033 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1034 }; 1035 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1036 1037 /* 1038 * Debugfs info 1039 */ 1040 #if defined(CONFIG_DEBUG_FS) 1041 1042 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1043 { 1044 struct drm_info_node *node = (struct drm_info_node *) m->private; 1045 struct drm_device *dev = node->minor->dev; 1046 struct amdgpu_device *adev = dev->dev_private; 1047 struct drm_amdgpu_info_firmware fw_info; 1048 struct drm_amdgpu_query_fw query_fw; 1049 int ret, i; 1050 1051 /* VCE */ 1052 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1053 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1054 if (ret) 1055 return ret; 1056 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1057 fw_info.feature, fw_info.ver); 1058 1059 /* UVD */ 1060 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1061 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1062 if (ret) 1063 return ret; 1064 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1065 fw_info.feature, fw_info.ver); 1066 1067 /* GMC */ 1068 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1069 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1070 if (ret) 1071 return ret; 1072 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1073 fw_info.feature, fw_info.ver); 1074 1075 /* ME */ 1076 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1077 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1078 if (ret) 1079 return ret; 1080 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1081 fw_info.feature, fw_info.ver); 1082 1083 /* PFP */ 1084 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1085 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1086 if (ret) 1087 return ret; 1088 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1089 fw_info.feature, fw_info.ver); 1090 1091 /* CE */ 1092 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1093 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1094 if (ret) 1095 return ret; 1096 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1097 fw_info.feature, fw_info.ver); 1098 1099 /* RLC */ 1100 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1101 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1102 if (ret) 1103 return ret; 1104 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1105 fw_info.feature, fw_info.ver); 1106 1107 /* MEC */ 1108 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1109 query_fw.index = 0; 1110 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1111 if (ret) 1112 return ret; 1113 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1114 fw_info.feature, fw_info.ver); 1115 1116 /* MEC2 */ 1117 if (adev->asic_type == CHIP_KAVERI || 1118 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1119 query_fw.index = 1; 1120 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1121 if (ret) 1122 return ret; 1123 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1124 fw_info.feature, fw_info.ver); 1125 } 1126 1127 /* PSP SOS */ 1128 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1129 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1130 if (ret) 1131 return ret; 1132 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1133 fw_info.feature, fw_info.ver); 1134 1135 1136 /* PSP ASD */ 1137 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1138 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1139 if (ret) 1140 return ret; 1141 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1142 fw_info.feature, fw_info.ver); 1143 1144 /* SMC */ 1145 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1146 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1147 if (ret) 1148 return ret; 1149 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1150 fw_info.feature, fw_info.ver); 1151 1152 /* SDMA */ 1153 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1154 for (i = 0; i < adev->sdma.num_instances; i++) { 1155 query_fw.index = i; 1156 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1157 if (ret) 1158 return ret; 1159 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1160 i, fw_info.feature, fw_info.ver); 1161 } 1162 1163 return 0; 1164 } 1165 1166 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1167 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1168 }; 1169 #endif 1170 1171 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1172 { 1173 #if defined(CONFIG_DEBUG_FS) 1174 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1175 ARRAY_SIZE(amdgpu_firmware_info_list)); 1176 #else 1177 return 0; 1178 #endif 1179 } 1180