1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (amdgpu_sriov_vf(adev)) 92 amdgpu_virt_request_full_gpu(adev, false); 93 94 if (amdgpu_device_is_px(dev)) { 95 pm_runtime_get_sync(dev->dev); 96 pm_runtime_forbid(dev->dev); 97 } 98 99 amdgpu_acpi_fini(adev); 100 101 amdgpu_device_fini(adev); 102 103 done_free: 104 kfree(adev); 105 dev->dev_private = NULL; 106 } 107 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 109 { 110 struct amdgpu_gpu_instance *gpu_instance; 111 112 mutex_lock(&mgpu_info.mutex); 113 114 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 115 DRM_ERROR("Cannot register more gpu instance\n"); 116 mutex_unlock(&mgpu_info.mutex); 117 return; 118 } 119 120 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 121 gpu_instance->adev = adev; 122 gpu_instance->mgpu_fan_enabled = 0; 123 124 mgpu_info.num_gpu++; 125 if (adev->flags & AMD_IS_APU) 126 mgpu_info.num_apu++; 127 else 128 mgpu_info.num_dgpu++; 129 130 mutex_unlock(&mgpu_info.mutex); 131 } 132 133 /** 134 * amdgpu_driver_load_kms - Main load function for KMS. 135 * 136 * @dev: drm dev pointer 137 * @flags: device flags 138 * 139 * This is the main load function for KMS (all asics). 140 * Returns 0 on success, error on failure. 141 */ 142 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 143 { 144 struct amdgpu_device *adev; 145 int r, acpi_status; 146 147 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 148 if (adev == NULL) { 149 return -ENOMEM; 150 } 151 dev->dev_private = (void *)adev; 152 153 if ((amdgpu_runtime_pm != 0) && 154 amdgpu_has_atpx() && 155 (amdgpu_is_atpx_hybrid() || 156 amdgpu_has_atpx_dgpu_power_cntl()) && 157 ((flags & AMD_IS_APU) == 0) && 158 !pci_is_thunderbolt_attached(dev->pdev)) 159 flags |= AMD_IS_PX; 160 161 /* amdgpu_device_init should report only fatal error 162 * like memory allocation failure or iomapping failure, 163 * or memory manager initialization failure, it must 164 * properly initialize the GPU MC controller and permit 165 * VRAM allocation 166 */ 167 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 168 if (r) { 169 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 170 goto out; 171 } 172 173 /* Call ACPI methods: require modeset init 174 * but failure is not fatal 175 */ 176 if (!r) { 177 acpi_status = amdgpu_acpi_init(adev); 178 if (acpi_status) 179 dev_dbg(&dev->pdev->dev, 180 "Error during ACPI methods call\n"); 181 } 182 183 if (amdgpu_device_is_px(dev)) { 184 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); 185 pm_runtime_use_autosuspend(dev->dev); 186 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 187 pm_runtime_set_active(dev->dev); 188 pm_runtime_allow(dev->dev); 189 pm_runtime_mark_last_busy(dev->dev); 190 pm_runtime_put_autosuspend(dev->dev); 191 } 192 193 amdgpu_register_gpu_instance(adev); 194 out: 195 if (r) { 196 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 197 if (adev->rmmio && amdgpu_device_is_px(dev)) 198 pm_runtime_put_noidle(dev->dev); 199 amdgpu_driver_unload_kms(dev); 200 } 201 202 return r; 203 } 204 205 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 206 struct drm_amdgpu_query_fw *query_fw, 207 struct amdgpu_device *adev) 208 { 209 switch (query_fw->fw_type) { 210 case AMDGPU_INFO_FW_VCE: 211 fw_info->ver = adev->vce.fw_version; 212 fw_info->feature = adev->vce.fb_version; 213 break; 214 case AMDGPU_INFO_FW_UVD: 215 fw_info->ver = adev->uvd.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_VCN: 219 fw_info->ver = adev->vcn.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GMC: 223 fw_info->ver = adev->gmc.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_GFX_ME: 227 fw_info->ver = adev->gfx.me_fw_version; 228 fw_info->feature = adev->gfx.me_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_PFP: 231 fw_info->ver = adev->gfx.pfp_fw_version; 232 fw_info->feature = adev->gfx.pfp_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_CE: 235 fw_info->ver = adev->gfx.ce_fw_version; 236 fw_info->feature = adev->gfx.ce_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC: 239 fw_info->ver = adev->gfx.rlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 243 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 247 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 248 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 251 fw_info->ver = adev->gfx.rlc_srls_fw_version; 252 fw_info->feature = adev->gfx.rlc_srls_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_MEC: 255 if (query_fw->index == 0) { 256 fw_info->ver = adev->gfx.mec_fw_version; 257 fw_info->feature = adev->gfx.mec_feature_version; 258 } else if (query_fw->index == 1) { 259 fw_info->ver = adev->gfx.mec2_fw_version; 260 fw_info->feature = adev->gfx.mec2_feature_version; 261 } else 262 return -EINVAL; 263 break; 264 case AMDGPU_INFO_FW_SMC: 265 fw_info->ver = adev->pm.fw_version; 266 fw_info->feature = 0; 267 break; 268 case AMDGPU_INFO_FW_TA: 269 if (query_fw->index > 1) 270 return -EINVAL; 271 if (query_fw->index == 0) { 272 fw_info->ver = adev->psp.ta_fw_version; 273 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 274 } else { 275 fw_info->ver = adev->psp.ta_fw_version; 276 fw_info->feature = adev->psp.ta_ras_ucode_version; 277 } 278 break; 279 case AMDGPU_INFO_FW_SDMA: 280 if (query_fw->index >= adev->sdma.num_instances) 281 return -EINVAL; 282 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 283 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 284 break; 285 case AMDGPU_INFO_FW_SOS: 286 fw_info->ver = adev->psp.sos_fw_version; 287 fw_info->feature = adev->psp.sos_feature_version; 288 break; 289 case AMDGPU_INFO_FW_ASD: 290 fw_info->ver = adev->psp.asd_fw_version; 291 fw_info->feature = adev->psp.asd_feature_version; 292 break; 293 case AMDGPU_INFO_FW_DMCU: 294 fw_info->ver = adev->dm.dmcu_fw_version; 295 fw_info->feature = 0; 296 break; 297 default: 298 return -EINVAL; 299 } 300 return 0; 301 } 302 303 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 304 struct drm_amdgpu_info *info, 305 struct drm_amdgpu_info_hw_ip *result) 306 { 307 uint32_t ib_start_alignment = 0; 308 uint32_t ib_size_alignment = 0; 309 enum amd_ip_block_type type; 310 unsigned int num_rings = 0; 311 unsigned int i, j; 312 313 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 314 return -EINVAL; 315 316 switch (info->query_hw_ip.type) { 317 case AMDGPU_HW_IP_GFX: 318 type = AMD_IP_BLOCK_TYPE_GFX; 319 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 320 if (adev->gfx.gfx_ring[i].sched.ready) 321 ++num_rings; 322 ib_start_alignment = 32; 323 ib_size_alignment = 32; 324 break; 325 case AMDGPU_HW_IP_COMPUTE: 326 type = AMD_IP_BLOCK_TYPE_GFX; 327 for (i = 0; i < adev->gfx.num_compute_rings; i++) 328 if (adev->gfx.compute_ring[i].sched.ready) 329 ++num_rings; 330 ib_start_alignment = 32; 331 ib_size_alignment = 32; 332 break; 333 case AMDGPU_HW_IP_DMA: 334 type = AMD_IP_BLOCK_TYPE_SDMA; 335 for (i = 0; i < adev->sdma.num_instances; i++) 336 if (adev->sdma.instance[i].ring.sched.ready) 337 ++num_rings; 338 ib_start_alignment = 256; 339 ib_size_alignment = 4; 340 break; 341 case AMDGPU_HW_IP_UVD: 342 type = AMD_IP_BLOCK_TYPE_UVD; 343 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 344 if (adev->uvd.harvest_config & (1 << i)) 345 continue; 346 347 if (adev->uvd.inst[i].ring.sched.ready) 348 ++num_rings; 349 } 350 ib_start_alignment = 64; 351 ib_size_alignment = 64; 352 break; 353 case AMDGPU_HW_IP_VCE: 354 type = AMD_IP_BLOCK_TYPE_VCE; 355 for (i = 0; i < adev->vce.num_rings; i++) 356 if (adev->vce.ring[i].sched.ready) 357 ++num_rings; 358 ib_start_alignment = 4; 359 ib_size_alignment = 1; 360 break; 361 case AMDGPU_HW_IP_UVD_ENC: 362 type = AMD_IP_BLOCK_TYPE_UVD; 363 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 364 if (adev->uvd.harvest_config & (1 << i)) 365 continue; 366 367 for (j = 0; j < adev->uvd.num_enc_rings; j++) 368 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 369 ++num_rings; 370 } 371 ib_start_alignment = 64; 372 ib_size_alignment = 64; 373 break; 374 case AMDGPU_HW_IP_VCN_DEC: 375 type = AMD_IP_BLOCK_TYPE_VCN; 376 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 377 if (adev->uvd.harvest_config & (1 << i)) 378 continue; 379 380 if (adev->vcn.inst[i].ring_dec.sched.ready) 381 ++num_rings; 382 } 383 ib_start_alignment = 16; 384 ib_size_alignment = 16; 385 break; 386 case AMDGPU_HW_IP_VCN_ENC: 387 type = AMD_IP_BLOCK_TYPE_VCN; 388 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 389 if (adev->uvd.harvest_config & (1 << i)) 390 continue; 391 392 for (j = 0; j < adev->vcn.num_enc_rings; j++) 393 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 394 ++num_rings; 395 } 396 ib_start_alignment = 64; 397 ib_size_alignment = 1; 398 break; 399 case AMDGPU_HW_IP_VCN_JPEG: 400 type = AMD_IP_BLOCK_TYPE_VCN; 401 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 402 if (adev->uvd.harvest_config & (1 << i)) 403 continue; 404 405 if (adev->vcn.inst[i].ring_jpeg.sched.ready) 406 ++num_rings; 407 } 408 ib_start_alignment = 16; 409 ib_size_alignment = 16; 410 break; 411 default: 412 return -EINVAL; 413 } 414 415 for (i = 0; i < adev->num_ip_blocks; i++) 416 if (adev->ip_blocks[i].version->type == type && 417 adev->ip_blocks[i].status.valid) 418 break; 419 420 if (i == adev->num_ip_blocks) 421 return 0; 422 423 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 424 num_rings); 425 426 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 427 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 428 result->capabilities_flags = 0; 429 result->available_rings = (1 << num_rings) - 1; 430 result->ib_start_alignment = ib_start_alignment; 431 result->ib_size_alignment = ib_size_alignment; 432 return 0; 433 } 434 435 /* 436 * Userspace get information ioctl 437 */ 438 /** 439 * amdgpu_info_ioctl - answer a device specific request. 440 * 441 * @adev: amdgpu device pointer 442 * @data: request object 443 * @filp: drm filp 444 * 445 * This function is used to pass device specific parameters to the userspace 446 * drivers. Examples include: pci device id, pipeline parms, tiling params, 447 * etc. (all asics). 448 * Returns 0 on success, -EINVAL on failure. 449 */ 450 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 451 { 452 struct amdgpu_device *adev = dev->dev_private; 453 struct drm_amdgpu_info *info = data; 454 struct amdgpu_mode_info *minfo = &adev->mode_info; 455 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 456 uint32_t size = info->return_size; 457 struct drm_crtc *crtc; 458 uint32_t ui32 = 0; 459 uint64_t ui64 = 0; 460 int i, found; 461 int ui32_size = sizeof(ui32); 462 463 if (!info->return_size || !info->return_pointer) 464 return -EINVAL; 465 466 switch (info->query) { 467 case AMDGPU_INFO_ACCEL_WORKING: 468 ui32 = adev->accel_working; 469 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 470 case AMDGPU_INFO_CRTC_FROM_ID: 471 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 472 crtc = (struct drm_crtc *)minfo->crtcs[i]; 473 if (crtc && crtc->base.id == info->mode_crtc.id) { 474 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 475 ui32 = amdgpu_crtc->crtc_id; 476 found = 1; 477 break; 478 } 479 } 480 if (!found) { 481 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 482 return -EINVAL; 483 } 484 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 485 case AMDGPU_INFO_HW_IP_INFO: { 486 struct drm_amdgpu_info_hw_ip ip = {}; 487 int ret; 488 489 ret = amdgpu_hw_ip_info(adev, info, &ip); 490 if (ret) 491 return ret; 492 493 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 494 return ret ? -EFAULT : 0; 495 } 496 case AMDGPU_INFO_HW_IP_COUNT: { 497 enum amd_ip_block_type type; 498 uint32_t count = 0; 499 500 switch (info->query_hw_ip.type) { 501 case AMDGPU_HW_IP_GFX: 502 type = AMD_IP_BLOCK_TYPE_GFX; 503 break; 504 case AMDGPU_HW_IP_COMPUTE: 505 type = AMD_IP_BLOCK_TYPE_GFX; 506 break; 507 case AMDGPU_HW_IP_DMA: 508 type = AMD_IP_BLOCK_TYPE_SDMA; 509 break; 510 case AMDGPU_HW_IP_UVD: 511 type = AMD_IP_BLOCK_TYPE_UVD; 512 break; 513 case AMDGPU_HW_IP_VCE: 514 type = AMD_IP_BLOCK_TYPE_VCE; 515 break; 516 case AMDGPU_HW_IP_UVD_ENC: 517 type = AMD_IP_BLOCK_TYPE_UVD; 518 break; 519 case AMDGPU_HW_IP_VCN_DEC: 520 case AMDGPU_HW_IP_VCN_ENC: 521 case AMDGPU_HW_IP_VCN_JPEG: 522 type = AMD_IP_BLOCK_TYPE_VCN; 523 break; 524 default: 525 return -EINVAL; 526 } 527 528 for (i = 0; i < adev->num_ip_blocks; i++) 529 if (adev->ip_blocks[i].version->type == type && 530 adev->ip_blocks[i].status.valid && 531 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 532 count++; 533 534 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 535 } 536 case AMDGPU_INFO_TIMESTAMP: 537 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 538 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 539 case AMDGPU_INFO_FW_VERSION: { 540 struct drm_amdgpu_info_firmware fw_info; 541 int ret; 542 543 /* We only support one instance of each IP block right now. */ 544 if (info->query_fw.ip_instance != 0) 545 return -EINVAL; 546 547 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 548 if (ret) 549 return ret; 550 551 return copy_to_user(out, &fw_info, 552 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 553 } 554 case AMDGPU_INFO_NUM_BYTES_MOVED: 555 ui64 = atomic64_read(&adev->num_bytes_moved); 556 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 557 case AMDGPU_INFO_NUM_EVICTIONS: 558 ui64 = atomic64_read(&adev->num_evictions); 559 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 560 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 561 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 562 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 563 case AMDGPU_INFO_VRAM_USAGE: 564 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 565 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 566 case AMDGPU_INFO_VIS_VRAM_USAGE: 567 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 568 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 569 case AMDGPU_INFO_GTT_USAGE: 570 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 571 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 572 case AMDGPU_INFO_GDS_CONFIG: { 573 struct drm_amdgpu_info_gds gds_info; 574 575 memset(&gds_info, 0, sizeof(gds_info)); 576 gds_info.compute_partition_size = adev->gds.gds_size; 577 gds_info.gds_total_size = adev->gds.gds_size; 578 gds_info.gws_per_compute_partition = adev->gds.gws_size; 579 gds_info.oa_per_compute_partition = adev->gds.oa_size; 580 return copy_to_user(out, &gds_info, 581 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 582 } 583 case AMDGPU_INFO_VRAM_GTT: { 584 struct drm_amdgpu_info_vram_gtt vram_gtt; 585 586 vram_gtt.vram_size = adev->gmc.real_vram_size - 587 atomic64_read(&adev->vram_pin_size) - 588 AMDGPU_VM_RESERVED_VRAM; 589 vram_gtt.vram_cpu_accessible_size = 590 min(adev->gmc.visible_vram_size - 591 atomic64_read(&adev->visible_pin_size), 592 vram_gtt.vram_size); 593 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 594 vram_gtt.gtt_size *= PAGE_SIZE; 595 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 596 return copy_to_user(out, &vram_gtt, 597 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 598 } 599 case AMDGPU_INFO_MEMORY: { 600 struct drm_amdgpu_memory_info mem; 601 602 memset(&mem, 0, sizeof(mem)); 603 mem.vram.total_heap_size = adev->gmc.real_vram_size; 604 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 605 atomic64_read(&adev->vram_pin_size) - 606 AMDGPU_VM_RESERVED_VRAM; 607 mem.vram.heap_usage = 608 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 609 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 610 611 mem.cpu_accessible_vram.total_heap_size = 612 adev->gmc.visible_vram_size; 613 mem.cpu_accessible_vram.usable_heap_size = 614 min(adev->gmc.visible_vram_size - 615 atomic64_read(&adev->visible_pin_size), 616 mem.vram.usable_heap_size); 617 mem.cpu_accessible_vram.heap_usage = 618 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 619 mem.cpu_accessible_vram.max_allocation = 620 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 621 622 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 623 mem.gtt.total_heap_size *= PAGE_SIZE; 624 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 625 atomic64_read(&adev->gart_pin_size); 626 mem.gtt.heap_usage = 627 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 628 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 629 630 return copy_to_user(out, &mem, 631 min((size_t)size, sizeof(mem))) 632 ? -EFAULT : 0; 633 } 634 case AMDGPU_INFO_READ_MMR_REG: { 635 unsigned n, alloc_size; 636 uint32_t *regs; 637 unsigned se_num = (info->read_mmr_reg.instance >> 638 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 639 AMDGPU_INFO_MMR_SE_INDEX_MASK; 640 unsigned sh_num = (info->read_mmr_reg.instance >> 641 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 642 AMDGPU_INFO_MMR_SH_INDEX_MASK; 643 644 /* set full masks if the userspace set all bits 645 * in the bitfields */ 646 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 647 se_num = 0xffffffff; 648 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 649 sh_num = 0xffffffff; 650 651 if (info->read_mmr_reg.count > 128) 652 return -EINVAL; 653 654 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 655 if (!regs) 656 return -ENOMEM; 657 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 658 659 for (i = 0; i < info->read_mmr_reg.count; i++) 660 if (amdgpu_asic_read_register(adev, se_num, sh_num, 661 info->read_mmr_reg.dword_offset + i, 662 ®s[i])) { 663 DRM_DEBUG_KMS("unallowed offset %#x\n", 664 info->read_mmr_reg.dword_offset + i); 665 kfree(regs); 666 return -EFAULT; 667 } 668 n = copy_to_user(out, regs, min(size, alloc_size)); 669 kfree(regs); 670 return n ? -EFAULT : 0; 671 } 672 case AMDGPU_INFO_DEV_INFO: { 673 struct drm_amdgpu_info_device dev_info = {}; 674 uint64_t vm_size; 675 676 dev_info.device_id = dev->pdev->device; 677 dev_info.chip_rev = adev->rev_id; 678 dev_info.external_rev = adev->external_rev_id; 679 dev_info.pci_rev = dev->pdev->revision; 680 dev_info.family = adev->family; 681 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 682 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 683 /* return all clocks in KHz */ 684 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 685 if (adev->pm.dpm_enabled) { 686 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 687 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 688 } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) && 689 adev->virt.ops->get_pp_clk) { 690 dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev, false) * 10; 691 dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev, false) * 10; 692 } else { 693 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 694 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 695 } 696 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 697 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 698 adev->gfx.config.max_shader_engines; 699 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 700 dev_info._pad = 0; 701 dev_info.ids_flags = 0; 702 if (adev->flags & AMD_IS_APU) 703 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 704 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 705 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 706 707 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 708 vm_size -= AMDGPU_VA_RESERVED_SIZE; 709 710 /* Older VCE FW versions are buggy and can handle only 40bits */ 711 if (adev->vce.fw_version && 712 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 713 vm_size = min(vm_size, 1ULL << 40); 714 715 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 716 dev_info.virtual_address_max = 717 min(vm_size, AMDGPU_GMC_HOLE_START); 718 719 if (vm_size > AMDGPU_GMC_HOLE_START) { 720 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 721 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 722 } 723 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 724 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 725 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 726 dev_info.cu_active_number = adev->gfx.cu_info.number; 727 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 728 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 729 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 730 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 731 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 732 sizeof(adev->gfx.cu_info.bitmap)); 733 dev_info.vram_type = adev->gmc.vram_type; 734 dev_info.vram_bit_width = adev->gmc.vram_width; 735 dev_info.vce_harvest_config = adev->vce.harvest_config; 736 dev_info.gc_double_offchip_lds_buf = 737 adev->gfx.config.double_offchip_lds_buf; 738 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 739 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 740 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 741 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 742 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 743 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 744 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 745 746 if (adev->family >= AMDGPU_FAMILY_NV) 747 dev_info.pa_sc_tile_steering_override = 748 adev->gfx.config.pa_sc_tile_steering_override; 749 750 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 751 752 return copy_to_user(out, &dev_info, 753 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 754 } 755 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 756 unsigned i; 757 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 758 struct amd_vce_state *vce_state; 759 760 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 761 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 762 if (vce_state) { 763 vce_clk_table.entries[i].sclk = vce_state->sclk; 764 vce_clk_table.entries[i].mclk = vce_state->mclk; 765 vce_clk_table.entries[i].eclk = vce_state->evclk; 766 vce_clk_table.num_valid_entries++; 767 } 768 } 769 770 return copy_to_user(out, &vce_clk_table, 771 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 772 } 773 case AMDGPU_INFO_VBIOS: { 774 uint32_t bios_size = adev->bios_size; 775 776 switch (info->vbios_info.type) { 777 case AMDGPU_INFO_VBIOS_SIZE: 778 return copy_to_user(out, &bios_size, 779 min((size_t)size, sizeof(bios_size))) 780 ? -EFAULT : 0; 781 case AMDGPU_INFO_VBIOS_IMAGE: { 782 uint8_t *bios; 783 uint32_t bios_offset = info->vbios_info.offset; 784 785 if (bios_offset >= bios_size) 786 return -EINVAL; 787 788 bios = adev->bios + bios_offset; 789 return copy_to_user(out, bios, 790 min((size_t)size, (size_t)(bios_size - bios_offset))) 791 ? -EFAULT : 0; 792 } 793 default: 794 DRM_DEBUG_KMS("Invalid request %d\n", 795 info->vbios_info.type); 796 return -EINVAL; 797 } 798 } 799 case AMDGPU_INFO_NUM_HANDLES: { 800 struct drm_amdgpu_info_num_handles handle; 801 802 switch (info->query_hw_ip.type) { 803 case AMDGPU_HW_IP_UVD: 804 /* Starting Polaris, we support unlimited UVD handles */ 805 if (adev->asic_type < CHIP_POLARIS10) { 806 handle.uvd_max_handles = adev->uvd.max_handles; 807 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 808 809 return copy_to_user(out, &handle, 810 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 811 } else { 812 return -ENODATA; 813 } 814 815 break; 816 default: 817 return -EINVAL; 818 } 819 } 820 case AMDGPU_INFO_SENSOR: { 821 if (!adev->pm.dpm_enabled) 822 return -ENOENT; 823 824 switch (info->sensor_info.type) { 825 case AMDGPU_INFO_SENSOR_GFX_SCLK: 826 /* get sclk in Mhz */ 827 if (amdgpu_dpm_read_sensor(adev, 828 AMDGPU_PP_SENSOR_GFX_SCLK, 829 (void *)&ui32, &ui32_size)) { 830 return -EINVAL; 831 } 832 ui32 /= 100; 833 break; 834 case AMDGPU_INFO_SENSOR_GFX_MCLK: 835 /* get mclk in Mhz */ 836 if (amdgpu_dpm_read_sensor(adev, 837 AMDGPU_PP_SENSOR_GFX_MCLK, 838 (void *)&ui32, &ui32_size)) { 839 return -EINVAL; 840 } 841 ui32 /= 100; 842 break; 843 case AMDGPU_INFO_SENSOR_GPU_TEMP: 844 /* get temperature in millidegrees C */ 845 if (amdgpu_dpm_read_sensor(adev, 846 AMDGPU_PP_SENSOR_GPU_TEMP, 847 (void *)&ui32, &ui32_size)) { 848 return -EINVAL; 849 } 850 break; 851 case AMDGPU_INFO_SENSOR_GPU_LOAD: 852 /* get GPU load */ 853 if (amdgpu_dpm_read_sensor(adev, 854 AMDGPU_PP_SENSOR_GPU_LOAD, 855 (void *)&ui32, &ui32_size)) { 856 return -EINVAL; 857 } 858 break; 859 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 860 /* get average GPU power */ 861 if (amdgpu_dpm_read_sensor(adev, 862 AMDGPU_PP_SENSOR_GPU_POWER, 863 (void *)&ui32, &ui32_size)) { 864 return -EINVAL; 865 } 866 ui32 >>= 8; 867 break; 868 case AMDGPU_INFO_SENSOR_VDDNB: 869 /* get VDDNB in millivolts */ 870 if (amdgpu_dpm_read_sensor(adev, 871 AMDGPU_PP_SENSOR_VDDNB, 872 (void *)&ui32, &ui32_size)) { 873 return -EINVAL; 874 } 875 break; 876 case AMDGPU_INFO_SENSOR_VDDGFX: 877 /* get VDDGFX in millivolts */ 878 if (amdgpu_dpm_read_sensor(adev, 879 AMDGPU_PP_SENSOR_VDDGFX, 880 (void *)&ui32, &ui32_size)) { 881 return -EINVAL; 882 } 883 break; 884 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 885 /* get stable pstate sclk in Mhz */ 886 if (amdgpu_dpm_read_sensor(adev, 887 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 888 (void *)&ui32, &ui32_size)) { 889 return -EINVAL; 890 } 891 ui32 /= 100; 892 break; 893 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 894 /* get stable pstate mclk in Mhz */ 895 if (amdgpu_dpm_read_sensor(adev, 896 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 897 (void *)&ui32, &ui32_size)) { 898 return -EINVAL; 899 } 900 ui32 /= 100; 901 break; 902 default: 903 DRM_DEBUG_KMS("Invalid request %d\n", 904 info->sensor_info.type); 905 return -EINVAL; 906 } 907 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 908 } 909 case AMDGPU_INFO_VRAM_LOST_COUNTER: 910 ui32 = atomic_read(&adev->vram_lost_counter); 911 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 912 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 913 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 914 uint64_t ras_mask; 915 916 if (!ras) 917 return -EINVAL; 918 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 919 920 return copy_to_user(out, &ras_mask, 921 min_t(u64, size, sizeof(ras_mask))) ? 922 -EFAULT : 0; 923 } 924 default: 925 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 926 return -EINVAL; 927 } 928 return 0; 929 } 930 931 932 /* 933 * Outdated mess for old drm with Xorg being in charge (void function now). 934 */ 935 /** 936 * amdgpu_driver_lastclose_kms - drm callback for last close 937 * 938 * @dev: drm dev pointer 939 * 940 * Switch vga_switcheroo state after last close (all asics). 941 */ 942 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 943 { 944 drm_fb_helper_lastclose(dev); 945 vga_switcheroo_process_delayed_switch(); 946 } 947 948 /** 949 * amdgpu_driver_open_kms - drm callback for open 950 * 951 * @dev: drm dev pointer 952 * @file_priv: drm file 953 * 954 * On device open, init vm on cayman+ (all asics). 955 * Returns 0 on success, error on failure. 956 */ 957 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 958 { 959 struct amdgpu_device *adev = dev->dev_private; 960 struct amdgpu_fpriv *fpriv; 961 int r, pasid; 962 963 /* Ensure IB tests are run on ring */ 964 flush_delayed_work(&adev->delayed_init_work); 965 966 967 if (amdgpu_ras_intr_triggered()) { 968 DRM_ERROR("RAS Intr triggered, device disabled!!"); 969 return -EHWPOISON; 970 } 971 972 file_priv->driver_priv = NULL; 973 974 r = pm_runtime_get_sync(dev->dev); 975 if (r < 0) 976 return r; 977 978 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 979 if (unlikely(!fpriv)) { 980 r = -ENOMEM; 981 goto out_suspend; 982 } 983 984 pasid = amdgpu_pasid_alloc(16); 985 if (pasid < 0) { 986 dev_warn(adev->dev, "No more PASIDs available!"); 987 pasid = 0; 988 } 989 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 990 if (r) 991 goto error_pasid; 992 993 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 994 if (!fpriv->prt_va) { 995 r = -ENOMEM; 996 goto error_vm; 997 } 998 999 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1000 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1001 1002 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1003 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1004 if (r) 1005 goto error_vm; 1006 } 1007 1008 mutex_init(&fpriv->bo_list_lock); 1009 idr_init(&fpriv->bo_list_handles); 1010 1011 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1012 1013 file_priv->driver_priv = fpriv; 1014 goto out_suspend; 1015 1016 error_vm: 1017 amdgpu_vm_fini(adev, &fpriv->vm); 1018 1019 error_pasid: 1020 if (pasid) 1021 amdgpu_pasid_free(pasid); 1022 1023 kfree(fpriv); 1024 1025 out_suspend: 1026 pm_runtime_mark_last_busy(dev->dev); 1027 pm_runtime_put_autosuspend(dev->dev); 1028 1029 return r; 1030 } 1031 1032 /** 1033 * amdgpu_driver_postclose_kms - drm callback for post close 1034 * 1035 * @dev: drm dev pointer 1036 * @file_priv: drm file 1037 * 1038 * On device post close, tear down vm on cayman+ (all asics). 1039 */ 1040 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1041 struct drm_file *file_priv) 1042 { 1043 struct amdgpu_device *adev = dev->dev_private; 1044 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1045 struct amdgpu_bo_list *list; 1046 struct amdgpu_bo *pd; 1047 unsigned int pasid; 1048 int handle; 1049 1050 if (!fpriv) 1051 return; 1052 1053 pm_runtime_get_sync(dev->dev); 1054 1055 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1056 amdgpu_uvd_free_handles(adev, file_priv); 1057 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1058 amdgpu_vce_free_handles(adev, file_priv); 1059 1060 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1061 1062 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1063 /* TODO: how to handle reserve failure */ 1064 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1065 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1066 fpriv->csa_va = NULL; 1067 amdgpu_bo_unreserve(adev->virt.csa_obj); 1068 } 1069 1070 pasid = fpriv->vm.pasid; 1071 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1072 1073 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1074 amdgpu_vm_fini(adev, &fpriv->vm); 1075 1076 if (pasid) 1077 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1078 amdgpu_bo_unref(&pd); 1079 1080 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1081 amdgpu_bo_list_put(list); 1082 1083 idr_destroy(&fpriv->bo_list_handles); 1084 mutex_destroy(&fpriv->bo_list_lock); 1085 1086 kfree(fpriv); 1087 file_priv->driver_priv = NULL; 1088 1089 pm_runtime_mark_last_busy(dev->dev); 1090 pm_runtime_put_autosuspend(dev->dev); 1091 } 1092 1093 /* 1094 * VBlank related functions. 1095 */ 1096 /** 1097 * amdgpu_get_vblank_counter_kms - get frame count 1098 * 1099 * @dev: drm dev pointer 1100 * @pipe: crtc to get the frame count from 1101 * 1102 * Gets the frame count on the requested crtc (all asics). 1103 * Returns frame count on success, -EINVAL on failure. 1104 */ 1105 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 1106 { 1107 struct amdgpu_device *adev = dev->dev_private; 1108 int vpos, hpos, stat; 1109 u32 count; 1110 1111 if (pipe >= adev->mode_info.num_crtc) { 1112 DRM_ERROR("Invalid crtc %u\n", pipe); 1113 return -EINVAL; 1114 } 1115 1116 /* The hw increments its frame counter at start of vsync, not at start 1117 * of vblank, as is required by DRM core vblank counter handling. 1118 * Cook the hw count here to make it appear to the caller as if it 1119 * incremented at start of vblank. We measure distance to start of 1120 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1121 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1122 * result by 1 to give the proper appearance to caller. 1123 */ 1124 if (adev->mode_info.crtcs[pipe]) { 1125 /* Repeat readout if needed to provide stable result if 1126 * we cross start of vsync during the queries. 1127 */ 1128 do { 1129 count = amdgpu_display_vblank_get_counter(adev, pipe); 1130 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1131 * vpos as distance to start of vblank, instead of 1132 * regular vertical scanout pos. 1133 */ 1134 stat = amdgpu_display_get_crtc_scanoutpos( 1135 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1136 &vpos, &hpos, NULL, NULL, 1137 &adev->mode_info.crtcs[pipe]->base.hwmode); 1138 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1139 1140 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1141 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1142 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1143 } else { 1144 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1145 pipe, vpos); 1146 1147 /* Bump counter if we are at >= leading edge of vblank, 1148 * but before vsync where vpos would turn negative and 1149 * the hw counter really increments. 1150 */ 1151 if (vpos >= 0) 1152 count++; 1153 } 1154 } else { 1155 /* Fallback to use value as is. */ 1156 count = amdgpu_display_vblank_get_counter(adev, pipe); 1157 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1158 } 1159 1160 return count; 1161 } 1162 1163 /** 1164 * amdgpu_enable_vblank_kms - enable vblank interrupt 1165 * 1166 * @dev: drm dev pointer 1167 * @pipe: crtc to enable vblank interrupt for 1168 * 1169 * Enable the interrupt on the requested crtc (all asics). 1170 * Returns 0 on success, -EINVAL on failure. 1171 */ 1172 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1173 { 1174 struct amdgpu_device *adev = dev->dev_private; 1175 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1176 1177 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1178 } 1179 1180 /** 1181 * amdgpu_disable_vblank_kms - disable vblank interrupt 1182 * 1183 * @dev: drm dev pointer 1184 * @pipe: crtc to disable vblank interrupt for 1185 * 1186 * Disable the interrupt on the requested crtc (all asics). 1187 */ 1188 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1189 { 1190 struct amdgpu_device *adev = dev->dev_private; 1191 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1192 1193 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1194 } 1195 1196 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1197 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1198 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1199 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1200 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1201 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1202 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1203 /* KMS */ 1204 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1205 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1206 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1207 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1208 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1209 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1210 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1211 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1212 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1213 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1214 }; 1215 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1216 1217 /* 1218 * Debugfs info 1219 */ 1220 #if defined(CONFIG_DEBUG_FS) 1221 1222 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1223 { 1224 struct drm_info_node *node = (struct drm_info_node *) m->private; 1225 struct drm_device *dev = node->minor->dev; 1226 struct amdgpu_device *adev = dev->dev_private; 1227 struct drm_amdgpu_info_firmware fw_info; 1228 struct drm_amdgpu_query_fw query_fw; 1229 struct atom_context *ctx = adev->mode_info.atom_context; 1230 int ret, i; 1231 1232 /* VCE */ 1233 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1234 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1235 if (ret) 1236 return ret; 1237 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1238 fw_info.feature, fw_info.ver); 1239 1240 /* UVD */ 1241 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1242 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1243 if (ret) 1244 return ret; 1245 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1246 fw_info.feature, fw_info.ver); 1247 1248 /* GMC */ 1249 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1250 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1251 if (ret) 1252 return ret; 1253 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1254 fw_info.feature, fw_info.ver); 1255 1256 /* ME */ 1257 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1258 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1259 if (ret) 1260 return ret; 1261 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1262 fw_info.feature, fw_info.ver); 1263 1264 /* PFP */ 1265 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1266 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1267 if (ret) 1268 return ret; 1269 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1270 fw_info.feature, fw_info.ver); 1271 1272 /* CE */ 1273 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1274 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1275 if (ret) 1276 return ret; 1277 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1278 fw_info.feature, fw_info.ver); 1279 1280 /* RLC */ 1281 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1282 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1283 if (ret) 1284 return ret; 1285 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1286 fw_info.feature, fw_info.ver); 1287 1288 /* RLC SAVE RESTORE LIST CNTL */ 1289 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1290 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1291 if (ret) 1292 return ret; 1293 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1294 fw_info.feature, fw_info.ver); 1295 1296 /* RLC SAVE RESTORE LIST GPM MEM */ 1297 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1298 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1299 if (ret) 1300 return ret; 1301 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1302 fw_info.feature, fw_info.ver); 1303 1304 /* RLC SAVE RESTORE LIST SRM MEM */ 1305 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1306 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1307 if (ret) 1308 return ret; 1309 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1310 fw_info.feature, fw_info.ver); 1311 1312 /* MEC */ 1313 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1314 query_fw.index = 0; 1315 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1316 if (ret) 1317 return ret; 1318 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1319 fw_info.feature, fw_info.ver); 1320 1321 /* MEC2 */ 1322 if (adev->asic_type == CHIP_KAVERI || 1323 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1324 query_fw.index = 1; 1325 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1326 if (ret) 1327 return ret; 1328 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1329 fw_info.feature, fw_info.ver); 1330 } 1331 1332 /* PSP SOS */ 1333 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1334 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1335 if (ret) 1336 return ret; 1337 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1338 fw_info.feature, fw_info.ver); 1339 1340 1341 /* PSP ASD */ 1342 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1343 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1344 if (ret) 1345 return ret; 1346 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1347 fw_info.feature, fw_info.ver); 1348 1349 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1350 for (i = 0; i < 2; i++) { 1351 query_fw.index = i; 1352 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1353 if (ret) 1354 continue; 1355 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1356 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1357 } 1358 1359 /* SMC */ 1360 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1361 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1362 if (ret) 1363 return ret; 1364 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1365 fw_info.feature, fw_info.ver); 1366 1367 /* SDMA */ 1368 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1369 for (i = 0; i < adev->sdma.num_instances; i++) { 1370 query_fw.index = i; 1371 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1372 if (ret) 1373 return ret; 1374 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1375 i, fw_info.feature, fw_info.ver); 1376 } 1377 1378 /* VCN */ 1379 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1380 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1381 if (ret) 1382 return ret; 1383 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1384 fw_info.feature, fw_info.ver); 1385 1386 /* DMCU */ 1387 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1388 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1389 if (ret) 1390 return ret; 1391 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1392 fw_info.feature, fw_info.ver); 1393 1394 1395 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1396 1397 return 0; 1398 } 1399 1400 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1401 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1402 }; 1403 #endif 1404 1405 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1406 { 1407 #if defined(CONFIG_DEBUG_FS) 1408 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1409 ARRAY_SIZE(amdgpu_firmware_info_list)); 1410 #else 1411 return 0; 1412 #endif 1413 } 1414