1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (adev->runpm) { 91 pm_runtime_get_sync(dev->dev); 92 pm_runtime_forbid(dev->dev); 93 } 94 95 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 96 DRM_WARN("smart shift update failed\n"); 97 98 amdgpu_acpi_fini(adev); 99 amdgpu_device_fini_hw(adev); 100 } 101 102 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 103 { 104 struct amdgpu_gpu_instance *gpu_instance; 105 106 mutex_lock(&mgpu_info.mutex); 107 108 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 109 DRM_ERROR("Cannot register more gpu instance\n"); 110 mutex_unlock(&mgpu_info.mutex); 111 return; 112 } 113 114 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 115 gpu_instance->adev = adev; 116 gpu_instance->mgpu_fan_enabled = 0; 117 118 mgpu_info.num_gpu++; 119 if (adev->flags & AMD_IS_APU) 120 mgpu_info.num_apu++; 121 else 122 mgpu_info.num_dgpu++; 123 124 mutex_unlock(&mgpu_info.mutex); 125 } 126 127 static void amdgpu_get_audio_func(struct amdgpu_device *adev) 128 { 129 struct pci_dev *p = NULL; 130 131 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 132 adev->pdev->bus->number, 1); 133 if (p) { 134 pm_runtime_get_sync(&p->dev); 135 136 pm_runtime_mark_last_busy(&p->dev); 137 pm_runtime_put_autosuspend(&p->dev); 138 139 pci_dev_put(p); 140 } 141 } 142 143 /** 144 * amdgpu_driver_load_kms - Main load function for KMS. 145 * 146 * @adev: pointer to struct amdgpu_device 147 * @flags: device flags 148 * 149 * This is the main load function for KMS (all asics). 150 * Returns 0 on success, error on failure. 151 */ 152 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 153 { 154 struct drm_device *dev; 155 struct pci_dev *parent; 156 int r, acpi_status; 157 158 dev = adev_to_drm(adev); 159 160 if (amdgpu_has_atpx() && 161 (amdgpu_is_atpx_hybrid() || 162 amdgpu_has_atpx_dgpu_power_cntl()) && 163 ((flags & AMD_IS_APU) == 0) && 164 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) 165 flags |= AMD_IS_PX; 166 167 parent = pci_upstream_bridge(adev->pdev); 168 adev->has_pr3 = parent ? pci_pr3_present(parent) : false; 169 170 /* amdgpu_device_init should report only fatal error 171 * like memory allocation failure or iomapping failure, 172 * or memory manager initialization failure, it must 173 * properly initialize the GPU MC controller and permit 174 * VRAM allocation 175 */ 176 r = amdgpu_device_init(adev, flags); 177 if (r) { 178 dev_err(dev->dev, "Fatal error during GPU init\n"); 179 goto out; 180 } 181 182 if (amdgpu_device_supports_px(dev) && 183 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 184 adev->runpm = true; 185 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 186 } else if (amdgpu_device_supports_boco(dev) && 187 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 188 adev->runpm = true; 189 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 190 } else if (amdgpu_device_supports_baco(dev) && 191 (amdgpu_runtime_pm != 0)) { 192 switch (adev->asic_type) { 193 case CHIP_VEGA20: 194 case CHIP_ARCTURUS: 195 /* enable runpm if runpm=1 */ 196 if (amdgpu_runtime_pm > 0) 197 adev->runpm = true; 198 break; 199 case CHIP_VEGA10: 200 /* turn runpm on if noretry=0 */ 201 if (!adev->gmc.noretry) 202 adev->runpm = true; 203 break; 204 default: 205 /* enable runpm on CI+ */ 206 adev->runpm = true; 207 break; 208 } 209 if (adev->runpm) 210 dev_info(adev->dev, "Using BACO for runtime pm\n"); 211 } 212 213 /* Call ACPI methods: require modeset init 214 * but failure is not fatal 215 */ 216 217 acpi_status = amdgpu_acpi_init(adev); 218 if (acpi_status) 219 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 220 221 if (adev->runpm) { 222 /* only need to skip on ATPX */ 223 if (amdgpu_device_supports_px(dev)) 224 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 225 /* we want direct complete for BOCO */ 226 if (amdgpu_device_supports_boco(dev)) 227 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE | 228 DPM_FLAG_SMART_SUSPEND | 229 DPM_FLAG_MAY_SKIP_RESUME); 230 pm_runtime_use_autosuspend(dev->dev); 231 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 232 233 pm_runtime_allow(dev->dev); 234 235 pm_runtime_mark_last_busy(dev->dev); 236 pm_runtime_put_autosuspend(dev->dev); 237 238 /* 239 * For runpm implemented via BACO, PMFW will handle the 240 * timing for BACO in and out: 241 * - put ASIC into BACO state only when both video and 242 * audio functions are in D3 state. 243 * - pull ASIC out of BACO state when either video or 244 * audio function is in D0 state. 245 * Also, at startup, PMFW assumes both functions are in 246 * D0 state. 247 * 248 * So if snd driver was loaded prior to amdgpu driver 249 * and audio function was put into D3 state, there will 250 * be no PMFW-aware D-state transition(D0->D3) on runpm 251 * suspend. Thus the BACO will be not correctly kicked in. 252 * 253 * Via amdgpu_get_audio_func(), the audio dev is put 254 * into D0 state. Then there will be a PMFW-aware D-state 255 * transition(D0->D3) on runpm suspend. 256 */ 257 if (amdgpu_device_supports_baco(dev) && 258 !(adev->flags & AMD_IS_APU) && 259 (adev->asic_type >= CHIP_NAVI10)) 260 amdgpu_get_audio_func(adev); 261 } 262 263 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 264 DRM_WARN("smart shift update failed\n"); 265 266 out: 267 if (r) { 268 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 269 if (adev->rmmio && adev->runpm) 270 pm_runtime_put_noidle(dev->dev); 271 amdgpu_driver_unload_kms(dev); 272 } 273 274 return r; 275 } 276 277 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 278 struct drm_amdgpu_query_fw *query_fw, 279 struct amdgpu_device *adev) 280 { 281 switch (query_fw->fw_type) { 282 case AMDGPU_INFO_FW_VCE: 283 fw_info->ver = adev->vce.fw_version; 284 fw_info->feature = adev->vce.fb_version; 285 break; 286 case AMDGPU_INFO_FW_UVD: 287 fw_info->ver = adev->uvd.fw_version; 288 fw_info->feature = 0; 289 break; 290 case AMDGPU_INFO_FW_VCN: 291 fw_info->ver = adev->vcn.fw_version; 292 fw_info->feature = 0; 293 break; 294 case AMDGPU_INFO_FW_GMC: 295 fw_info->ver = adev->gmc.fw_version; 296 fw_info->feature = 0; 297 break; 298 case AMDGPU_INFO_FW_GFX_ME: 299 fw_info->ver = adev->gfx.me_fw_version; 300 fw_info->feature = adev->gfx.me_feature_version; 301 break; 302 case AMDGPU_INFO_FW_GFX_PFP: 303 fw_info->ver = adev->gfx.pfp_fw_version; 304 fw_info->feature = adev->gfx.pfp_feature_version; 305 break; 306 case AMDGPU_INFO_FW_GFX_CE: 307 fw_info->ver = adev->gfx.ce_fw_version; 308 fw_info->feature = adev->gfx.ce_feature_version; 309 break; 310 case AMDGPU_INFO_FW_GFX_RLC: 311 fw_info->ver = adev->gfx.rlc_fw_version; 312 fw_info->feature = adev->gfx.rlc_feature_version; 313 break; 314 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 315 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 316 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 317 break; 318 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 319 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 320 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 321 break; 322 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 323 fw_info->ver = adev->gfx.rlc_srls_fw_version; 324 fw_info->feature = adev->gfx.rlc_srls_feature_version; 325 break; 326 case AMDGPU_INFO_FW_GFX_MEC: 327 if (query_fw->index == 0) { 328 fw_info->ver = adev->gfx.mec_fw_version; 329 fw_info->feature = adev->gfx.mec_feature_version; 330 } else if (query_fw->index == 1) { 331 fw_info->ver = adev->gfx.mec2_fw_version; 332 fw_info->feature = adev->gfx.mec2_feature_version; 333 } else 334 return -EINVAL; 335 break; 336 case AMDGPU_INFO_FW_SMC: 337 fw_info->ver = adev->pm.fw_version; 338 fw_info->feature = 0; 339 break; 340 case AMDGPU_INFO_FW_TA: 341 switch (query_fw->index) { 342 case TA_FW_TYPE_PSP_XGMI: 343 fw_info->ver = adev->psp.ta_fw_version; 344 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 345 break; 346 case TA_FW_TYPE_PSP_RAS: 347 fw_info->ver = adev->psp.ta_fw_version; 348 fw_info->feature = adev->psp.ta_ras_ucode_version; 349 break; 350 case TA_FW_TYPE_PSP_HDCP: 351 fw_info->ver = adev->psp.ta_fw_version; 352 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 353 break; 354 case TA_FW_TYPE_PSP_DTM: 355 fw_info->ver = adev->psp.ta_fw_version; 356 fw_info->feature = adev->psp.ta_dtm_ucode_version; 357 break; 358 case TA_FW_TYPE_PSP_RAP: 359 fw_info->ver = adev->psp.ta_fw_version; 360 fw_info->feature = adev->psp.ta_rap_ucode_version; 361 break; 362 case TA_FW_TYPE_PSP_SECUREDISPLAY: 363 fw_info->ver = adev->psp.ta_fw_version; 364 fw_info->feature = adev->psp.ta_securedisplay_ucode_version; 365 break; 366 default: 367 return -EINVAL; 368 } 369 break; 370 case AMDGPU_INFO_FW_SDMA: 371 if (query_fw->index >= adev->sdma.num_instances) 372 return -EINVAL; 373 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 374 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 375 break; 376 case AMDGPU_INFO_FW_SOS: 377 fw_info->ver = adev->psp.sos_fw_version; 378 fw_info->feature = adev->psp.sos_feature_version; 379 break; 380 case AMDGPU_INFO_FW_ASD: 381 fw_info->ver = adev->psp.asd_fw_version; 382 fw_info->feature = adev->psp.asd_feature_version; 383 break; 384 case AMDGPU_INFO_FW_DMCU: 385 fw_info->ver = adev->dm.dmcu_fw_version; 386 fw_info->feature = 0; 387 break; 388 case AMDGPU_INFO_FW_DMCUB: 389 fw_info->ver = adev->dm.dmcub_fw_version; 390 fw_info->feature = 0; 391 break; 392 case AMDGPU_INFO_FW_TOC: 393 fw_info->ver = adev->psp.toc_fw_version; 394 fw_info->feature = adev->psp.toc_feature_version; 395 break; 396 default: 397 return -EINVAL; 398 } 399 return 0; 400 } 401 402 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 403 struct drm_amdgpu_info *info, 404 struct drm_amdgpu_info_hw_ip *result) 405 { 406 uint32_t ib_start_alignment = 0; 407 uint32_t ib_size_alignment = 0; 408 enum amd_ip_block_type type; 409 unsigned int num_rings = 0; 410 unsigned int i, j; 411 412 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 413 return -EINVAL; 414 415 switch (info->query_hw_ip.type) { 416 case AMDGPU_HW_IP_GFX: 417 type = AMD_IP_BLOCK_TYPE_GFX; 418 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 419 if (adev->gfx.gfx_ring[i].sched.ready) 420 ++num_rings; 421 ib_start_alignment = 32; 422 ib_size_alignment = 32; 423 break; 424 case AMDGPU_HW_IP_COMPUTE: 425 type = AMD_IP_BLOCK_TYPE_GFX; 426 for (i = 0; i < adev->gfx.num_compute_rings; i++) 427 if (adev->gfx.compute_ring[i].sched.ready) 428 ++num_rings; 429 ib_start_alignment = 32; 430 ib_size_alignment = 32; 431 break; 432 case AMDGPU_HW_IP_DMA: 433 type = AMD_IP_BLOCK_TYPE_SDMA; 434 for (i = 0; i < adev->sdma.num_instances; i++) 435 if (adev->sdma.instance[i].ring.sched.ready) 436 ++num_rings; 437 ib_start_alignment = 256; 438 ib_size_alignment = 4; 439 break; 440 case AMDGPU_HW_IP_UVD: 441 type = AMD_IP_BLOCK_TYPE_UVD; 442 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 443 if (adev->uvd.harvest_config & (1 << i)) 444 continue; 445 446 if (adev->uvd.inst[i].ring.sched.ready) 447 ++num_rings; 448 } 449 ib_start_alignment = 64; 450 ib_size_alignment = 64; 451 break; 452 case AMDGPU_HW_IP_VCE: 453 type = AMD_IP_BLOCK_TYPE_VCE; 454 for (i = 0; i < adev->vce.num_rings; i++) 455 if (adev->vce.ring[i].sched.ready) 456 ++num_rings; 457 ib_start_alignment = 4; 458 ib_size_alignment = 1; 459 break; 460 case AMDGPU_HW_IP_UVD_ENC: 461 type = AMD_IP_BLOCK_TYPE_UVD; 462 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 463 if (adev->uvd.harvest_config & (1 << i)) 464 continue; 465 466 for (j = 0; j < adev->uvd.num_enc_rings; j++) 467 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 468 ++num_rings; 469 } 470 ib_start_alignment = 64; 471 ib_size_alignment = 64; 472 break; 473 case AMDGPU_HW_IP_VCN_DEC: 474 type = AMD_IP_BLOCK_TYPE_VCN; 475 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 476 if (adev->uvd.harvest_config & (1 << i)) 477 continue; 478 479 if (adev->vcn.inst[i].ring_dec.sched.ready) 480 ++num_rings; 481 } 482 ib_start_alignment = 16; 483 ib_size_alignment = 16; 484 break; 485 case AMDGPU_HW_IP_VCN_ENC: 486 type = AMD_IP_BLOCK_TYPE_VCN; 487 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 488 if (adev->uvd.harvest_config & (1 << i)) 489 continue; 490 491 for (j = 0; j < adev->vcn.num_enc_rings; j++) 492 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 493 ++num_rings; 494 } 495 ib_start_alignment = 64; 496 ib_size_alignment = 1; 497 break; 498 case AMDGPU_HW_IP_VCN_JPEG: 499 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 500 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 501 502 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 503 if (adev->jpeg.harvest_config & (1 << i)) 504 continue; 505 506 if (adev->jpeg.inst[i].ring_dec.sched.ready) 507 ++num_rings; 508 } 509 ib_start_alignment = 16; 510 ib_size_alignment = 16; 511 break; 512 default: 513 return -EINVAL; 514 } 515 516 for (i = 0; i < adev->num_ip_blocks; i++) 517 if (adev->ip_blocks[i].version->type == type && 518 adev->ip_blocks[i].status.valid) 519 break; 520 521 if (i == adev->num_ip_blocks) 522 return 0; 523 524 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 525 num_rings); 526 527 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 528 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 529 result->capabilities_flags = 0; 530 result->available_rings = (1 << num_rings) - 1; 531 result->ib_start_alignment = ib_start_alignment; 532 result->ib_size_alignment = ib_size_alignment; 533 return 0; 534 } 535 536 /* 537 * Userspace get information ioctl 538 */ 539 /** 540 * amdgpu_info_ioctl - answer a device specific request. 541 * 542 * @dev: drm device pointer 543 * @data: request object 544 * @filp: drm filp 545 * 546 * This function is used to pass device specific parameters to the userspace 547 * drivers. Examples include: pci device id, pipeline parms, tiling params, 548 * etc. (all asics). 549 * Returns 0 on success, -EINVAL on failure. 550 */ 551 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 552 { 553 struct amdgpu_device *adev = drm_to_adev(dev); 554 struct drm_amdgpu_info *info = data; 555 struct amdgpu_mode_info *minfo = &adev->mode_info; 556 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 557 uint32_t size = info->return_size; 558 struct drm_crtc *crtc; 559 uint32_t ui32 = 0; 560 uint64_t ui64 = 0; 561 int i, found; 562 int ui32_size = sizeof(ui32); 563 564 if (!info->return_size || !info->return_pointer) 565 return -EINVAL; 566 567 switch (info->query) { 568 case AMDGPU_INFO_ACCEL_WORKING: 569 ui32 = adev->accel_working; 570 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 571 case AMDGPU_INFO_CRTC_FROM_ID: 572 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 573 crtc = (struct drm_crtc *)minfo->crtcs[i]; 574 if (crtc && crtc->base.id == info->mode_crtc.id) { 575 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 576 ui32 = amdgpu_crtc->crtc_id; 577 found = 1; 578 break; 579 } 580 } 581 if (!found) { 582 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 583 return -EINVAL; 584 } 585 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 586 case AMDGPU_INFO_HW_IP_INFO: { 587 struct drm_amdgpu_info_hw_ip ip = {}; 588 int ret; 589 590 ret = amdgpu_hw_ip_info(adev, info, &ip); 591 if (ret) 592 return ret; 593 594 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 595 return ret ? -EFAULT : 0; 596 } 597 case AMDGPU_INFO_HW_IP_COUNT: { 598 enum amd_ip_block_type type; 599 uint32_t count = 0; 600 601 switch (info->query_hw_ip.type) { 602 case AMDGPU_HW_IP_GFX: 603 type = AMD_IP_BLOCK_TYPE_GFX; 604 break; 605 case AMDGPU_HW_IP_COMPUTE: 606 type = AMD_IP_BLOCK_TYPE_GFX; 607 break; 608 case AMDGPU_HW_IP_DMA: 609 type = AMD_IP_BLOCK_TYPE_SDMA; 610 break; 611 case AMDGPU_HW_IP_UVD: 612 type = AMD_IP_BLOCK_TYPE_UVD; 613 break; 614 case AMDGPU_HW_IP_VCE: 615 type = AMD_IP_BLOCK_TYPE_VCE; 616 break; 617 case AMDGPU_HW_IP_UVD_ENC: 618 type = AMD_IP_BLOCK_TYPE_UVD; 619 break; 620 case AMDGPU_HW_IP_VCN_DEC: 621 case AMDGPU_HW_IP_VCN_ENC: 622 type = AMD_IP_BLOCK_TYPE_VCN; 623 break; 624 case AMDGPU_HW_IP_VCN_JPEG: 625 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 626 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 627 break; 628 default: 629 return -EINVAL; 630 } 631 632 for (i = 0; i < adev->num_ip_blocks; i++) 633 if (adev->ip_blocks[i].version->type == type && 634 adev->ip_blocks[i].status.valid && 635 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 636 count++; 637 638 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 639 } 640 case AMDGPU_INFO_TIMESTAMP: 641 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 643 case AMDGPU_INFO_FW_VERSION: { 644 struct drm_amdgpu_info_firmware fw_info; 645 int ret; 646 647 /* We only support one instance of each IP block right now. */ 648 if (info->query_fw.ip_instance != 0) 649 return -EINVAL; 650 651 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 652 if (ret) 653 return ret; 654 655 return copy_to_user(out, &fw_info, 656 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 657 } 658 case AMDGPU_INFO_NUM_BYTES_MOVED: 659 ui64 = atomic64_read(&adev->num_bytes_moved); 660 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 661 case AMDGPU_INFO_NUM_EVICTIONS: 662 ui64 = atomic64_read(&adev->num_evictions); 663 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 664 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 665 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 666 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 667 case AMDGPU_INFO_VRAM_USAGE: 668 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 669 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 670 case AMDGPU_INFO_VIS_VRAM_USAGE: 671 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 672 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 673 case AMDGPU_INFO_GTT_USAGE: 674 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 675 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 676 case AMDGPU_INFO_GDS_CONFIG: { 677 struct drm_amdgpu_info_gds gds_info; 678 679 memset(&gds_info, 0, sizeof(gds_info)); 680 gds_info.compute_partition_size = adev->gds.gds_size; 681 gds_info.gds_total_size = adev->gds.gds_size; 682 gds_info.gws_per_compute_partition = adev->gds.gws_size; 683 gds_info.oa_per_compute_partition = adev->gds.oa_size; 684 return copy_to_user(out, &gds_info, 685 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 686 } 687 case AMDGPU_INFO_VRAM_GTT: { 688 struct drm_amdgpu_info_vram_gtt vram_gtt; 689 690 vram_gtt.vram_size = adev->gmc.real_vram_size - 691 atomic64_read(&adev->vram_pin_size) - 692 AMDGPU_VM_RESERVED_VRAM; 693 vram_gtt.vram_cpu_accessible_size = 694 min(adev->gmc.visible_vram_size - 695 atomic64_read(&adev->visible_pin_size), 696 vram_gtt.vram_size); 697 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 698 vram_gtt.gtt_size *= PAGE_SIZE; 699 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 700 return copy_to_user(out, &vram_gtt, 701 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 702 } 703 case AMDGPU_INFO_MEMORY: { 704 struct drm_amdgpu_memory_info mem; 705 struct ttm_resource_manager *vram_man = 706 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 707 struct ttm_resource_manager *gtt_man = 708 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 709 memset(&mem, 0, sizeof(mem)); 710 mem.vram.total_heap_size = adev->gmc.real_vram_size; 711 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 712 atomic64_read(&adev->vram_pin_size) - 713 AMDGPU_VM_RESERVED_VRAM; 714 mem.vram.heap_usage = 715 amdgpu_vram_mgr_usage(vram_man); 716 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 717 718 mem.cpu_accessible_vram.total_heap_size = 719 adev->gmc.visible_vram_size; 720 mem.cpu_accessible_vram.usable_heap_size = 721 min(adev->gmc.visible_vram_size - 722 atomic64_read(&adev->visible_pin_size), 723 mem.vram.usable_heap_size); 724 mem.cpu_accessible_vram.heap_usage = 725 amdgpu_vram_mgr_vis_usage(vram_man); 726 mem.cpu_accessible_vram.max_allocation = 727 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 728 729 mem.gtt.total_heap_size = gtt_man->size; 730 mem.gtt.total_heap_size *= PAGE_SIZE; 731 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 732 atomic64_read(&adev->gart_pin_size); 733 mem.gtt.heap_usage = 734 amdgpu_gtt_mgr_usage(gtt_man); 735 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 736 737 return copy_to_user(out, &mem, 738 min((size_t)size, sizeof(mem))) 739 ? -EFAULT : 0; 740 } 741 case AMDGPU_INFO_READ_MMR_REG: { 742 unsigned n, alloc_size; 743 uint32_t *regs; 744 unsigned se_num = (info->read_mmr_reg.instance >> 745 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 746 AMDGPU_INFO_MMR_SE_INDEX_MASK; 747 unsigned sh_num = (info->read_mmr_reg.instance >> 748 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 749 AMDGPU_INFO_MMR_SH_INDEX_MASK; 750 751 /* set full masks if the userspace set all bits 752 * in the bitfields */ 753 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 754 se_num = 0xffffffff; 755 else if (se_num >= AMDGPU_GFX_MAX_SE) 756 return -EINVAL; 757 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 758 sh_num = 0xffffffff; 759 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 760 return -EINVAL; 761 762 if (info->read_mmr_reg.count > 128) 763 return -EINVAL; 764 765 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 766 if (!regs) 767 return -ENOMEM; 768 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 769 770 amdgpu_gfx_off_ctrl(adev, false); 771 for (i = 0; i < info->read_mmr_reg.count; i++) { 772 if (amdgpu_asic_read_register(adev, se_num, sh_num, 773 info->read_mmr_reg.dword_offset + i, 774 ®s[i])) { 775 DRM_DEBUG_KMS("unallowed offset %#x\n", 776 info->read_mmr_reg.dword_offset + i); 777 kfree(regs); 778 amdgpu_gfx_off_ctrl(adev, true); 779 return -EFAULT; 780 } 781 } 782 amdgpu_gfx_off_ctrl(adev, true); 783 n = copy_to_user(out, regs, min(size, alloc_size)); 784 kfree(regs); 785 return n ? -EFAULT : 0; 786 } 787 case AMDGPU_INFO_DEV_INFO: { 788 struct drm_amdgpu_info_device *dev_info; 789 uint64_t vm_size; 790 int ret; 791 792 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 793 if (!dev_info) 794 return -ENOMEM; 795 796 dev_info->device_id = adev->pdev->device; 797 dev_info->chip_rev = adev->rev_id; 798 dev_info->external_rev = adev->external_rev_id; 799 dev_info->pci_rev = adev->pdev->revision; 800 dev_info->family = adev->family; 801 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 802 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 803 /* return all clocks in KHz */ 804 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 805 if (adev->pm.dpm_enabled) { 806 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 807 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 808 } else { 809 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 810 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 811 } 812 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 813 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 814 adev->gfx.config.max_shader_engines; 815 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 816 dev_info->_pad = 0; 817 dev_info->ids_flags = 0; 818 if (adev->flags & AMD_IS_APU) 819 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 820 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 821 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 822 if (amdgpu_is_tmz(adev)) 823 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 824 825 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 826 vm_size -= AMDGPU_VA_RESERVED_SIZE; 827 828 /* Older VCE FW versions are buggy and can handle only 40bits */ 829 if (adev->vce.fw_version && 830 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 831 vm_size = min(vm_size, 1ULL << 40); 832 833 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 834 dev_info->virtual_address_max = 835 min(vm_size, AMDGPU_GMC_HOLE_START); 836 837 if (vm_size > AMDGPU_GMC_HOLE_START) { 838 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 839 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 840 } 841 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 842 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 843 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 844 dev_info->cu_active_number = adev->gfx.cu_info.number; 845 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 846 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 847 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 848 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 849 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 850 sizeof(adev->gfx.cu_info.bitmap)); 851 dev_info->vram_type = adev->gmc.vram_type; 852 dev_info->vram_bit_width = adev->gmc.vram_width; 853 dev_info->vce_harvest_config = adev->vce.harvest_config; 854 dev_info->gc_double_offchip_lds_buf = 855 adev->gfx.config.double_offchip_lds_buf; 856 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 857 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 858 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 859 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 860 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 861 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 862 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 863 864 if (adev->family >= AMDGPU_FAMILY_NV) 865 dev_info->pa_sc_tile_steering_override = 866 adev->gfx.config.pa_sc_tile_steering_override; 867 868 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 869 870 ret = copy_to_user(out, dev_info, 871 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 872 kfree(dev_info); 873 return ret; 874 } 875 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 876 unsigned i; 877 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 878 struct amd_vce_state *vce_state; 879 880 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 881 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 882 if (vce_state) { 883 vce_clk_table.entries[i].sclk = vce_state->sclk; 884 vce_clk_table.entries[i].mclk = vce_state->mclk; 885 vce_clk_table.entries[i].eclk = vce_state->evclk; 886 vce_clk_table.num_valid_entries++; 887 } 888 } 889 890 return copy_to_user(out, &vce_clk_table, 891 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 892 } 893 case AMDGPU_INFO_VBIOS: { 894 uint32_t bios_size = adev->bios_size; 895 896 switch (info->vbios_info.type) { 897 case AMDGPU_INFO_VBIOS_SIZE: 898 return copy_to_user(out, &bios_size, 899 min((size_t)size, sizeof(bios_size))) 900 ? -EFAULT : 0; 901 case AMDGPU_INFO_VBIOS_IMAGE: { 902 uint8_t *bios; 903 uint32_t bios_offset = info->vbios_info.offset; 904 905 if (bios_offset >= bios_size) 906 return -EINVAL; 907 908 bios = adev->bios + bios_offset; 909 return copy_to_user(out, bios, 910 min((size_t)size, (size_t)(bios_size - bios_offset))) 911 ? -EFAULT : 0; 912 } 913 case AMDGPU_INFO_VBIOS_INFO: { 914 struct drm_amdgpu_info_vbios vbios_info = {}; 915 struct atom_context *atom_context; 916 917 atom_context = adev->mode_info.atom_context; 918 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 919 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 920 vbios_info.version = atom_context->version; 921 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 922 sizeof(atom_context->vbios_ver_str)); 923 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 924 925 return copy_to_user(out, &vbios_info, 926 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 927 } 928 default: 929 DRM_DEBUG_KMS("Invalid request %d\n", 930 info->vbios_info.type); 931 return -EINVAL; 932 } 933 } 934 case AMDGPU_INFO_NUM_HANDLES: { 935 struct drm_amdgpu_info_num_handles handle; 936 937 switch (info->query_hw_ip.type) { 938 case AMDGPU_HW_IP_UVD: 939 /* Starting Polaris, we support unlimited UVD handles */ 940 if (adev->asic_type < CHIP_POLARIS10) { 941 handle.uvd_max_handles = adev->uvd.max_handles; 942 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 943 944 return copy_to_user(out, &handle, 945 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 946 } else { 947 return -ENODATA; 948 } 949 950 break; 951 default: 952 return -EINVAL; 953 } 954 } 955 case AMDGPU_INFO_SENSOR: { 956 if (!adev->pm.dpm_enabled) 957 return -ENOENT; 958 959 switch (info->sensor_info.type) { 960 case AMDGPU_INFO_SENSOR_GFX_SCLK: 961 /* get sclk in Mhz */ 962 if (amdgpu_dpm_read_sensor(adev, 963 AMDGPU_PP_SENSOR_GFX_SCLK, 964 (void *)&ui32, &ui32_size)) { 965 return -EINVAL; 966 } 967 ui32 /= 100; 968 break; 969 case AMDGPU_INFO_SENSOR_GFX_MCLK: 970 /* get mclk in Mhz */ 971 if (amdgpu_dpm_read_sensor(adev, 972 AMDGPU_PP_SENSOR_GFX_MCLK, 973 (void *)&ui32, &ui32_size)) { 974 return -EINVAL; 975 } 976 ui32 /= 100; 977 break; 978 case AMDGPU_INFO_SENSOR_GPU_TEMP: 979 /* get temperature in millidegrees C */ 980 if (amdgpu_dpm_read_sensor(adev, 981 AMDGPU_PP_SENSOR_GPU_TEMP, 982 (void *)&ui32, &ui32_size)) { 983 return -EINVAL; 984 } 985 break; 986 case AMDGPU_INFO_SENSOR_GPU_LOAD: 987 /* get GPU load */ 988 if (amdgpu_dpm_read_sensor(adev, 989 AMDGPU_PP_SENSOR_GPU_LOAD, 990 (void *)&ui32, &ui32_size)) { 991 return -EINVAL; 992 } 993 break; 994 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 995 /* get average GPU power */ 996 if (amdgpu_dpm_read_sensor(adev, 997 AMDGPU_PP_SENSOR_GPU_POWER, 998 (void *)&ui32, &ui32_size)) { 999 return -EINVAL; 1000 } 1001 ui32 >>= 8; 1002 break; 1003 case AMDGPU_INFO_SENSOR_VDDNB: 1004 /* get VDDNB in millivolts */ 1005 if (amdgpu_dpm_read_sensor(adev, 1006 AMDGPU_PP_SENSOR_VDDNB, 1007 (void *)&ui32, &ui32_size)) { 1008 return -EINVAL; 1009 } 1010 break; 1011 case AMDGPU_INFO_SENSOR_VDDGFX: 1012 /* get VDDGFX in millivolts */ 1013 if (amdgpu_dpm_read_sensor(adev, 1014 AMDGPU_PP_SENSOR_VDDGFX, 1015 (void *)&ui32, &ui32_size)) { 1016 return -EINVAL; 1017 } 1018 break; 1019 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1020 /* get stable pstate sclk in Mhz */ 1021 if (amdgpu_dpm_read_sensor(adev, 1022 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1023 (void *)&ui32, &ui32_size)) { 1024 return -EINVAL; 1025 } 1026 ui32 /= 100; 1027 break; 1028 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1029 /* get stable pstate mclk in Mhz */ 1030 if (amdgpu_dpm_read_sensor(adev, 1031 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1032 (void *)&ui32, &ui32_size)) { 1033 return -EINVAL; 1034 } 1035 ui32 /= 100; 1036 break; 1037 default: 1038 DRM_DEBUG_KMS("Invalid request %d\n", 1039 info->sensor_info.type); 1040 return -EINVAL; 1041 } 1042 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1043 } 1044 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1045 ui32 = atomic_read(&adev->vram_lost_counter); 1046 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1047 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1048 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1049 uint64_t ras_mask; 1050 1051 if (!ras) 1052 return -EINVAL; 1053 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1054 1055 return copy_to_user(out, &ras_mask, 1056 min_t(u64, size, sizeof(ras_mask))) ? 1057 -EFAULT : 0; 1058 } 1059 case AMDGPU_INFO_VIDEO_CAPS: { 1060 const struct amdgpu_video_codecs *codecs; 1061 struct drm_amdgpu_info_video_caps *caps; 1062 int r; 1063 1064 switch (info->video_cap.type) { 1065 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1066 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1067 if (r) 1068 return -EINVAL; 1069 break; 1070 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1071 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1072 if (r) 1073 return -EINVAL; 1074 break; 1075 default: 1076 DRM_DEBUG_KMS("Invalid request %d\n", 1077 info->video_cap.type); 1078 return -EINVAL; 1079 } 1080 1081 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1082 if (!caps) 1083 return -ENOMEM; 1084 1085 for (i = 0; i < codecs->codec_count; i++) { 1086 int idx = codecs->codec_array[i].codec_type; 1087 1088 switch (idx) { 1089 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1090 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1091 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1092 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1093 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1094 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1095 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1096 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1097 caps->codec_info[idx].valid = 1; 1098 caps->codec_info[idx].max_width = 1099 codecs->codec_array[i].max_width; 1100 caps->codec_info[idx].max_height = 1101 codecs->codec_array[i].max_height; 1102 caps->codec_info[idx].max_pixels_per_frame = 1103 codecs->codec_array[i].max_pixels_per_frame; 1104 caps->codec_info[idx].max_level = 1105 codecs->codec_array[i].max_level; 1106 break; 1107 default: 1108 break; 1109 } 1110 } 1111 r = copy_to_user(out, caps, 1112 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1113 kfree(caps); 1114 return r; 1115 } 1116 default: 1117 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1118 return -EINVAL; 1119 } 1120 return 0; 1121 } 1122 1123 1124 /* 1125 * Outdated mess for old drm with Xorg being in charge (void function now). 1126 */ 1127 /** 1128 * amdgpu_driver_lastclose_kms - drm callback for last close 1129 * 1130 * @dev: drm dev pointer 1131 * 1132 * Switch vga_switcheroo state after last close (all asics). 1133 */ 1134 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1135 { 1136 drm_fb_helper_lastclose(dev); 1137 vga_switcheroo_process_delayed_switch(); 1138 } 1139 1140 /** 1141 * amdgpu_driver_open_kms - drm callback for open 1142 * 1143 * @dev: drm dev pointer 1144 * @file_priv: drm file 1145 * 1146 * On device open, init vm on cayman+ (all asics). 1147 * Returns 0 on success, error on failure. 1148 */ 1149 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1150 { 1151 struct amdgpu_device *adev = drm_to_adev(dev); 1152 struct amdgpu_fpriv *fpriv; 1153 int r, pasid; 1154 1155 /* Ensure IB tests are run on ring */ 1156 flush_delayed_work(&adev->delayed_init_work); 1157 1158 1159 if (amdgpu_ras_intr_triggered()) { 1160 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1161 return -EHWPOISON; 1162 } 1163 1164 file_priv->driver_priv = NULL; 1165 1166 r = pm_runtime_get_sync(dev->dev); 1167 if (r < 0) 1168 goto pm_put; 1169 1170 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1171 if (unlikely(!fpriv)) { 1172 r = -ENOMEM; 1173 goto out_suspend; 1174 } 1175 1176 pasid = amdgpu_pasid_alloc(16); 1177 if (pasid < 0) { 1178 dev_warn(adev->dev, "No more PASIDs available!"); 1179 pasid = 0; 1180 } 1181 1182 r = amdgpu_vm_init(adev, &fpriv->vm, pasid); 1183 if (r) 1184 goto error_pasid; 1185 1186 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1187 if (!fpriv->prt_va) { 1188 r = -ENOMEM; 1189 goto error_vm; 1190 } 1191 1192 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1193 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1194 1195 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1196 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1197 if (r) 1198 goto error_vm; 1199 } 1200 1201 mutex_init(&fpriv->bo_list_lock); 1202 idr_init(&fpriv->bo_list_handles); 1203 1204 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1205 1206 file_priv->driver_priv = fpriv; 1207 goto out_suspend; 1208 1209 error_vm: 1210 amdgpu_vm_fini(adev, &fpriv->vm); 1211 1212 error_pasid: 1213 if (pasid) 1214 amdgpu_pasid_free(pasid); 1215 1216 kfree(fpriv); 1217 1218 out_suspend: 1219 pm_runtime_mark_last_busy(dev->dev); 1220 pm_put: 1221 pm_runtime_put_autosuspend(dev->dev); 1222 1223 return r; 1224 } 1225 1226 /** 1227 * amdgpu_driver_postclose_kms - drm callback for post close 1228 * 1229 * @dev: drm dev pointer 1230 * @file_priv: drm file 1231 * 1232 * On device post close, tear down vm on cayman+ (all asics). 1233 */ 1234 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1235 struct drm_file *file_priv) 1236 { 1237 struct amdgpu_device *adev = drm_to_adev(dev); 1238 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1239 struct amdgpu_bo_list *list; 1240 struct amdgpu_bo *pd; 1241 u32 pasid; 1242 int handle; 1243 1244 if (!fpriv) 1245 return; 1246 1247 pm_runtime_get_sync(dev->dev); 1248 1249 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1250 amdgpu_uvd_free_handles(adev, file_priv); 1251 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1252 amdgpu_vce_free_handles(adev, file_priv); 1253 1254 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1255 1256 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1257 /* TODO: how to handle reserve failure */ 1258 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1259 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1260 fpriv->csa_va = NULL; 1261 amdgpu_bo_unreserve(adev->virt.csa_obj); 1262 } 1263 1264 pasid = fpriv->vm.pasid; 1265 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1266 1267 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1268 amdgpu_vm_fini(adev, &fpriv->vm); 1269 1270 if (pasid) 1271 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1272 amdgpu_bo_unref(&pd); 1273 1274 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1275 amdgpu_bo_list_put(list); 1276 1277 idr_destroy(&fpriv->bo_list_handles); 1278 mutex_destroy(&fpriv->bo_list_lock); 1279 1280 kfree(fpriv); 1281 file_priv->driver_priv = NULL; 1282 1283 pm_runtime_mark_last_busy(dev->dev); 1284 pm_runtime_put_autosuspend(dev->dev); 1285 } 1286 1287 1288 void amdgpu_driver_release_kms(struct drm_device *dev) 1289 { 1290 struct amdgpu_device *adev = drm_to_adev(dev); 1291 1292 amdgpu_device_fini_sw(adev); 1293 pci_set_drvdata(adev->pdev, NULL); 1294 } 1295 1296 /* 1297 * VBlank related functions. 1298 */ 1299 /** 1300 * amdgpu_get_vblank_counter_kms - get frame count 1301 * 1302 * @crtc: crtc to get the frame count from 1303 * 1304 * Gets the frame count on the requested crtc (all asics). 1305 * Returns frame count on success, -EINVAL on failure. 1306 */ 1307 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1308 { 1309 struct drm_device *dev = crtc->dev; 1310 unsigned int pipe = crtc->index; 1311 struct amdgpu_device *adev = drm_to_adev(dev); 1312 int vpos, hpos, stat; 1313 u32 count; 1314 1315 if (pipe >= adev->mode_info.num_crtc) { 1316 DRM_ERROR("Invalid crtc %u\n", pipe); 1317 return -EINVAL; 1318 } 1319 1320 /* The hw increments its frame counter at start of vsync, not at start 1321 * of vblank, as is required by DRM core vblank counter handling. 1322 * Cook the hw count here to make it appear to the caller as if it 1323 * incremented at start of vblank. We measure distance to start of 1324 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1325 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1326 * result by 1 to give the proper appearance to caller. 1327 */ 1328 if (adev->mode_info.crtcs[pipe]) { 1329 /* Repeat readout if needed to provide stable result if 1330 * we cross start of vsync during the queries. 1331 */ 1332 do { 1333 count = amdgpu_display_vblank_get_counter(adev, pipe); 1334 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1335 * vpos as distance to start of vblank, instead of 1336 * regular vertical scanout pos. 1337 */ 1338 stat = amdgpu_display_get_crtc_scanoutpos( 1339 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1340 &vpos, &hpos, NULL, NULL, 1341 &adev->mode_info.crtcs[pipe]->base.hwmode); 1342 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1343 1344 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1345 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1346 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1347 } else { 1348 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1349 pipe, vpos); 1350 1351 /* Bump counter if we are at >= leading edge of vblank, 1352 * but before vsync where vpos would turn negative and 1353 * the hw counter really increments. 1354 */ 1355 if (vpos >= 0) 1356 count++; 1357 } 1358 } else { 1359 /* Fallback to use value as is. */ 1360 count = amdgpu_display_vblank_get_counter(adev, pipe); 1361 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1362 } 1363 1364 return count; 1365 } 1366 1367 /** 1368 * amdgpu_enable_vblank_kms - enable vblank interrupt 1369 * 1370 * @crtc: crtc to enable vblank interrupt for 1371 * 1372 * Enable the interrupt on the requested crtc (all asics). 1373 * Returns 0 on success, -EINVAL on failure. 1374 */ 1375 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1376 { 1377 struct drm_device *dev = crtc->dev; 1378 unsigned int pipe = crtc->index; 1379 struct amdgpu_device *adev = drm_to_adev(dev); 1380 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1381 1382 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1383 } 1384 1385 /** 1386 * amdgpu_disable_vblank_kms - disable vblank interrupt 1387 * 1388 * @crtc: crtc to disable vblank interrupt for 1389 * 1390 * Disable the interrupt on the requested crtc (all asics). 1391 */ 1392 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1393 { 1394 struct drm_device *dev = crtc->dev; 1395 unsigned int pipe = crtc->index; 1396 struct amdgpu_device *adev = drm_to_adev(dev); 1397 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1398 1399 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1400 } 1401 1402 /* 1403 * Debugfs info 1404 */ 1405 #if defined(CONFIG_DEBUG_FS) 1406 1407 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1408 { 1409 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1410 struct drm_amdgpu_info_firmware fw_info; 1411 struct drm_amdgpu_query_fw query_fw; 1412 struct atom_context *ctx = adev->mode_info.atom_context; 1413 int ret, i; 1414 1415 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1416 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1417 TA_FW_NAME(XGMI), 1418 TA_FW_NAME(RAS), 1419 TA_FW_NAME(HDCP), 1420 TA_FW_NAME(DTM), 1421 TA_FW_NAME(RAP), 1422 TA_FW_NAME(SECUREDISPLAY), 1423 #undef TA_FW_NAME 1424 }; 1425 1426 /* VCE */ 1427 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1428 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1429 if (ret) 1430 return ret; 1431 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1432 fw_info.feature, fw_info.ver); 1433 1434 /* UVD */ 1435 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1436 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1437 if (ret) 1438 return ret; 1439 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1440 fw_info.feature, fw_info.ver); 1441 1442 /* GMC */ 1443 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1444 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1445 if (ret) 1446 return ret; 1447 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1448 fw_info.feature, fw_info.ver); 1449 1450 /* ME */ 1451 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1452 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1453 if (ret) 1454 return ret; 1455 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1456 fw_info.feature, fw_info.ver); 1457 1458 /* PFP */ 1459 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1460 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1461 if (ret) 1462 return ret; 1463 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1464 fw_info.feature, fw_info.ver); 1465 1466 /* CE */ 1467 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1468 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1469 if (ret) 1470 return ret; 1471 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1472 fw_info.feature, fw_info.ver); 1473 1474 /* RLC */ 1475 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1476 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1477 if (ret) 1478 return ret; 1479 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1480 fw_info.feature, fw_info.ver); 1481 1482 /* RLC SAVE RESTORE LIST CNTL */ 1483 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1484 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1485 if (ret) 1486 return ret; 1487 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1488 fw_info.feature, fw_info.ver); 1489 1490 /* RLC SAVE RESTORE LIST GPM MEM */ 1491 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1492 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1493 if (ret) 1494 return ret; 1495 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1496 fw_info.feature, fw_info.ver); 1497 1498 /* RLC SAVE RESTORE LIST SRM MEM */ 1499 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1500 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1501 if (ret) 1502 return ret; 1503 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1504 fw_info.feature, fw_info.ver); 1505 1506 /* MEC */ 1507 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1508 query_fw.index = 0; 1509 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1510 if (ret) 1511 return ret; 1512 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1513 fw_info.feature, fw_info.ver); 1514 1515 /* MEC2 */ 1516 if (adev->gfx.mec2_fw) { 1517 query_fw.index = 1; 1518 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1519 if (ret) 1520 return ret; 1521 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1522 fw_info.feature, fw_info.ver); 1523 } 1524 1525 /* PSP SOS */ 1526 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1527 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1528 if (ret) 1529 return ret; 1530 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1531 fw_info.feature, fw_info.ver); 1532 1533 1534 /* PSP ASD */ 1535 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1536 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1537 if (ret) 1538 return ret; 1539 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1540 fw_info.feature, fw_info.ver); 1541 1542 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1543 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1544 query_fw.index = i; 1545 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1546 if (ret) 1547 continue; 1548 1549 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1550 ta_fw_name[i], fw_info.feature, fw_info.ver); 1551 } 1552 1553 /* SMC */ 1554 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1555 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1556 if (ret) 1557 return ret; 1558 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1559 fw_info.feature, fw_info.ver); 1560 1561 /* SDMA */ 1562 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1563 for (i = 0; i < adev->sdma.num_instances; i++) { 1564 query_fw.index = i; 1565 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1566 if (ret) 1567 return ret; 1568 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1569 i, fw_info.feature, fw_info.ver); 1570 } 1571 1572 /* VCN */ 1573 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1574 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1575 if (ret) 1576 return ret; 1577 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1578 fw_info.feature, fw_info.ver); 1579 1580 /* DMCU */ 1581 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1582 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1583 if (ret) 1584 return ret; 1585 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1586 fw_info.feature, fw_info.ver); 1587 1588 /* DMCUB */ 1589 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1590 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1591 if (ret) 1592 return ret; 1593 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1594 fw_info.feature, fw_info.ver); 1595 1596 /* TOC */ 1597 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1598 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1599 if (ret) 1600 return ret; 1601 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1602 fw_info.feature, fw_info.ver); 1603 1604 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1605 1606 return 0; 1607 } 1608 1609 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1610 1611 #endif 1612 1613 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1614 { 1615 #if defined(CONFIG_DEBUG_FS) 1616 struct drm_minor *minor = adev_to_drm(adev)->primary; 1617 struct dentry *root = minor->debugfs_root; 1618 1619 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1620 adev, &amdgpu_debugfs_firmware_info_fops); 1621 1622 #endif 1623 } 1624