1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (adev->runpm) { 91 pm_runtime_get_sync(dev->dev); 92 pm_runtime_forbid(dev->dev); 93 } 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 if (amdgpu_has_atpx() && 141 (amdgpu_is_atpx_hybrid() || 142 amdgpu_has_atpx_dgpu_power_cntl()) && 143 ((flags & AMD_IS_APU) == 0) && 144 !pci_is_thunderbolt_attached(dev->pdev)) 145 flags |= AMD_IS_PX; 146 147 /* amdgpu_device_init should report only fatal error 148 * like memory allocation failure or iomapping failure, 149 * or memory manager initialization failure, it must 150 * properly initialize the GPU MC controller and permit 151 * VRAM allocation 152 */ 153 r = amdgpu_device_init(adev, flags); 154 if (r) { 155 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 156 goto out; 157 } 158 159 if (amdgpu_device_supports_boco(dev) && 160 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 161 adev->runpm = true; 162 } else if (amdgpu_device_supports_baco(dev) && 163 (amdgpu_runtime_pm != 0)) { 164 switch (adev->asic_type) { 165 #ifdef CONFIG_DRM_AMDGPU_CIK 166 case CHIP_BONAIRE: 167 case CHIP_HAWAII: 168 #endif 169 case CHIP_VEGA20: 170 case CHIP_ARCTURUS: 171 case CHIP_SIENNA_CICHLID: 172 case CHIP_NAVY_FLOUNDER: 173 /* enable runpm if runpm=1 */ 174 if (amdgpu_runtime_pm > 0) 175 adev->runpm = true; 176 break; 177 case CHIP_VEGA10: 178 /* turn runpm on if noretry=0 */ 179 if (!adev->gmc.noretry) 180 adev->runpm = true; 181 break; 182 default: 183 /* enable runpm on VI+ */ 184 adev->runpm = true; 185 break; 186 } 187 } 188 189 /* Call ACPI methods: require modeset init 190 * but failure is not fatal 191 */ 192 193 acpi_status = amdgpu_acpi_init(adev); 194 if (acpi_status) 195 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 196 197 if (adev->runpm) { 198 /* only need to skip on ATPX */ 199 if (amdgpu_device_supports_boco(dev) && 200 !amdgpu_is_atpx_hybrid()) 201 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 202 pm_runtime_use_autosuspend(dev->dev); 203 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 204 pm_runtime_allow(dev->dev); 205 pm_runtime_mark_last_busy(dev->dev); 206 pm_runtime_put_autosuspend(dev->dev); 207 } 208 209 out: 210 if (r) { 211 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 212 if (adev->rmmio && adev->runpm) 213 pm_runtime_put_noidle(dev->dev); 214 amdgpu_driver_unload_kms(dev); 215 } 216 217 return r; 218 } 219 220 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 221 struct drm_amdgpu_query_fw *query_fw, 222 struct amdgpu_device *adev) 223 { 224 switch (query_fw->fw_type) { 225 case AMDGPU_INFO_FW_VCE: 226 fw_info->ver = adev->vce.fw_version; 227 fw_info->feature = adev->vce.fb_version; 228 break; 229 case AMDGPU_INFO_FW_UVD: 230 fw_info->ver = adev->uvd.fw_version; 231 fw_info->feature = 0; 232 break; 233 case AMDGPU_INFO_FW_VCN: 234 fw_info->ver = adev->vcn.fw_version; 235 fw_info->feature = 0; 236 break; 237 case AMDGPU_INFO_FW_GMC: 238 fw_info->ver = adev->gmc.fw_version; 239 fw_info->feature = 0; 240 break; 241 case AMDGPU_INFO_FW_GFX_ME: 242 fw_info->ver = adev->gfx.me_fw_version; 243 fw_info->feature = adev->gfx.me_feature_version; 244 break; 245 case AMDGPU_INFO_FW_GFX_PFP: 246 fw_info->ver = adev->gfx.pfp_fw_version; 247 fw_info->feature = adev->gfx.pfp_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_CE: 250 fw_info->ver = adev->gfx.ce_fw_version; 251 fw_info->feature = adev->gfx.ce_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_RLC: 254 fw_info->ver = adev->gfx.rlc_fw_version; 255 fw_info->feature = adev->gfx.rlc_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 258 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 259 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 262 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 263 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 264 break; 265 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 266 fw_info->ver = adev->gfx.rlc_srls_fw_version; 267 fw_info->feature = adev->gfx.rlc_srls_feature_version; 268 break; 269 case AMDGPU_INFO_FW_GFX_MEC: 270 if (query_fw->index == 0) { 271 fw_info->ver = adev->gfx.mec_fw_version; 272 fw_info->feature = adev->gfx.mec_feature_version; 273 } else if (query_fw->index == 1) { 274 fw_info->ver = adev->gfx.mec2_fw_version; 275 fw_info->feature = adev->gfx.mec2_feature_version; 276 } else 277 return -EINVAL; 278 break; 279 case AMDGPU_INFO_FW_SMC: 280 fw_info->ver = adev->pm.fw_version; 281 fw_info->feature = 0; 282 break; 283 case AMDGPU_INFO_FW_TA: 284 switch (query_fw->index) { 285 case 0: 286 fw_info->ver = adev->psp.ta_fw_version; 287 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 288 break; 289 case 1: 290 fw_info->ver = adev->psp.ta_fw_version; 291 fw_info->feature = adev->psp.ta_ras_ucode_version; 292 break; 293 case 2: 294 fw_info->ver = adev->psp.ta_fw_version; 295 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 296 break; 297 case 3: 298 fw_info->ver = adev->psp.ta_fw_version; 299 fw_info->feature = adev->psp.ta_dtm_ucode_version; 300 break; 301 default: 302 return -EINVAL; 303 } 304 break; 305 case AMDGPU_INFO_FW_SDMA: 306 if (query_fw->index >= adev->sdma.num_instances) 307 return -EINVAL; 308 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 309 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 310 break; 311 case AMDGPU_INFO_FW_SOS: 312 fw_info->ver = adev->psp.sos_fw_version; 313 fw_info->feature = adev->psp.sos_feature_version; 314 break; 315 case AMDGPU_INFO_FW_ASD: 316 fw_info->ver = adev->psp.asd_fw_version; 317 fw_info->feature = adev->psp.asd_feature_version; 318 break; 319 case AMDGPU_INFO_FW_DMCU: 320 fw_info->ver = adev->dm.dmcu_fw_version; 321 fw_info->feature = 0; 322 break; 323 case AMDGPU_INFO_FW_DMCUB: 324 fw_info->ver = adev->dm.dmcub_fw_version; 325 fw_info->feature = 0; 326 break; 327 default: 328 return -EINVAL; 329 } 330 return 0; 331 } 332 333 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 334 struct drm_amdgpu_info *info, 335 struct drm_amdgpu_info_hw_ip *result) 336 { 337 uint32_t ib_start_alignment = 0; 338 uint32_t ib_size_alignment = 0; 339 enum amd_ip_block_type type; 340 unsigned int num_rings = 0; 341 unsigned int i, j; 342 343 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 344 return -EINVAL; 345 346 switch (info->query_hw_ip.type) { 347 case AMDGPU_HW_IP_GFX: 348 type = AMD_IP_BLOCK_TYPE_GFX; 349 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 350 if (adev->gfx.gfx_ring[i].sched.ready) 351 ++num_rings; 352 ib_start_alignment = 32; 353 ib_size_alignment = 32; 354 break; 355 case AMDGPU_HW_IP_COMPUTE: 356 type = AMD_IP_BLOCK_TYPE_GFX; 357 for (i = 0; i < adev->gfx.num_compute_rings; i++) 358 if (adev->gfx.compute_ring[i].sched.ready) 359 ++num_rings; 360 ib_start_alignment = 32; 361 ib_size_alignment = 32; 362 break; 363 case AMDGPU_HW_IP_DMA: 364 type = AMD_IP_BLOCK_TYPE_SDMA; 365 for (i = 0; i < adev->sdma.num_instances; i++) 366 if (adev->sdma.instance[i].ring.sched.ready) 367 ++num_rings; 368 ib_start_alignment = 256; 369 ib_size_alignment = 4; 370 break; 371 case AMDGPU_HW_IP_UVD: 372 type = AMD_IP_BLOCK_TYPE_UVD; 373 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 374 if (adev->uvd.harvest_config & (1 << i)) 375 continue; 376 377 if (adev->uvd.inst[i].ring.sched.ready) 378 ++num_rings; 379 } 380 ib_start_alignment = 64; 381 ib_size_alignment = 64; 382 break; 383 case AMDGPU_HW_IP_VCE: 384 type = AMD_IP_BLOCK_TYPE_VCE; 385 for (i = 0; i < adev->vce.num_rings; i++) 386 if (adev->vce.ring[i].sched.ready) 387 ++num_rings; 388 ib_start_alignment = 4; 389 ib_size_alignment = 1; 390 break; 391 case AMDGPU_HW_IP_UVD_ENC: 392 type = AMD_IP_BLOCK_TYPE_UVD; 393 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 394 if (adev->uvd.harvest_config & (1 << i)) 395 continue; 396 397 for (j = 0; j < adev->uvd.num_enc_rings; j++) 398 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 399 ++num_rings; 400 } 401 ib_start_alignment = 64; 402 ib_size_alignment = 64; 403 break; 404 case AMDGPU_HW_IP_VCN_DEC: 405 type = AMD_IP_BLOCK_TYPE_VCN; 406 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 407 if (adev->uvd.harvest_config & (1 << i)) 408 continue; 409 410 if (adev->vcn.inst[i].ring_dec.sched.ready) 411 ++num_rings; 412 } 413 ib_start_alignment = 16; 414 ib_size_alignment = 16; 415 break; 416 case AMDGPU_HW_IP_VCN_ENC: 417 type = AMD_IP_BLOCK_TYPE_VCN; 418 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 419 if (adev->uvd.harvest_config & (1 << i)) 420 continue; 421 422 for (j = 0; j < adev->vcn.num_enc_rings; j++) 423 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 424 ++num_rings; 425 } 426 ib_start_alignment = 64; 427 ib_size_alignment = 1; 428 break; 429 case AMDGPU_HW_IP_VCN_JPEG: 430 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 431 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 432 433 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 434 if (adev->jpeg.harvest_config & (1 << i)) 435 continue; 436 437 if (adev->jpeg.inst[i].ring_dec.sched.ready) 438 ++num_rings; 439 } 440 ib_start_alignment = 16; 441 ib_size_alignment = 16; 442 break; 443 default: 444 return -EINVAL; 445 } 446 447 for (i = 0; i < adev->num_ip_blocks; i++) 448 if (adev->ip_blocks[i].version->type == type && 449 adev->ip_blocks[i].status.valid) 450 break; 451 452 if (i == adev->num_ip_blocks) 453 return 0; 454 455 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 456 num_rings); 457 458 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 459 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 460 result->capabilities_flags = 0; 461 result->available_rings = (1 << num_rings) - 1; 462 result->ib_start_alignment = ib_start_alignment; 463 result->ib_size_alignment = ib_size_alignment; 464 return 0; 465 } 466 467 /* 468 * Userspace get information ioctl 469 */ 470 /** 471 * amdgpu_info_ioctl - answer a device specific request. 472 * 473 * @adev: amdgpu device pointer 474 * @data: request object 475 * @filp: drm filp 476 * 477 * This function is used to pass device specific parameters to the userspace 478 * drivers. Examples include: pci device id, pipeline parms, tiling params, 479 * etc. (all asics). 480 * Returns 0 on success, -EINVAL on failure. 481 */ 482 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 483 { 484 struct amdgpu_device *adev = drm_to_adev(dev); 485 struct drm_amdgpu_info *info = data; 486 struct amdgpu_mode_info *minfo = &adev->mode_info; 487 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 488 uint32_t size = info->return_size; 489 struct drm_crtc *crtc; 490 uint32_t ui32 = 0; 491 uint64_t ui64 = 0; 492 int i, found; 493 int ui32_size = sizeof(ui32); 494 495 if (!info->return_size || !info->return_pointer) 496 return -EINVAL; 497 498 switch (info->query) { 499 case AMDGPU_INFO_ACCEL_WORKING: 500 ui32 = adev->accel_working; 501 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 502 case AMDGPU_INFO_CRTC_FROM_ID: 503 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 504 crtc = (struct drm_crtc *)minfo->crtcs[i]; 505 if (crtc && crtc->base.id == info->mode_crtc.id) { 506 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 507 ui32 = amdgpu_crtc->crtc_id; 508 found = 1; 509 break; 510 } 511 } 512 if (!found) { 513 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 514 return -EINVAL; 515 } 516 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 517 case AMDGPU_INFO_HW_IP_INFO: { 518 struct drm_amdgpu_info_hw_ip ip = {}; 519 int ret; 520 521 ret = amdgpu_hw_ip_info(adev, info, &ip); 522 if (ret) 523 return ret; 524 525 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 526 return ret ? -EFAULT : 0; 527 } 528 case AMDGPU_INFO_HW_IP_COUNT: { 529 enum amd_ip_block_type type; 530 uint32_t count = 0; 531 532 switch (info->query_hw_ip.type) { 533 case AMDGPU_HW_IP_GFX: 534 type = AMD_IP_BLOCK_TYPE_GFX; 535 break; 536 case AMDGPU_HW_IP_COMPUTE: 537 type = AMD_IP_BLOCK_TYPE_GFX; 538 break; 539 case AMDGPU_HW_IP_DMA: 540 type = AMD_IP_BLOCK_TYPE_SDMA; 541 break; 542 case AMDGPU_HW_IP_UVD: 543 type = AMD_IP_BLOCK_TYPE_UVD; 544 break; 545 case AMDGPU_HW_IP_VCE: 546 type = AMD_IP_BLOCK_TYPE_VCE; 547 break; 548 case AMDGPU_HW_IP_UVD_ENC: 549 type = AMD_IP_BLOCK_TYPE_UVD; 550 break; 551 case AMDGPU_HW_IP_VCN_DEC: 552 case AMDGPU_HW_IP_VCN_ENC: 553 type = AMD_IP_BLOCK_TYPE_VCN; 554 break; 555 case AMDGPU_HW_IP_VCN_JPEG: 556 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 557 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 558 break; 559 default: 560 return -EINVAL; 561 } 562 563 for (i = 0; i < adev->num_ip_blocks; i++) 564 if (adev->ip_blocks[i].version->type == type && 565 adev->ip_blocks[i].status.valid && 566 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 567 count++; 568 569 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 570 } 571 case AMDGPU_INFO_TIMESTAMP: 572 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 573 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 574 case AMDGPU_INFO_FW_VERSION: { 575 struct drm_amdgpu_info_firmware fw_info; 576 int ret; 577 578 /* We only support one instance of each IP block right now. */ 579 if (info->query_fw.ip_instance != 0) 580 return -EINVAL; 581 582 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 583 if (ret) 584 return ret; 585 586 return copy_to_user(out, &fw_info, 587 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 588 } 589 case AMDGPU_INFO_NUM_BYTES_MOVED: 590 ui64 = atomic64_read(&adev->num_bytes_moved); 591 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 592 case AMDGPU_INFO_NUM_EVICTIONS: 593 ui64 = atomic64_read(&adev->num_evictions); 594 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 595 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 596 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 597 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 598 case AMDGPU_INFO_VRAM_USAGE: 599 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 600 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 601 case AMDGPU_INFO_VIS_VRAM_USAGE: 602 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 603 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 604 case AMDGPU_INFO_GTT_USAGE: 605 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 606 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 607 case AMDGPU_INFO_GDS_CONFIG: { 608 struct drm_amdgpu_info_gds gds_info; 609 610 memset(&gds_info, 0, sizeof(gds_info)); 611 gds_info.compute_partition_size = adev->gds.gds_size; 612 gds_info.gds_total_size = adev->gds.gds_size; 613 gds_info.gws_per_compute_partition = adev->gds.gws_size; 614 gds_info.oa_per_compute_partition = adev->gds.oa_size; 615 return copy_to_user(out, &gds_info, 616 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 617 } 618 case AMDGPU_INFO_VRAM_GTT: { 619 struct drm_amdgpu_info_vram_gtt vram_gtt; 620 621 vram_gtt.vram_size = adev->gmc.real_vram_size - 622 atomic64_read(&adev->vram_pin_size) - 623 AMDGPU_VM_RESERVED_VRAM; 624 vram_gtt.vram_cpu_accessible_size = 625 min(adev->gmc.visible_vram_size - 626 atomic64_read(&adev->visible_pin_size), 627 vram_gtt.vram_size); 628 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 629 vram_gtt.gtt_size *= PAGE_SIZE; 630 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 631 return copy_to_user(out, &vram_gtt, 632 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 633 } 634 case AMDGPU_INFO_MEMORY: { 635 struct drm_amdgpu_memory_info mem; 636 struct ttm_resource_manager *vram_man = 637 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 638 struct ttm_resource_manager *gtt_man = 639 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 640 memset(&mem, 0, sizeof(mem)); 641 mem.vram.total_heap_size = adev->gmc.real_vram_size; 642 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 643 atomic64_read(&adev->vram_pin_size) - 644 AMDGPU_VM_RESERVED_VRAM; 645 mem.vram.heap_usage = 646 amdgpu_vram_mgr_usage(vram_man); 647 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 648 649 mem.cpu_accessible_vram.total_heap_size = 650 adev->gmc.visible_vram_size; 651 mem.cpu_accessible_vram.usable_heap_size = 652 min(adev->gmc.visible_vram_size - 653 atomic64_read(&adev->visible_pin_size), 654 mem.vram.usable_heap_size); 655 mem.cpu_accessible_vram.heap_usage = 656 amdgpu_vram_mgr_vis_usage(vram_man); 657 mem.cpu_accessible_vram.max_allocation = 658 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 659 660 mem.gtt.total_heap_size = gtt_man->size; 661 mem.gtt.total_heap_size *= PAGE_SIZE; 662 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 663 atomic64_read(&adev->gart_pin_size); 664 mem.gtt.heap_usage = 665 amdgpu_gtt_mgr_usage(gtt_man); 666 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 667 668 return copy_to_user(out, &mem, 669 min((size_t)size, sizeof(mem))) 670 ? -EFAULT : 0; 671 } 672 case AMDGPU_INFO_READ_MMR_REG: { 673 unsigned n, alloc_size; 674 uint32_t *regs; 675 unsigned se_num = (info->read_mmr_reg.instance >> 676 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 677 AMDGPU_INFO_MMR_SE_INDEX_MASK; 678 unsigned sh_num = (info->read_mmr_reg.instance >> 679 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 680 AMDGPU_INFO_MMR_SH_INDEX_MASK; 681 682 /* set full masks if the userspace set all bits 683 * in the bitfields */ 684 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 685 se_num = 0xffffffff; 686 else if (se_num >= AMDGPU_GFX_MAX_SE) 687 return -EINVAL; 688 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 689 sh_num = 0xffffffff; 690 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 691 return -EINVAL; 692 693 if (info->read_mmr_reg.count > 128) 694 return -EINVAL; 695 696 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 697 if (!regs) 698 return -ENOMEM; 699 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 700 701 amdgpu_gfx_off_ctrl(adev, false); 702 for (i = 0; i < info->read_mmr_reg.count; i++) { 703 if (amdgpu_asic_read_register(adev, se_num, sh_num, 704 info->read_mmr_reg.dword_offset + i, 705 ®s[i])) { 706 DRM_DEBUG_KMS("unallowed offset %#x\n", 707 info->read_mmr_reg.dword_offset + i); 708 kfree(regs); 709 amdgpu_gfx_off_ctrl(adev, true); 710 return -EFAULT; 711 } 712 } 713 amdgpu_gfx_off_ctrl(adev, true); 714 n = copy_to_user(out, regs, min(size, alloc_size)); 715 kfree(regs); 716 return n ? -EFAULT : 0; 717 } 718 case AMDGPU_INFO_DEV_INFO: { 719 struct drm_amdgpu_info_device dev_info; 720 uint64_t vm_size; 721 722 memset(&dev_info, 0, sizeof(dev_info)); 723 dev_info.device_id = dev->pdev->device; 724 dev_info.chip_rev = adev->rev_id; 725 dev_info.external_rev = adev->external_rev_id; 726 dev_info.pci_rev = dev->pdev->revision; 727 dev_info.family = adev->family; 728 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 729 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 730 /* return all clocks in KHz */ 731 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 732 if (adev->pm.dpm_enabled) { 733 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 734 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 735 } else { 736 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 737 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 738 } 739 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 740 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 741 adev->gfx.config.max_shader_engines; 742 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 743 dev_info._pad = 0; 744 dev_info.ids_flags = 0; 745 if (adev->flags & AMD_IS_APU) 746 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 747 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 748 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 749 if (amdgpu_is_tmz(adev)) 750 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 751 752 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 753 vm_size -= AMDGPU_VA_RESERVED_SIZE; 754 755 /* Older VCE FW versions are buggy and can handle only 40bits */ 756 if (adev->vce.fw_version && 757 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 758 vm_size = min(vm_size, 1ULL << 40); 759 760 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 761 dev_info.virtual_address_max = 762 min(vm_size, AMDGPU_GMC_HOLE_START); 763 764 if (vm_size > AMDGPU_GMC_HOLE_START) { 765 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 766 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 767 } 768 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 769 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 770 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 771 dev_info.cu_active_number = adev->gfx.cu_info.number; 772 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 773 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 774 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 775 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 776 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 777 sizeof(adev->gfx.cu_info.bitmap)); 778 dev_info.vram_type = adev->gmc.vram_type; 779 dev_info.vram_bit_width = adev->gmc.vram_width; 780 dev_info.vce_harvest_config = adev->vce.harvest_config; 781 dev_info.gc_double_offchip_lds_buf = 782 adev->gfx.config.double_offchip_lds_buf; 783 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 784 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 785 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 786 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 787 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 788 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 789 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 790 791 if (adev->family >= AMDGPU_FAMILY_NV) 792 dev_info.pa_sc_tile_steering_override = 793 adev->gfx.config.pa_sc_tile_steering_override; 794 795 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 796 797 return copy_to_user(out, &dev_info, 798 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 799 } 800 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 801 unsigned i; 802 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 803 struct amd_vce_state *vce_state; 804 805 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 806 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 807 if (vce_state) { 808 vce_clk_table.entries[i].sclk = vce_state->sclk; 809 vce_clk_table.entries[i].mclk = vce_state->mclk; 810 vce_clk_table.entries[i].eclk = vce_state->evclk; 811 vce_clk_table.num_valid_entries++; 812 } 813 } 814 815 return copy_to_user(out, &vce_clk_table, 816 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 817 } 818 case AMDGPU_INFO_VBIOS: { 819 uint32_t bios_size = adev->bios_size; 820 821 switch (info->vbios_info.type) { 822 case AMDGPU_INFO_VBIOS_SIZE: 823 return copy_to_user(out, &bios_size, 824 min((size_t)size, sizeof(bios_size))) 825 ? -EFAULT : 0; 826 case AMDGPU_INFO_VBIOS_IMAGE: { 827 uint8_t *bios; 828 uint32_t bios_offset = info->vbios_info.offset; 829 830 if (bios_offset >= bios_size) 831 return -EINVAL; 832 833 bios = adev->bios + bios_offset; 834 return copy_to_user(out, bios, 835 min((size_t)size, (size_t)(bios_size - bios_offset))) 836 ? -EFAULT : 0; 837 } 838 default: 839 DRM_DEBUG_KMS("Invalid request %d\n", 840 info->vbios_info.type); 841 return -EINVAL; 842 } 843 } 844 case AMDGPU_INFO_NUM_HANDLES: { 845 struct drm_amdgpu_info_num_handles handle; 846 847 switch (info->query_hw_ip.type) { 848 case AMDGPU_HW_IP_UVD: 849 /* Starting Polaris, we support unlimited UVD handles */ 850 if (adev->asic_type < CHIP_POLARIS10) { 851 handle.uvd_max_handles = adev->uvd.max_handles; 852 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 853 854 return copy_to_user(out, &handle, 855 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 856 } else { 857 return -ENODATA; 858 } 859 860 break; 861 default: 862 return -EINVAL; 863 } 864 } 865 case AMDGPU_INFO_SENSOR: { 866 if (!adev->pm.dpm_enabled) 867 return -ENOENT; 868 869 switch (info->sensor_info.type) { 870 case AMDGPU_INFO_SENSOR_GFX_SCLK: 871 /* get sclk in Mhz */ 872 if (amdgpu_dpm_read_sensor(adev, 873 AMDGPU_PP_SENSOR_GFX_SCLK, 874 (void *)&ui32, &ui32_size)) { 875 return -EINVAL; 876 } 877 ui32 /= 100; 878 break; 879 case AMDGPU_INFO_SENSOR_GFX_MCLK: 880 /* get mclk in Mhz */ 881 if (amdgpu_dpm_read_sensor(adev, 882 AMDGPU_PP_SENSOR_GFX_MCLK, 883 (void *)&ui32, &ui32_size)) { 884 return -EINVAL; 885 } 886 ui32 /= 100; 887 break; 888 case AMDGPU_INFO_SENSOR_GPU_TEMP: 889 /* get temperature in millidegrees C */ 890 if (amdgpu_dpm_read_sensor(adev, 891 AMDGPU_PP_SENSOR_GPU_TEMP, 892 (void *)&ui32, &ui32_size)) { 893 return -EINVAL; 894 } 895 break; 896 case AMDGPU_INFO_SENSOR_GPU_LOAD: 897 /* get GPU load */ 898 if (amdgpu_dpm_read_sensor(adev, 899 AMDGPU_PP_SENSOR_GPU_LOAD, 900 (void *)&ui32, &ui32_size)) { 901 return -EINVAL; 902 } 903 break; 904 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 905 /* get average GPU power */ 906 if (amdgpu_dpm_read_sensor(adev, 907 AMDGPU_PP_SENSOR_GPU_POWER, 908 (void *)&ui32, &ui32_size)) { 909 return -EINVAL; 910 } 911 ui32 >>= 8; 912 break; 913 case AMDGPU_INFO_SENSOR_VDDNB: 914 /* get VDDNB in millivolts */ 915 if (amdgpu_dpm_read_sensor(adev, 916 AMDGPU_PP_SENSOR_VDDNB, 917 (void *)&ui32, &ui32_size)) { 918 return -EINVAL; 919 } 920 break; 921 case AMDGPU_INFO_SENSOR_VDDGFX: 922 /* get VDDGFX in millivolts */ 923 if (amdgpu_dpm_read_sensor(adev, 924 AMDGPU_PP_SENSOR_VDDGFX, 925 (void *)&ui32, &ui32_size)) { 926 return -EINVAL; 927 } 928 break; 929 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 930 /* get stable pstate sclk in Mhz */ 931 if (amdgpu_dpm_read_sensor(adev, 932 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 933 (void *)&ui32, &ui32_size)) { 934 return -EINVAL; 935 } 936 ui32 /= 100; 937 break; 938 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 939 /* get stable pstate mclk in Mhz */ 940 if (amdgpu_dpm_read_sensor(adev, 941 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 942 (void *)&ui32, &ui32_size)) { 943 return -EINVAL; 944 } 945 ui32 /= 100; 946 break; 947 default: 948 DRM_DEBUG_KMS("Invalid request %d\n", 949 info->sensor_info.type); 950 return -EINVAL; 951 } 952 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 953 } 954 case AMDGPU_INFO_VRAM_LOST_COUNTER: 955 ui32 = atomic_read(&adev->vram_lost_counter); 956 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 957 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 958 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 959 uint64_t ras_mask; 960 961 if (!ras) 962 return -EINVAL; 963 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 964 965 return copy_to_user(out, &ras_mask, 966 min_t(u64, size, sizeof(ras_mask))) ? 967 -EFAULT : 0; 968 } 969 default: 970 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 971 return -EINVAL; 972 } 973 return 0; 974 } 975 976 977 /* 978 * Outdated mess for old drm with Xorg being in charge (void function now). 979 */ 980 /** 981 * amdgpu_driver_lastclose_kms - drm callback for last close 982 * 983 * @dev: drm dev pointer 984 * 985 * Switch vga_switcheroo state after last close (all asics). 986 */ 987 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 988 { 989 drm_fb_helper_lastclose(dev); 990 vga_switcheroo_process_delayed_switch(); 991 } 992 993 /** 994 * amdgpu_driver_open_kms - drm callback for open 995 * 996 * @dev: drm dev pointer 997 * @file_priv: drm file 998 * 999 * On device open, init vm on cayman+ (all asics). 1000 * Returns 0 on success, error on failure. 1001 */ 1002 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1003 { 1004 struct amdgpu_device *adev = drm_to_adev(dev); 1005 struct amdgpu_fpriv *fpriv; 1006 int r, pasid; 1007 1008 /* Ensure IB tests are run on ring */ 1009 flush_delayed_work(&adev->delayed_init_work); 1010 1011 1012 if (amdgpu_ras_intr_triggered()) { 1013 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1014 return -EHWPOISON; 1015 } 1016 1017 file_priv->driver_priv = NULL; 1018 1019 r = pm_runtime_get_sync(dev->dev); 1020 if (r < 0) 1021 goto pm_put; 1022 1023 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1024 if (unlikely(!fpriv)) { 1025 r = -ENOMEM; 1026 goto out_suspend; 1027 } 1028 1029 pasid = amdgpu_pasid_alloc(16); 1030 if (pasid < 0) { 1031 dev_warn(adev->dev, "No more PASIDs available!"); 1032 pasid = 0; 1033 } 1034 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1035 if (r) 1036 goto error_pasid; 1037 1038 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1039 if (!fpriv->prt_va) { 1040 r = -ENOMEM; 1041 goto error_vm; 1042 } 1043 1044 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1045 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1046 1047 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1048 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1049 if (r) 1050 goto error_vm; 1051 } 1052 1053 mutex_init(&fpriv->bo_list_lock); 1054 idr_init(&fpriv->bo_list_handles); 1055 1056 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1057 1058 file_priv->driver_priv = fpriv; 1059 goto out_suspend; 1060 1061 error_vm: 1062 amdgpu_vm_fini(adev, &fpriv->vm); 1063 1064 error_pasid: 1065 if (pasid) 1066 amdgpu_pasid_free(pasid); 1067 1068 kfree(fpriv); 1069 1070 out_suspend: 1071 pm_runtime_mark_last_busy(dev->dev); 1072 pm_put: 1073 pm_runtime_put_autosuspend(dev->dev); 1074 1075 return r; 1076 } 1077 1078 /** 1079 * amdgpu_driver_postclose_kms - drm callback for post close 1080 * 1081 * @dev: drm dev pointer 1082 * @file_priv: drm file 1083 * 1084 * On device post close, tear down vm on cayman+ (all asics). 1085 */ 1086 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1087 struct drm_file *file_priv) 1088 { 1089 struct amdgpu_device *adev = drm_to_adev(dev); 1090 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1091 struct amdgpu_bo_list *list; 1092 struct amdgpu_bo *pd; 1093 u32 pasid; 1094 int handle; 1095 1096 if (!fpriv) 1097 return; 1098 1099 pm_runtime_get_sync(dev->dev); 1100 1101 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1102 amdgpu_uvd_free_handles(adev, file_priv); 1103 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1104 amdgpu_vce_free_handles(adev, file_priv); 1105 1106 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1107 1108 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1109 /* TODO: how to handle reserve failure */ 1110 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1111 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1112 fpriv->csa_va = NULL; 1113 amdgpu_bo_unreserve(adev->virt.csa_obj); 1114 } 1115 1116 pasid = fpriv->vm.pasid; 1117 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1118 1119 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1120 amdgpu_vm_fini(adev, &fpriv->vm); 1121 1122 if (pasid) 1123 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1124 amdgpu_bo_unref(&pd); 1125 1126 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1127 amdgpu_bo_list_put(list); 1128 1129 idr_destroy(&fpriv->bo_list_handles); 1130 mutex_destroy(&fpriv->bo_list_lock); 1131 1132 kfree(fpriv); 1133 file_priv->driver_priv = NULL; 1134 1135 pm_runtime_mark_last_busy(dev->dev); 1136 pm_runtime_put_autosuspend(dev->dev); 1137 } 1138 1139 /* 1140 * VBlank related functions. 1141 */ 1142 /** 1143 * amdgpu_get_vblank_counter_kms - get frame count 1144 * 1145 * @crtc: crtc to get the frame count from 1146 * 1147 * Gets the frame count on the requested crtc (all asics). 1148 * Returns frame count on success, -EINVAL on failure. 1149 */ 1150 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1151 { 1152 struct drm_device *dev = crtc->dev; 1153 unsigned int pipe = crtc->index; 1154 struct amdgpu_device *adev = drm_to_adev(dev); 1155 int vpos, hpos, stat; 1156 u32 count; 1157 1158 if (pipe >= adev->mode_info.num_crtc) { 1159 DRM_ERROR("Invalid crtc %u\n", pipe); 1160 return -EINVAL; 1161 } 1162 1163 /* The hw increments its frame counter at start of vsync, not at start 1164 * of vblank, as is required by DRM core vblank counter handling. 1165 * Cook the hw count here to make it appear to the caller as if it 1166 * incremented at start of vblank. We measure distance to start of 1167 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1168 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1169 * result by 1 to give the proper appearance to caller. 1170 */ 1171 if (adev->mode_info.crtcs[pipe]) { 1172 /* Repeat readout if needed to provide stable result if 1173 * we cross start of vsync during the queries. 1174 */ 1175 do { 1176 count = amdgpu_display_vblank_get_counter(adev, pipe); 1177 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1178 * vpos as distance to start of vblank, instead of 1179 * regular vertical scanout pos. 1180 */ 1181 stat = amdgpu_display_get_crtc_scanoutpos( 1182 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1183 &vpos, &hpos, NULL, NULL, 1184 &adev->mode_info.crtcs[pipe]->base.hwmode); 1185 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1186 1187 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1188 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1189 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1190 } else { 1191 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1192 pipe, vpos); 1193 1194 /* Bump counter if we are at >= leading edge of vblank, 1195 * but before vsync where vpos would turn negative and 1196 * the hw counter really increments. 1197 */ 1198 if (vpos >= 0) 1199 count++; 1200 } 1201 } else { 1202 /* Fallback to use value as is. */ 1203 count = amdgpu_display_vblank_get_counter(adev, pipe); 1204 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1205 } 1206 1207 return count; 1208 } 1209 1210 /** 1211 * amdgpu_enable_vblank_kms - enable vblank interrupt 1212 * 1213 * @crtc: crtc to enable vblank interrupt for 1214 * 1215 * Enable the interrupt on the requested crtc (all asics). 1216 * Returns 0 on success, -EINVAL on failure. 1217 */ 1218 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1219 { 1220 struct drm_device *dev = crtc->dev; 1221 unsigned int pipe = crtc->index; 1222 struct amdgpu_device *adev = drm_to_adev(dev); 1223 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1224 1225 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1226 } 1227 1228 /** 1229 * amdgpu_disable_vblank_kms - disable vblank interrupt 1230 * 1231 * @crtc: crtc to disable vblank interrupt for 1232 * 1233 * Disable the interrupt on the requested crtc (all asics). 1234 */ 1235 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1236 { 1237 struct drm_device *dev = crtc->dev; 1238 unsigned int pipe = crtc->index; 1239 struct amdgpu_device *adev = drm_to_adev(dev); 1240 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1241 1242 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1243 } 1244 1245 /* 1246 * Debugfs info 1247 */ 1248 #if defined(CONFIG_DEBUG_FS) 1249 1250 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1251 { 1252 struct drm_info_node *node = (struct drm_info_node *) m->private; 1253 struct drm_device *dev = node->minor->dev; 1254 struct amdgpu_device *adev = drm_to_adev(dev); 1255 struct drm_amdgpu_info_firmware fw_info; 1256 struct drm_amdgpu_query_fw query_fw; 1257 struct atom_context *ctx = adev->mode_info.atom_context; 1258 int ret, i; 1259 1260 /* VCE */ 1261 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1262 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1263 if (ret) 1264 return ret; 1265 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1266 fw_info.feature, fw_info.ver); 1267 1268 /* UVD */ 1269 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1270 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1271 if (ret) 1272 return ret; 1273 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1274 fw_info.feature, fw_info.ver); 1275 1276 /* GMC */ 1277 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1278 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1279 if (ret) 1280 return ret; 1281 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1282 fw_info.feature, fw_info.ver); 1283 1284 /* ME */ 1285 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1286 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1287 if (ret) 1288 return ret; 1289 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1290 fw_info.feature, fw_info.ver); 1291 1292 /* PFP */ 1293 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1294 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1295 if (ret) 1296 return ret; 1297 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1298 fw_info.feature, fw_info.ver); 1299 1300 /* CE */ 1301 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1302 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1303 if (ret) 1304 return ret; 1305 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1306 fw_info.feature, fw_info.ver); 1307 1308 /* RLC */ 1309 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1310 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1311 if (ret) 1312 return ret; 1313 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1314 fw_info.feature, fw_info.ver); 1315 1316 /* RLC SAVE RESTORE LIST CNTL */ 1317 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1318 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1319 if (ret) 1320 return ret; 1321 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1322 fw_info.feature, fw_info.ver); 1323 1324 /* RLC SAVE RESTORE LIST GPM MEM */ 1325 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1326 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1327 if (ret) 1328 return ret; 1329 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1330 fw_info.feature, fw_info.ver); 1331 1332 /* RLC SAVE RESTORE LIST SRM MEM */ 1333 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1334 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1335 if (ret) 1336 return ret; 1337 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1338 fw_info.feature, fw_info.ver); 1339 1340 /* MEC */ 1341 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1342 query_fw.index = 0; 1343 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1344 if (ret) 1345 return ret; 1346 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1347 fw_info.feature, fw_info.ver); 1348 1349 /* MEC2 */ 1350 if (adev->gfx.mec2_fw) { 1351 query_fw.index = 1; 1352 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1353 if (ret) 1354 return ret; 1355 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1356 fw_info.feature, fw_info.ver); 1357 } 1358 1359 /* PSP SOS */ 1360 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1361 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1362 if (ret) 1363 return ret; 1364 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1365 fw_info.feature, fw_info.ver); 1366 1367 1368 /* PSP ASD */ 1369 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1370 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1371 if (ret) 1372 return ret; 1373 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1374 fw_info.feature, fw_info.ver); 1375 1376 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1377 for (i = 0; i < 4; i++) { 1378 query_fw.index = i; 1379 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1380 if (ret) 1381 continue; 1382 switch (query_fw.index) { 1383 case 0: 1384 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1385 "RAS", fw_info.feature, fw_info.ver); 1386 break; 1387 case 1: 1388 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1389 "XGMI", fw_info.feature, fw_info.ver); 1390 break; 1391 case 2: 1392 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1393 "HDCP", fw_info.feature, fw_info.ver); 1394 break; 1395 case 3: 1396 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1397 "DTM", fw_info.feature, fw_info.ver); 1398 break; 1399 default: 1400 return -EINVAL; 1401 } 1402 } 1403 1404 /* SMC */ 1405 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1406 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1407 if (ret) 1408 return ret; 1409 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1410 fw_info.feature, fw_info.ver); 1411 1412 /* SDMA */ 1413 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1414 for (i = 0; i < adev->sdma.num_instances; i++) { 1415 query_fw.index = i; 1416 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1417 if (ret) 1418 return ret; 1419 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1420 i, fw_info.feature, fw_info.ver); 1421 } 1422 1423 /* VCN */ 1424 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1425 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1426 if (ret) 1427 return ret; 1428 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1429 fw_info.feature, fw_info.ver); 1430 1431 /* DMCU */ 1432 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1433 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1434 if (ret) 1435 return ret; 1436 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1437 fw_info.feature, fw_info.ver); 1438 1439 /* DMCUB */ 1440 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1441 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1442 if (ret) 1443 return ret; 1444 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1445 fw_info.feature, fw_info.ver); 1446 1447 1448 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1449 1450 return 0; 1451 } 1452 1453 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1454 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1455 }; 1456 #endif 1457 1458 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1459 { 1460 #if defined(CONFIG_DEBUG_FS) 1461 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1462 ARRAY_SIZE(amdgpu_firmware_info_list)); 1463 #else 1464 return 0; 1465 #endif 1466 } 1467