1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_sched.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 35 #include <linux/vga_switcheroo.h> 36 #include <linux/slab.h> 37 #include <linux/pm_runtime.h> 38 #include "amdgpu_amdkfd.h" 39 40 /** 41 * amdgpu_driver_unload_kms - Main unload function for KMS. 42 * 43 * @dev: drm dev pointer 44 * 45 * This is the main unload function for KMS (all asics). 46 * Returns 0 on success. 47 */ 48 void amdgpu_driver_unload_kms(struct drm_device *dev) 49 { 50 struct amdgpu_device *adev = dev->dev_private; 51 52 if (adev == NULL) 53 return; 54 55 if (adev->rmmio == NULL) 56 goto done_free; 57 58 if (amdgpu_sriov_vf(adev)) 59 amdgpu_virt_request_full_gpu(adev, false); 60 61 if (amdgpu_device_is_px(dev)) { 62 pm_runtime_get_sync(dev->dev); 63 pm_runtime_forbid(dev->dev); 64 } 65 66 amdgpu_acpi_fini(adev); 67 68 amdgpu_device_fini(adev); 69 70 done_free: 71 kfree(adev); 72 dev->dev_private = NULL; 73 } 74 75 /** 76 * amdgpu_driver_load_kms - Main load function for KMS. 77 * 78 * @dev: drm dev pointer 79 * @flags: device flags 80 * 81 * This is the main load function for KMS (all asics). 82 * Returns 0 on success, error on failure. 83 */ 84 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 85 { 86 struct amdgpu_device *adev; 87 int r, acpi_status; 88 89 #ifdef CONFIG_DRM_AMDGPU_SI 90 if (!amdgpu_si_support) { 91 switch (flags & AMD_ASIC_MASK) { 92 case CHIP_TAHITI: 93 case CHIP_PITCAIRN: 94 case CHIP_VERDE: 95 case CHIP_OLAND: 96 case CHIP_HAINAN: 97 dev_info(dev->dev, 98 "SI support provided by radeon.\n"); 99 dev_info(dev->dev, 100 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 101 ); 102 return -ENODEV; 103 } 104 } 105 #endif 106 #ifdef CONFIG_DRM_AMDGPU_CIK 107 if (!amdgpu_cik_support) { 108 switch (flags & AMD_ASIC_MASK) { 109 case CHIP_KAVERI: 110 case CHIP_BONAIRE: 111 case CHIP_HAWAII: 112 case CHIP_KABINI: 113 case CHIP_MULLINS: 114 dev_info(dev->dev, 115 "CIK support provided by radeon.\n"); 116 dev_info(dev->dev, 117 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 118 ); 119 return -ENODEV; 120 } 121 } 122 #endif 123 124 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 125 if (adev == NULL) { 126 return -ENOMEM; 127 } 128 dev->dev_private = (void *)adev; 129 130 if ((amdgpu_runtime_pm != 0) && 131 amdgpu_has_atpx() && 132 (amdgpu_is_atpx_hybrid() || 133 amdgpu_has_atpx_dgpu_power_cntl()) && 134 ((flags & AMD_IS_APU) == 0) && 135 !pci_is_thunderbolt_attached(dev->pdev)) 136 flags |= AMD_IS_PX; 137 138 /* amdgpu_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 145 if (r) { 146 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 /* Call ACPI methods: require modeset init 151 * but failure is not fatal 152 */ 153 if (!r) { 154 acpi_status = amdgpu_acpi_init(adev); 155 if (acpi_status) 156 dev_dbg(&dev->pdev->dev, 157 "Error during ACPI methods call\n"); 158 } 159 160 if (amdgpu_device_is_px(dev)) { 161 pm_runtime_use_autosuspend(dev->dev); 162 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 163 pm_runtime_set_active(dev->dev); 164 pm_runtime_allow(dev->dev); 165 pm_runtime_mark_last_busy(dev->dev); 166 pm_runtime_put_autosuspend(dev->dev); 167 } 168 169 out: 170 if (r) { 171 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 172 if (adev->rmmio && amdgpu_device_is_px(dev)) 173 pm_runtime_put_noidle(dev->dev); 174 amdgpu_driver_unload_kms(dev); 175 } 176 177 return r; 178 } 179 180 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 181 struct drm_amdgpu_query_fw *query_fw, 182 struct amdgpu_device *adev) 183 { 184 switch (query_fw->fw_type) { 185 case AMDGPU_INFO_FW_VCE: 186 fw_info->ver = adev->vce.fw_version; 187 fw_info->feature = adev->vce.fb_version; 188 break; 189 case AMDGPU_INFO_FW_UVD: 190 fw_info->ver = adev->uvd.fw_version; 191 fw_info->feature = 0; 192 break; 193 case AMDGPU_INFO_FW_VCN: 194 fw_info->ver = adev->vcn.fw_version; 195 fw_info->feature = 0; 196 break; 197 case AMDGPU_INFO_FW_GMC: 198 fw_info->ver = adev->gmc.fw_version; 199 fw_info->feature = 0; 200 break; 201 case AMDGPU_INFO_FW_GFX_ME: 202 fw_info->ver = adev->gfx.me_fw_version; 203 fw_info->feature = adev->gfx.me_feature_version; 204 break; 205 case AMDGPU_INFO_FW_GFX_PFP: 206 fw_info->ver = adev->gfx.pfp_fw_version; 207 fw_info->feature = adev->gfx.pfp_feature_version; 208 break; 209 case AMDGPU_INFO_FW_GFX_CE: 210 fw_info->ver = adev->gfx.ce_fw_version; 211 fw_info->feature = adev->gfx.ce_feature_version; 212 break; 213 case AMDGPU_INFO_FW_GFX_RLC: 214 fw_info->ver = adev->gfx.rlc_fw_version; 215 fw_info->feature = adev->gfx.rlc_feature_version; 216 break; 217 case AMDGPU_INFO_FW_GFX_MEC: 218 if (query_fw->index == 0) { 219 fw_info->ver = adev->gfx.mec_fw_version; 220 fw_info->feature = adev->gfx.mec_feature_version; 221 } else if (query_fw->index == 1) { 222 fw_info->ver = adev->gfx.mec2_fw_version; 223 fw_info->feature = adev->gfx.mec2_feature_version; 224 } else 225 return -EINVAL; 226 break; 227 case AMDGPU_INFO_FW_SMC: 228 fw_info->ver = adev->pm.fw_version; 229 fw_info->feature = 0; 230 break; 231 case AMDGPU_INFO_FW_SDMA: 232 if (query_fw->index >= adev->sdma.num_instances) 233 return -EINVAL; 234 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 235 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 236 break; 237 case AMDGPU_INFO_FW_SOS: 238 fw_info->ver = adev->psp.sos_fw_version; 239 fw_info->feature = adev->psp.sos_feature_version; 240 break; 241 case AMDGPU_INFO_FW_ASD: 242 fw_info->ver = adev->psp.asd_fw_version; 243 fw_info->feature = adev->psp.asd_feature_version; 244 break; 245 default: 246 return -EINVAL; 247 } 248 return 0; 249 } 250 251 /* 252 * Userspace get information ioctl 253 */ 254 /** 255 * amdgpu_info_ioctl - answer a device specific request. 256 * 257 * @adev: amdgpu device pointer 258 * @data: request object 259 * @filp: drm filp 260 * 261 * This function is used to pass device specific parameters to the userspace 262 * drivers. Examples include: pci device id, pipeline parms, tiling params, 263 * etc. (all asics). 264 * Returns 0 on success, -EINVAL on failure. 265 */ 266 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 267 { 268 struct amdgpu_device *adev = dev->dev_private; 269 struct drm_amdgpu_info *info = data; 270 struct amdgpu_mode_info *minfo = &adev->mode_info; 271 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 272 uint32_t size = info->return_size; 273 struct drm_crtc *crtc; 274 uint32_t ui32 = 0; 275 uint64_t ui64 = 0; 276 int i, found; 277 int ui32_size = sizeof(ui32); 278 279 if (!info->return_size || !info->return_pointer) 280 return -EINVAL; 281 282 switch (info->query) { 283 case AMDGPU_INFO_ACCEL_WORKING: 284 ui32 = adev->accel_working; 285 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 286 case AMDGPU_INFO_CRTC_FROM_ID: 287 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 288 crtc = (struct drm_crtc *)minfo->crtcs[i]; 289 if (crtc && crtc->base.id == info->mode_crtc.id) { 290 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 291 ui32 = amdgpu_crtc->crtc_id; 292 found = 1; 293 break; 294 } 295 } 296 if (!found) { 297 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 298 return -EINVAL; 299 } 300 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 301 case AMDGPU_INFO_HW_IP_INFO: { 302 struct drm_amdgpu_info_hw_ip ip = {}; 303 enum amd_ip_block_type type; 304 uint32_t ring_mask = 0; 305 uint32_t ib_start_alignment = 0; 306 uint32_t ib_size_alignment = 0; 307 308 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 309 return -EINVAL; 310 311 switch (info->query_hw_ip.type) { 312 case AMDGPU_HW_IP_GFX: 313 type = AMD_IP_BLOCK_TYPE_GFX; 314 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 315 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 316 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 317 ib_size_alignment = 8; 318 break; 319 case AMDGPU_HW_IP_COMPUTE: 320 type = AMD_IP_BLOCK_TYPE_GFX; 321 for (i = 0; i < adev->gfx.num_compute_rings; i++) 322 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 323 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 324 ib_size_alignment = 8; 325 break; 326 case AMDGPU_HW_IP_DMA: 327 type = AMD_IP_BLOCK_TYPE_SDMA; 328 for (i = 0; i < adev->sdma.num_instances; i++) 329 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 330 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 331 ib_size_alignment = 1; 332 break; 333 case AMDGPU_HW_IP_UVD: 334 type = AMD_IP_BLOCK_TYPE_UVD; 335 ring_mask = adev->uvd.ring.ready ? 1 : 0; 336 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 337 ib_size_alignment = 16; 338 break; 339 case AMDGPU_HW_IP_VCE: 340 type = AMD_IP_BLOCK_TYPE_VCE; 341 for (i = 0; i < adev->vce.num_rings; i++) 342 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 343 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 344 ib_size_alignment = 1; 345 break; 346 case AMDGPU_HW_IP_UVD_ENC: 347 type = AMD_IP_BLOCK_TYPE_UVD; 348 for (i = 0; i < adev->uvd.num_enc_rings; i++) 349 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 350 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 351 ib_size_alignment = 1; 352 break; 353 case AMDGPU_HW_IP_VCN_DEC: 354 type = AMD_IP_BLOCK_TYPE_VCN; 355 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 356 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 357 ib_size_alignment = 16; 358 break; 359 case AMDGPU_HW_IP_VCN_ENC: 360 type = AMD_IP_BLOCK_TYPE_VCN; 361 for (i = 0; i < adev->vcn.num_enc_rings; i++) 362 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 363 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 364 ib_size_alignment = 1; 365 break; 366 default: 367 return -EINVAL; 368 } 369 370 for (i = 0; i < adev->num_ip_blocks; i++) { 371 if (adev->ip_blocks[i].version->type == type && 372 adev->ip_blocks[i].status.valid) { 373 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 374 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 375 ip.capabilities_flags = 0; 376 ip.available_rings = ring_mask; 377 ip.ib_start_alignment = ib_start_alignment; 378 ip.ib_size_alignment = ib_size_alignment; 379 break; 380 } 381 } 382 return copy_to_user(out, &ip, 383 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 384 } 385 case AMDGPU_INFO_HW_IP_COUNT: { 386 enum amd_ip_block_type type; 387 uint32_t count = 0; 388 389 switch (info->query_hw_ip.type) { 390 case AMDGPU_HW_IP_GFX: 391 type = AMD_IP_BLOCK_TYPE_GFX; 392 break; 393 case AMDGPU_HW_IP_COMPUTE: 394 type = AMD_IP_BLOCK_TYPE_GFX; 395 break; 396 case AMDGPU_HW_IP_DMA: 397 type = AMD_IP_BLOCK_TYPE_SDMA; 398 break; 399 case AMDGPU_HW_IP_UVD: 400 type = AMD_IP_BLOCK_TYPE_UVD; 401 break; 402 case AMDGPU_HW_IP_VCE: 403 type = AMD_IP_BLOCK_TYPE_VCE; 404 break; 405 case AMDGPU_HW_IP_UVD_ENC: 406 type = AMD_IP_BLOCK_TYPE_UVD; 407 break; 408 case AMDGPU_HW_IP_VCN_DEC: 409 case AMDGPU_HW_IP_VCN_ENC: 410 type = AMD_IP_BLOCK_TYPE_VCN; 411 break; 412 default: 413 return -EINVAL; 414 } 415 416 for (i = 0; i < adev->num_ip_blocks; i++) 417 if (adev->ip_blocks[i].version->type == type && 418 adev->ip_blocks[i].status.valid && 419 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 420 count++; 421 422 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 423 } 424 case AMDGPU_INFO_TIMESTAMP: 425 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 426 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 427 case AMDGPU_INFO_FW_VERSION: { 428 struct drm_amdgpu_info_firmware fw_info; 429 int ret; 430 431 /* We only support one instance of each IP block right now. */ 432 if (info->query_fw.ip_instance != 0) 433 return -EINVAL; 434 435 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 436 if (ret) 437 return ret; 438 439 return copy_to_user(out, &fw_info, 440 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 441 } 442 case AMDGPU_INFO_NUM_BYTES_MOVED: 443 ui64 = atomic64_read(&adev->num_bytes_moved); 444 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 445 case AMDGPU_INFO_NUM_EVICTIONS: 446 ui64 = atomic64_read(&adev->num_evictions); 447 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 448 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 449 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 450 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 451 case AMDGPU_INFO_VRAM_USAGE: 452 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 453 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 454 case AMDGPU_INFO_VIS_VRAM_USAGE: 455 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 456 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 457 case AMDGPU_INFO_GTT_USAGE: 458 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 459 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 460 case AMDGPU_INFO_GDS_CONFIG: { 461 struct drm_amdgpu_info_gds gds_info; 462 463 memset(&gds_info, 0, sizeof(gds_info)); 464 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 465 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 466 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 467 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 468 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 469 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 470 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 471 return copy_to_user(out, &gds_info, 472 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 473 } 474 case AMDGPU_INFO_VRAM_GTT: { 475 struct drm_amdgpu_info_vram_gtt vram_gtt; 476 477 vram_gtt.vram_size = adev->gmc.real_vram_size; 478 vram_gtt.vram_size -= adev->vram_pin_size; 479 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size; 480 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 481 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 482 vram_gtt.gtt_size *= PAGE_SIZE; 483 vram_gtt.gtt_size -= adev->gart_pin_size; 484 return copy_to_user(out, &vram_gtt, 485 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 486 } 487 case AMDGPU_INFO_MEMORY: { 488 struct drm_amdgpu_memory_info mem; 489 490 memset(&mem, 0, sizeof(mem)); 491 mem.vram.total_heap_size = adev->gmc.real_vram_size; 492 mem.vram.usable_heap_size = 493 adev->gmc.real_vram_size - adev->vram_pin_size; 494 mem.vram.heap_usage = 495 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 496 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 497 498 mem.cpu_accessible_vram.total_heap_size = 499 adev->gmc.visible_vram_size; 500 mem.cpu_accessible_vram.usable_heap_size = 501 adev->gmc.visible_vram_size - 502 (adev->vram_pin_size - adev->invisible_pin_size); 503 mem.cpu_accessible_vram.heap_usage = 504 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 505 mem.cpu_accessible_vram.max_allocation = 506 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 507 508 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 509 mem.gtt.total_heap_size *= PAGE_SIZE; 510 mem.gtt.usable_heap_size = mem.gtt.total_heap_size 511 - adev->gart_pin_size; 512 mem.gtt.heap_usage = 513 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 514 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 515 516 return copy_to_user(out, &mem, 517 min((size_t)size, sizeof(mem))) 518 ? -EFAULT : 0; 519 } 520 case AMDGPU_INFO_READ_MMR_REG: { 521 unsigned n, alloc_size; 522 uint32_t *regs; 523 unsigned se_num = (info->read_mmr_reg.instance >> 524 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 525 AMDGPU_INFO_MMR_SE_INDEX_MASK; 526 unsigned sh_num = (info->read_mmr_reg.instance >> 527 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 528 AMDGPU_INFO_MMR_SH_INDEX_MASK; 529 530 /* set full masks if the userspace set all bits 531 * in the bitfields */ 532 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 533 se_num = 0xffffffff; 534 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 535 sh_num = 0xffffffff; 536 537 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 538 if (!regs) 539 return -ENOMEM; 540 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 541 542 for (i = 0; i < info->read_mmr_reg.count; i++) 543 if (amdgpu_asic_read_register(adev, se_num, sh_num, 544 info->read_mmr_reg.dword_offset + i, 545 ®s[i])) { 546 DRM_DEBUG_KMS("unallowed offset %#x\n", 547 info->read_mmr_reg.dword_offset + i); 548 kfree(regs); 549 return -EFAULT; 550 } 551 n = copy_to_user(out, regs, min(size, alloc_size)); 552 kfree(regs); 553 return n ? -EFAULT : 0; 554 } 555 case AMDGPU_INFO_DEV_INFO: { 556 struct drm_amdgpu_info_device dev_info = {}; 557 uint64_t vm_size; 558 559 dev_info.device_id = dev->pdev->device; 560 dev_info.chip_rev = adev->rev_id; 561 dev_info.external_rev = adev->external_rev_id; 562 dev_info.pci_rev = dev->pdev->revision; 563 dev_info.family = adev->family; 564 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 565 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 566 /* return all clocks in KHz */ 567 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 568 if (adev->pm.dpm_enabled) { 569 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 570 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 571 } else { 572 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 573 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 574 } 575 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 576 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 577 adev->gfx.config.max_shader_engines; 578 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 579 dev_info._pad = 0; 580 dev_info.ids_flags = 0; 581 if (adev->flags & AMD_IS_APU) 582 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 583 if (amdgpu_sriov_vf(adev)) 584 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 585 586 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 587 vm_size -= AMDGPU_VA_RESERVED_SIZE; 588 589 /* Older VCE FW versions are buggy and can handle only 40bits */ 590 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 591 vm_size = min(vm_size, 1ULL << 40); 592 593 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 594 dev_info.virtual_address_max = 595 min(vm_size, AMDGPU_VA_HOLE_START); 596 597 if (vm_size > AMDGPU_VA_HOLE_START) { 598 dev_info.high_va_offset = AMDGPU_VA_HOLE_END; 599 dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; 600 } 601 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 602 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 603 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 604 dev_info.cu_active_number = adev->gfx.cu_info.number; 605 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 606 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 607 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 608 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 609 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 610 sizeof(adev->gfx.cu_info.bitmap)); 611 dev_info.vram_type = adev->gmc.vram_type; 612 dev_info.vram_bit_width = adev->gmc.vram_width; 613 dev_info.vce_harvest_config = adev->vce.harvest_config; 614 dev_info.gc_double_offchip_lds_buf = 615 adev->gfx.config.double_offchip_lds_buf; 616 617 if (amdgpu_ngg) { 618 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 619 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 620 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 621 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 622 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 623 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 624 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 625 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 626 } 627 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 628 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 629 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 630 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 631 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 632 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 633 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 634 635 return copy_to_user(out, &dev_info, 636 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 637 } 638 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 639 unsigned i; 640 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 641 struct amd_vce_state *vce_state; 642 643 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 644 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 645 if (vce_state) { 646 vce_clk_table.entries[i].sclk = vce_state->sclk; 647 vce_clk_table.entries[i].mclk = vce_state->mclk; 648 vce_clk_table.entries[i].eclk = vce_state->evclk; 649 vce_clk_table.num_valid_entries++; 650 } 651 } 652 653 return copy_to_user(out, &vce_clk_table, 654 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 655 } 656 case AMDGPU_INFO_VBIOS: { 657 uint32_t bios_size = adev->bios_size; 658 659 switch (info->vbios_info.type) { 660 case AMDGPU_INFO_VBIOS_SIZE: 661 return copy_to_user(out, &bios_size, 662 min((size_t)size, sizeof(bios_size))) 663 ? -EFAULT : 0; 664 case AMDGPU_INFO_VBIOS_IMAGE: { 665 uint8_t *bios; 666 uint32_t bios_offset = info->vbios_info.offset; 667 668 if (bios_offset >= bios_size) 669 return -EINVAL; 670 671 bios = adev->bios + bios_offset; 672 return copy_to_user(out, bios, 673 min((size_t)size, (size_t)(bios_size - bios_offset))) 674 ? -EFAULT : 0; 675 } 676 default: 677 DRM_DEBUG_KMS("Invalid request %d\n", 678 info->vbios_info.type); 679 return -EINVAL; 680 } 681 } 682 case AMDGPU_INFO_NUM_HANDLES: { 683 struct drm_amdgpu_info_num_handles handle; 684 685 switch (info->query_hw_ip.type) { 686 case AMDGPU_HW_IP_UVD: 687 /* Starting Polaris, we support unlimited UVD handles */ 688 if (adev->asic_type < CHIP_POLARIS10) { 689 handle.uvd_max_handles = adev->uvd.max_handles; 690 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 691 692 return copy_to_user(out, &handle, 693 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 694 } else { 695 return -ENODATA; 696 } 697 698 break; 699 default: 700 return -EINVAL; 701 } 702 } 703 case AMDGPU_INFO_SENSOR: { 704 struct pp_gpu_power query = {0}; 705 int query_size = sizeof(query); 706 707 if (amdgpu_dpm == 0) 708 return -ENOENT; 709 710 switch (info->sensor_info.type) { 711 case AMDGPU_INFO_SENSOR_GFX_SCLK: 712 /* get sclk in Mhz */ 713 if (amdgpu_dpm_read_sensor(adev, 714 AMDGPU_PP_SENSOR_GFX_SCLK, 715 (void *)&ui32, &ui32_size)) { 716 return -EINVAL; 717 } 718 ui32 /= 100; 719 break; 720 case AMDGPU_INFO_SENSOR_GFX_MCLK: 721 /* get mclk in Mhz */ 722 if (amdgpu_dpm_read_sensor(adev, 723 AMDGPU_PP_SENSOR_GFX_MCLK, 724 (void *)&ui32, &ui32_size)) { 725 return -EINVAL; 726 } 727 ui32 /= 100; 728 break; 729 case AMDGPU_INFO_SENSOR_GPU_TEMP: 730 /* get temperature in millidegrees C */ 731 if (amdgpu_dpm_read_sensor(adev, 732 AMDGPU_PP_SENSOR_GPU_TEMP, 733 (void *)&ui32, &ui32_size)) { 734 return -EINVAL; 735 } 736 break; 737 case AMDGPU_INFO_SENSOR_GPU_LOAD: 738 /* get GPU load */ 739 if (amdgpu_dpm_read_sensor(adev, 740 AMDGPU_PP_SENSOR_GPU_LOAD, 741 (void *)&ui32, &ui32_size)) { 742 return -EINVAL; 743 } 744 break; 745 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 746 /* get average GPU power */ 747 if (amdgpu_dpm_read_sensor(adev, 748 AMDGPU_PP_SENSOR_GPU_POWER, 749 (void *)&query, &query_size)) { 750 return -EINVAL; 751 } 752 ui32 = query.average_gpu_power >> 8; 753 break; 754 case AMDGPU_INFO_SENSOR_VDDNB: 755 /* get VDDNB in millivolts */ 756 if (amdgpu_dpm_read_sensor(adev, 757 AMDGPU_PP_SENSOR_VDDNB, 758 (void *)&ui32, &ui32_size)) { 759 return -EINVAL; 760 } 761 break; 762 case AMDGPU_INFO_SENSOR_VDDGFX: 763 /* get VDDGFX in millivolts */ 764 if (amdgpu_dpm_read_sensor(adev, 765 AMDGPU_PP_SENSOR_VDDGFX, 766 (void *)&ui32, &ui32_size)) { 767 return -EINVAL; 768 } 769 break; 770 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 771 /* get stable pstate sclk in Mhz */ 772 if (amdgpu_dpm_read_sensor(adev, 773 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 774 (void *)&ui32, &ui32_size)) { 775 return -EINVAL; 776 } 777 ui32 /= 100; 778 break; 779 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 780 /* get stable pstate mclk in Mhz */ 781 if (amdgpu_dpm_read_sensor(adev, 782 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 783 (void *)&ui32, &ui32_size)) { 784 return -EINVAL; 785 } 786 ui32 /= 100; 787 break; 788 default: 789 DRM_DEBUG_KMS("Invalid request %d\n", 790 info->sensor_info.type); 791 return -EINVAL; 792 } 793 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 794 } 795 case AMDGPU_INFO_VRAM_LOST_COUNTER: 796 ui32 = atomic_read(&adev->vram_lost_counter); 797 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 798 default: 799 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 800 return -EINVAL; 801 } 802 return 0; 803 } 804 805 806 /* 807 * Outdated mess for old drm with Xorg being in charge (void function now). 808 */ 809 /** 810 * amdgpu_driver_lastclose_kms - drm callback for last close 811 * 812 * @dev: drm dev pointer 813 * 814 * Switch vga_switcheroo state after last close (all asics). 815 */ 816 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 817 { 818 drm_fb_helper_lastclose(dev); 819 vga_switcheroo_process_delayed_switch(); 820 } 821 822 /** 823 * amdgpu_driver_open_kms - drm callback for open 824 * 825 * @dev: drm dev pointer 826 * @file_priv: drm file 827 * 828 * On device open, init vm on cayman+ (all asics). 829 * Returns 0 on success, error on failure. 830 */ 831 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 832 { 833 struct amdgpu_device *adev = dev->dev_private; 834 struct amdgpu_fpriv *fpriv; 835 int r, pasid; 836 837 file_priv->driver_priv = NULL; 838 839 r = pm_runtime_get_sync(dev->dev); 840 if (r < 0) 841 return r; 842 843 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 844 if (unlikely(!fpriv)) { 845 r = -ENOMEM; 846 goto out_suspend; 847 } 848 849 pasid = amdgpu_pasid_alloc(16); 850 if (pasid < 0) { 851 dev_warn(adev->dev, "No more PASIDs available!"); 852 pasid = 0; 853 } 854 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 855 if (r) 856 goto error_pasid; 857 858 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 859 if (!fpriv->prt_va) { 860 r = -ENOMEM; 861 goto error_vm; 862 } 863 864 if (amdgpu_sriov_vf(adev)) { 865 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); 866 if (r) 867 goto error_vm; 868 } 869 870 mutex_init(&fpriv->bo_list_lock); 871 idr_init(&fpriv->bo_list_handles); 872 873 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 874 875 file_priv->driver_priv = fpriv; 876 goto out_suspend; 877 878 error_vm: 879 amdgpu_vm_fini(adev, &fpriv->vm); 880 881 error_pasid: 882 if (pasid) 883 amdgpu_pasid_free(pasid); 884 885 kfree(fpriv); 886 887 out_suspend: 888 pm_runtime_mark_last_busy(dev->dev); 889 pm_runtime_put_autosuspend(dev->dev); 890 891 return r; 892 } 893 894 /** 895 * amdgpu_driver_postclose_kms - drm callback for post close 896 * 897 * @dev: drm dev pointer 898 * @file_priv: drm file 899 * 900 * On device post close, tear down vm on cayman+ (all asics). 901 */ 902 void amdgpu_driver_postclose_kms(struct drm_device *dev, 903 struct drm_file *file_priv) 904 { 905 struct amdgpu_device *adev = dev->dev_private; 906 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 907 struct amdgpu_bo_list *list; 908 struct amdgpu_bo *pd; 909 unsigned int pasid; 910 int handle; 911 912 if (!fpriv) 913 return; 914 915 pm_runtime_get_sync(dev->dev); 916 917 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 918 919 if (adev->asic_type != CHIP_RAVEN) { 920 amdgpu_uvd_free_handles(adev, file_priv); 921 amdgpu_vce_free_handles(adev, file_priv); 922 } 923 924 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 925 926 if (amdgpu_sriov_vf(adev)) { 927 /* TODO: how to handle reserve failure */ 928 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 929 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 930 fpriv->csa_va = NULL; 931 amdgpu_bo_unreserve(adev->virt.csa_obj); 932 } 933 934 pasid = fpriv->vm.pasid; 935 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 936 937 amdgpu_vm_fini(adev, &fpriv->vm); 938 if (pasid) 939 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); 940 amdgpu_bo_unref(&pd); 941 942 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 943 amdgpu_bo_list_free(list); 944 945 idr_destroy(&fpriv->bo_list_handles); 946 mutex_destroy(&fpriv->bo_list_lock); 947 948 kfree(fpriv); 949 file_priv->driver_priv = NULL; 950 951 pm_runtime_mark_last_busy(dev->dev); 952 pm_runtime_put_autosuspend(dev->dev); 953 } 954 955 /* 956 * VBlank related functions. 957 */ 958 /** 959 * amdgpu_get_vblank_counter_kms - get frame count 960 * 961 * @dev: drm dev pointer 962 * @pipe: crtc to get the frame count from 963 * 964 * Gets the frame count on the requested crtc (all asics). 965 * Returns frame count on success, -EINVAL on failure. 966 */ 967 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 968 { 969 struct amdgpu_device *adev = dev->dev_private; 970 int vpos, hpos, stat; 971 u32 count; 972 973 if (pipe >= adev->mode_info.num_crtc) { 974 DRM_ERROR("Invalid crtc %u\n", pipe); 975 return -EINVAL; 976 } 977 978 /* The hw increments its frame counter at start of vsync, not at start 979 * of vblank, as is required by DRM core vblank counter handling. 980 * Cook the hw count here to make it appear to the caller as if it 981 * incremented at start of vblank. We measure distance to start of 982 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 983 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 984 * result by 1 to give the proper appearance to caller. 985 */ 986 if (adev->mode_info.crtcs[pipe]) { 987 /* Repeat readout if needed to provide stable result if 988 * we cross start of vsync during the queries. 989 */ 990 do { 991 count = amdgpu_display_vblank_get_counter(adev, pipe); 992 /* Ask amdgpu_display_get_crtc_scanoutpos to return 993 * vpos as distance to start of vblank, instead of 994 * regular vertical scanout pos. 995 */ 996 stat = amdgpu_display_get_crtc_scanoutpos( 997 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 998 &vpos, &hpos, NULL, NULL, 999 &adev->mode_info.crtcs[pipe]->base.hwmode); 1000 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1001 1002 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1003 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1004 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1005 } else { 1006 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1007 pipe, vpos); 1008 1009 /* Bump counter if we are at >= leading edge of vblank, 1010 * but before vsync where vpos would turn negative and 1011 * the hw counter really increments. 1012 */ 1013 if (vpos >= 0) 1014 count++; 1015 } 1016 } else { 1017 /* Fallback to use value as is. */ 1018 count = amdgpu_display_vblank_get_counter(adev, pipe); 1019 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1020 } 1021 1022 return count; 1023 } 1024 1025 /** 1026 * amdgpu_enable_vblank_kms - enable vblank interrupt 1027 * 1028 * @dev: drm dev pointer 1029 * @pipe: crtc to enable vblank interrupt for 1030 * 1031 * Enable the interrupt on the requested crtc (all asics). 1032 * Returns 0 on success, -EINVAL on failure. 1033 */ 1034 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1035 { 1036 struct amdgpu_device *adev = dev->dev_private; 1037 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1038 1039 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1040 } 1041 1042 /** 1043 * amdgpu_disable_vblank_kms - disable vblank interrupt 1044 * 1045 * @dev: drm dev pointer 1046 * @pipe: crtc to disable vblank interrupt for 1047 * 1048 * Disable the interrupt on the requested crtc (all asics). 1049 */ 1050 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1051 { 1052 struct amdgpu_device *adev = dev->dev_private; 1053 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1054 1055 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1056 } 1057 1058 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1059 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1060 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1061 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1062 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1063 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1064 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1065 /* KMS */ 1066 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1067 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1068 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1069 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1070 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1071 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1072 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1073 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1074 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1075 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1076 }; 1077 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1078 1079 /* 1080 * Debugfs info 1081 */ 1082 #if defined(CONFIG_DEBUG_FS) 1083 1084 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1085 { 1086 struct drm_info_node *node = (struct drm_info_node *) m->private; 1087 struct drm_device *dev = node->minor->dev; 1088 struct amdgpu_device *adev = dev->dev_private; 1089 struct drm_amdgpu_info_firmware fw_info; 1090 struct drm_amdgpu_query_fw query_fw; 1091 int ret, i; 1092 1093 /* VCE */ 1094 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1095 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1096 if (ret) 1097 return ret; 1098 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1099 fw_info.feature, fw_info.ver); 1100 1101 /* UVD */ 1102 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1103 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1104 if (ret) 1105 return ret; 1106 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1107 fw_info.feature, fw_info.ver); 1108 1109 /* GMC */ 1110 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1111 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1112 if (ret) 1113 return ret; 1114 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1115 fw_info.feature, fw_info.ver); 1116 1117 /* ME */ 1118 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1119 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1120 if (ret) 1121 return ret; 1122 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1123 fw_info.feature, fw_info.ver); 1124 1125 /* PFP */ 1126 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1127 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1128 if (ret) 1129 return ret; 1130 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1131 fw_info.feature, fw_info.ver); 1132 1133 /* CE */ 1134 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1135 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1136 if (ret) 1137 return ret; 1138 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1139 fw_info.feature, fw_info.ver); 1140 1141 /* RLC */ 1142 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1143 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1144 if (ret) 1145 return ret; 1146 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1147 fw_info.feature, fw_info.ver); 1148 1149 /* MEC */ 1150 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1151 query_fw.index = 0; 1152 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1153 if (ret) 1154 return ret; 1155 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1156 fw_info.feature, fw_info.ver); 1157 1158 /* MEC2 */ 1159 if (adev->asic_type == CHIP_KAVERI || 1160 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1161 query_fw.index = 1; 1162 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1163 if (ret) 1164 return ret; 1165 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1166 fw_info.feature, fw_info.ver); 1167 } 1168 1169 /* PSP SOS */ 1170 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1171 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1172 if (ret) 1173 return ret; 1174 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1175 fw_info.feature, fw_info.ver); 1176 1177 1178 /* PSP ASD */ 1179 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1180 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1181 if (ret) 1182 return ret; 1183 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1184 fw_info.feature, fw_info.ver); 1185 1186 /* SMC */ 1187 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1188 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1189 if (ret) 1190 return ret; 1191 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1192 fw_info.feature, fw_info.ver); 1193 1194 /* SDMA */ 1195 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1196 for (i = 0; i < adev->sdma.num_instances; i++) { 1197 query_fw.index = i; 1198 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1199 if (ret) 1200 return ret; 1201 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1202 i, fw_info.feature, fw_info.ver); 1203 } 1204 1205 /* VCN */ 1206 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1207 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1208 if (ret) 1209 return ret; 1210 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1211 fw_info.feature, fw_info.ver); 1212 1213 return 0; 1214 } 1215 1216 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1217 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1218 }; 1219 #endif 1220 1221 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1222 { 1223 #if defined(CONFIG_DEBUG_FS) 1224 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1225 ARRAY_SIZE(amdgpu_firmware_info_list)); 1226 #else 1227 return 0; 1228 #endif 1229 } 1230