1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (amdgpu_sriov_vf(adev)) 92 amdgpu_virt_request_full_gpu(adev, false); 93 94 if (amdgpu_device_is_px(dev)) { 95 pm_runtime_get_sync(dev->dev); 96 pm_runtime_forbid(dev->dev); 97 } 98 99 amdgpu_acpi_fini(adev); 100 101 amdgpu_device_fini(adev); 102 103 done_free: 104 kfree(adev); 105 dev->dev_private = NULL; 106 } 107 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 109 { 110 struct amdgpu_gpu_instance *gpu_instance; 111 112 mutex_lock(&mgpu_info.mutex); 113 114 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 115 DRM_ERROR("Cannot register more gpu instance\n"); 116 mutex_unlock(&mgpu_info.mutex); 117 return; 118 } 119 120 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 121 gpu_instance->adev = adev; 122 gpu_instance->mgpu_fan_enabled = 0; 123 124 mgpu_info.num_gpu++; 125 if (adev->flags & AMD_IS_APU) 126 mgpu_info.num_apu++; 127 else 128 mgpu_info.num_dgpu++; 129 130 mutex_unlock(&mgpu_info.mutex); 131 } 132 133 /** 134 * amdgpu_driver_load_kms - Main load function for KMS. 135 * 136 * @dev: drm dev pointer 137 * @flags: device flags 138 * 139 * This is the main load function for KMS (all asics). 140 * Returns 0 on success, error on failure. 141 */ 142 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 143 { 144 struct amdgpu_device *adev; 145 int r, acpi_status; 146 147 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 148 if (adev == NULL) { 149 return -ENOMEM; 150 } 151 dev->dev_private = (void *)adev; 152 153 if ((amdgpu_runtime_pm != 0) && 154 amdgpu_has_atpx() && 155 (amdgpu_is_atpx_hybrid() || 156 amdgpu_has_atpx_dgpu_power_cntl()) && 157 ((flags & AMD_IS_APU) == 0) && 158 !pci_is_thunderbolt_attached(dev->pdev)) 159 flags |= AMD_IS_PX; 160 161 /* amdgpu_device_init should report only fatal error 162 * like memory allocation failure or iomapping failure, 163 * or memory manager initialization failure, it must 164 * properly initialize the GPU MC controller and permit 165 * VRAM allocation 166 */ 167 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 168 if (r) { 169 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 170 goto out; 171 } 172 173 /* Call ACPI methods: require modeset init 174 * but failure is not fatal 175 */ 176 if (!r) { 177 acpi_status = amdgpu_acpi_init(adev); 178 if (acpi_status) 179 dev_dbg(&dev->pdev->dev, 180 "Error during ACPI methods call\n"); 181 } 182 183 if (amdgpu_device_is_px(dev)) { 184 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); 185 pm_runtime_use_autosuspend(dev->dev); 186 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 187 pm_runtime_set_active(dev->dev); 188 pm_runtime_allow(dev->dev); 189 pm_runtime_mark_last_busy(dev->dev); 190 pm_runtime_put_autosuspend(dev->dev); 191 } 192 193 amdgpu_register_gpu_instance(adev); 194 out: 195 if (r) { 196 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 197 if (adev->rmmio && amdgpu_device_is_px(dev)) 198 pm_runtime_put_noidle(dev->dev); 199 amdgpu_driver_unload_kms(dev); 200 } 201 202 return r; 203 } 204 205 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 206 struct drm_amdgpu_query_fw *query_fw, 207 struct amdgpu_device *adev) 208 { 209 switch (query_fw->fw_type) { 210 case AMDGPU_INFO_FW_VCE: 211 fw_info->ver = adev->vce.fw_version; 212 fw_info->feature = adev->vce.fb_version; 213 break; 214 case AMDGPU_INFO_FW_UVD: 215 fw_info->ver = adev->uvd.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_VCN: 219 fw_info->ver = adev->vcn.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GMC: 223 fw_info->ver = adev->gmc.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_GFX_ME: 227 fw_info->ver = adev->gfx.me_fw_version; 228 fw_info->feature = adev->gfx.me_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_PFP: 231 fw_info->ver = adev->gfx.pfp_fw_version; 232 fw_info->feature = adev->gfx.pfp_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_CE: 235 fw_info->ver = adev->gfx.ce_fw_version; 236 fw_info->feature = adev->gfx.ce_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC: 239 fw_info->ver = adev->gfx.rlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 243 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 247 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 248 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 251 fw_info->ver = adev->gfx.rlc_srls_fw_version; 252 fw_info->feature = adev->gfx.rlc_srls_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_MEC: 255 if (query_fw->index == 0) { 256 fw_info->ver = adev->gfx.mec_fw_version; 257 fw_info->feature = adev->gfx.mec_feature_version; 258 } else if (query_fw->index == 1) { 259 fw_info->ver = adev->gfx.mec2_fw_version; 260 fw_info->feature = adev->gfx.mec2_feature_version; 261 } else 262 return -EINVAL; 263 break; 264 case AMDGPU_INFO_FW_SMC: 265 fw_info->ver = adev->pm.fw_version; 266 fw_info->feature = 0; 267 break; 268 case AMDGPU_INFO_FW_TA: 269 if (query_fw->index > 1) 270 return -EINVAL; 271 if (query_fw->index == 0) { 272 fw_info->ver = adev->psp.ta_fw_version; 273 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 274 } else { 275 fw_info->ver = adev->psp.ta_fw_version; 276 fw_info->feature = adev->psp.ta_ras_ucode_version; 277 } 278 break; 279 case AMDGPU_INFO_FW_SDMA: 280 if (query_fw->index >= adev->sdma.num_instances) 281 return -EINVAL; 282 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 283 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 284 break; 285 case AMDGPU_INFO_FW_SOS: 286 fw_info->ver = adev->psp.sos_fw_version; 287 fw_info->feature = adev->psp.sos_feature_version; 288 break; 289 case AMDGPU_INFO_FW_ASD: 290 fw_info->ver = adev->psp.asd_fw_version; 291 fw_info->feature = adev->psp.asd_feature_version; 292 break; 293 case AMDGPU_INFO_FW_DMCU: 294 fw_info->ver = adev->dm.dmcu_fw_version; 295 fw_info->feature = 0; 296 break; 297 default: 298 return -EINVAL; 299 } 300 return 0; 301 } 302 303 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 304 struct drm_amdgpu_info *info, 305 struct drm_amdgpu_info_hw_ip *result) 306 { 307 uint32_t ib_start_alignment = 0; 308 uint32_t ib_size_alignment = 0; 309 enum amd_ip_block_type type; 310 unsigned int num_rings = 0; 311 unsigned int i, j; 312 313 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 314 return -EINVAL; 315 316 switch (info->query_hw_ip.type) { 317 case AMDGPU_HW_IP_GFX: 318 type = AMD_IP_BLOCK_TYPE_GFX; 319 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 320 if (adev->gfx.gfx_ring[i].sched.ready) 321 ++num_rings; 322 ib_start_alignment = 32; 323 ib_size_alignment = 32; 324 break; 325 case AMDGPU_HW_IP_COMPUTE: 326 type = AMD_IP_BLOCK_TYPE_GFX; 327 for (i = 0; i < adev->gfx.num_compute_rings; i++) 328 if (adev->gfx.compute_ring[i].sched.ready) 329 ++num_rings; 330 ib_start_alignment = 32; 331 ib_size_alignment = 32; 332 break; 333 case AMDGPU_HW_IP_DMA: 334 type = AMD_IP_BLOCK_TYPE_SDMA; 335 for (i = 0; i < adev->sdma.num_instances; i++) 336 if (adev->sdma.instance[i].ring.sched.ready) 337 ++num_rings; 338 ib_start_alignment = 256; 339 ib_size_alignment = 4; 340 break; 341 case AMDGPU_HW_IP_UVD: 342 type = AMD_IP_BLOCK_TYPE_UVD; 343 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 344 if (adev->uvd.harvest_config & (1 << i)) 345 continue; 346 347 if (adev->uvd.inst[i].ring.sched.ready) 348 ++num_rings; 349 } 350 ib_start_alignment = 64; 351 ib_size_alignment = 64; 352 break; 353 case AMDGPU_HW_IP_VCE: 354 type = AMD_IP_BLOCK_TYPE_VCE; 355 for (i = 0; i < adev->vce.num_rings; i++) 356 if (adev->vce.ring[i].sched.ready) 357 ++num_rings; 358 ib_start_alignment = 4; 359 ib_size_alignment = 1; 360 break; 361 case AMDGPU_HW_IP_UVD_ENC: 362 type = AMD_IP_BLOCK_TYPE_UVD; 363 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 364 if (adev->uvd.harvest_config & (1 << i)) 365 continue; 366 367 for (j = 0; j < adev->uvd.num_enc_rings; j++) 368 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 369 ++num_rings; 370 } 371 ib_start_alignment = 64; 372 ib_size_alignment = 64; 373 break; 374 case AMDGPU_HW_IP_VCN_DEC: 375 type = AMD_IP_BLOCK_TYPE_VCN; 376 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 377 if (adev->uvd.harvest_config & (1 << i)) 378 continue; 379 380 if (adev->vcn.inst[i].ring_dec.sched.ready) 381 ++num_rings; 382 } 383 ib_start_alignment = 16; 384 ib_size_alignment = 16; 385 break; 386 case AMDGPU_HW_IP_VCN_ENC: 387 type = AMD_IP_BLOCK_TYPE_VCN; 388 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 389 if (adev->uvd.harvest_config & (1 << i)) 390 continue; 391 392 for (j = 0; j < adev->vcn.num_enc_rings; j++) 393 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 394 ++num_rings; 395 } 396 ib_start_alignment = 64; 397 ib_size_alignment = 1; 398 break; 399 case AMDGPU_HW_IP_VCN_JPEG: 400 type = AMD_IP_BLOCK_TYPE_VCN; 401 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 402 if (adev->uvd.harvest_config & (1 << i)) 403 continue; 404 405 if (adev->vcn.inst[i].ring_jpeg.sched.ready) 406 ++num_rings; 407 } 408 ib_start_alignment = 16; 409 ib_size_alignment = 16; 410 break; 411 default: 412 return -EINVAL; 413 } 414 415 for (i = 0; i < adev->num_ip_blocks; i++) 416 if (adev->ip_blocks[i].version->type == type && 417 adev->ip_blocks[i].status.valid) 418 break; 419 420 if (i == adev->num_ip_blocks) 421 return 0; 422 423 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 424 num_rings); 425 426 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 427 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 428 result->capabilities_flags = 0; 429 result->available_rings = (1 << num_rings) - 1; 430 result->ib_start_alignment = ib_start_alignment; 431 result->ib_size_alignment = ib_size_alignment; 432 return 0; 433 } 434 435 /* 436 * Userspace get information ioctl 437 */ 438 /** 439 * amdgpu_info_ioctl - answer a device specific request. 440 * 441 * @adev: amdgpu device pointer 442 * @data: request object 443 * @filp: drm filp 444 * 445 * This function is used to pass device specific parameters to the userspace 446 * drivers. Examples include: pci device id, pipeline parms, tiling params, 447 * etc. (all asics). 448 * Returns 0 on success, -EINVAL on failure. 449 */ 450 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 451 { 452 struct amdgpu_device *adev = dev->dev_private; 453 struct drm_amdgpu_info *info = data; 454 struct amdgpu_mode_info *minfo = &adev->mode_info; 455 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 456 uint32_t size = info->return_size; 457 struct drm_crtc *crtc; 458 uint32_t ui32 = 0; 459 uint64_t ui64 = 0; 460 int i, found; 461 int ui32_size = sizeof(ui32); 462 463 if (!info->return_size || !info->return_pointer) 464 return -EINVAL; 465 466 switch (info->query) { 467 case AMDGPU_INFO_ACCEL_WORKING: 468 ui32 = adev->accel_working; 469 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 470 case AMDGPU_INFO_CRTC_FROM_ID: 471 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 472 crtc = (struct drm_crtc *)minfo->crtcs[i]; 473 if (crtc && crtc->base.id == info->mode_crtc.id) { 474 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 475 ui32 = amdgpu_crtc->crtc_id; 476 found = 1; 477 break; 478 } 479 } 480 if (!found) { 481 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 482 return -EINVAL; 483 } 484 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 485 case AMDGPU_INFO_HW_IP_INFO: { 486 struct drm_amdgpu_info_hw_ip ip = {}; 487 int ret; 488 489 ret = amdgpu_hw_ip_info(adev, info, &ip); 490 if (ret) 491 return ret; 492 493 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 494 return ret ? -EFAULT : 0; 495 } 496 case AMDGPU_INFO_HW_IP_COUNT: { 497 enum amd_ip_block_type type; 498 uint32_t count = 0; 499 500 switch (info->query_hw_ip.type) { 501 case AMDGPU_HW_IP_GFX: 502 type = AMD_IP_BLOCK_TYPE_GFX; 503 break; 504 case AMDGPU_HW_IP_COMPUTE: 505 type = AMD_IP_BLOCK_TYPE_GFX; 506 break; 507 case AMDGPU_HW_IP_DMA: 508 type = AMD_IP_BLOCK_TYPE_SDMA; 509 break; 510 case AMDGPU_HW_IP_UVD: 511 type = AMD_IP_BLOCK_TYPE_UVD; 512 break; 513 case AMDGPU_HW_IP_VCE: 514 type = AMD_IP_BLOCK_TYPE_VCE; 515 break; 516 case AMDGPU_HW_IP_UVD_ENC: 517 type = AMD_IP_BLOCK_TYPE_UVD; 518 break; 519 case AMDGPU_HW_IP_VCN_DEC: 520 case AMDGPU_HW_IP_VCN_ENC: 521 case AMDGPU_HW_IP_VCN_JPEG: 522 type = AMD_IP_BLOCK_TYPE_VCN; 523 break; 524 default: 525 return -EINVAL; 526 } 527 528 for (i = 0; i < adev->num_ip_blocks; i++) 529 if (adev->ip_blocks[i].version->type == type && 530 adev->ip_blocks[i].status.valid && 531 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 532 count++; 533 534 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 535 } 536 case AMDGPU_INFO_TIMESTAMP: 537 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 538 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 539 case AMDGPU_INFO_FW_VERSION: { 540 struct drm_amdgpu_info_firmware fw_info; 541 int ret; 542 543 /* We only support one instance of each IP block right now. */ 544 if (info->query_fw.ip_instance != 0) 545 return -EINVAL; 546 547 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 548 if (ret) 549 return ret; 550 551 return copy_to_user(out, &fw_info, 552 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 553 } 554 case AMDGPU_INFO_NUM_BYTES_MOVED: 555 ui64 = atomic64_read(&adev->num_bytes_moved); 556 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 557 case AMDGPU_INFO_NUM_EVICTIONS: 558 ui64 = atomic64_read(&adev->num_evictions); 559 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 560 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 561 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 562 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 563 case AMDGPU_INFO_VRAM_USAGE: 564 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 565 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 566 case AMDGPU_INFO_VIS_VRAM_USAGE: 567 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 568 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 569 case AMDGPU_INFO_GTT_USAGE: 570 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 571 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 572 case AMDGPU_INFO_GDS_CONFIG: { 573 struct drm_amdgpu_info_gds gds_info; 574 575 memset(&gds_info, 0, sizeof(gds_info)); 576 gds_info.compute_partition_size = adev->gds.gds_size; 577 gds_info.gds_total_size = adev->gds.gds_size; 578 gds_info.gws_per_compute_partition = adev->gds.gws_size; 579 gds_info.oa_per_compute_partition = adev->gds.oa_size; 580 return copy_to_user(out, &gds_info, 581 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 582 } 583 case AMDGPU_INFO_VRAM_GTT: { 584 struct drm_amdgpu_info_vram_gtt vram_gtt; 585 586 vram_gtt.vram_size = adev->gmc.real_vram_size - 587 atomic64_read(&adev->vram_pin_size); 588 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size - 589 atomic64_read(&adev->visible_pin_size); 590 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 591 vram_gtt.gtt_size *= PAGE_SIZE; 592 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 593 return copy_to_user(out, &vram_gtt, 594 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 595 } 596 case AMDGPU_INFO_MEMORY: { 597 struct drm_amdgpu_memory_info mem; 598 599 memset(&mem, 0, sizeof(mem)); 600 mem.vram.total_heap_size = adev->gmc.real_vram_size; 601 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 602 atomic64_read(&adev->vram_pin_size); 603 mem.vram.heap_usage = 604 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 605 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 606 607 mem.cpu_accessible_vram.total_heap_size = 608 adev->gmc.visible_vram_size; 609 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size - 610 atomic64_read(&adev->visible_pin_size); 611 mem.cpu_accessible_vram.heap_usage = 612 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 613 mem.cpu_accessible_vram.max_allocation = 614 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 615 616 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 617 mem.gtt.total_heap_size *= PAGE_SIZE; 618 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 619 atomic64_read(&adev->gart_pin_size); 620 mem.gtt.heap_usage = 621 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 622 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 623 624 return copy_to_user(out, &mem, 625 min((size_t)size, sizeof(mem))) 626 ? -EFAULT : 0; 627 } 628 case AMDGPU_INFO_READ_MMR_REG: { 629 unsigned n, alloc_size; 630 uint32_t *regs; 631 unsigned se_num = (info->read_mmr_reg.instance >> 632 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 633 AMDGPU_INFO_MMR_SE_INDEX_MASK; 634 unsigned sh_num = (info->read_mmr_reg.instance >> 635 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 636 AMDGPU_INFO_MMR_SH_INDEX_MASK; 637 638 /* set full masks if the userspace set all bits 639 * in the bitfields */ 640 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 641 se_num = 0xffffffff; 642 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 643 sh_num = 0xffffffff; 644 645 if (info->read_mmr_reg.count > 128) 646 return -EINVAL; 647 648 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 649 if (!regs) 650 return -ENOMEM; 651 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 652 653 for (i = 0; i < info->read_mmr_reg.count; i++) 654 if (amdgpu_asic_read_register(adev, se_num, sh_num, 655 info->read_mmr_reg.dword_offset + i, 656 ®s[i])) { 657 DRM_DEBUG_KMS("unallowed offset %#x\n", 658 info->read_mmr_reg.dword_offset + i); 659 kfree(regs); 660 return -EFAULT; 661 } 662 n = copy_to_user(out, regs, min(size, alloc_size)); 663 kfree(regs); 664 return n ? -EFAULT : 0; 665 } 666 case AMDGPU_INFO_DEV_INFO: { 667 struct drm_amdgpu_info_device dev_info = {}; 668 uint64_t vm_size; 669 670 dev_info.device_id = dev->pdev->device; 671 dev_info.chip_rev = adev->rev_id; 672 dev_info.external_rev = adev->external_rev_id; 673 dev_info.pci_rev = dev->pdev->revision; 674 dev_info.family = adev->family; 675 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 676 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 677 /* return all clocks in KHz */ 678 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 679 if (adev->pm.dpm_enabled) { 680 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 681 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 682 } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) && 683 adev->virt.ops->get_pp_clk) { 684 dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev, false) * 10; 685 dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev, false) * 10; 686 } else { 687 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 688 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 689 } 690 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 691 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 692 adev->gfx.config.max_shader_engines; 693 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 694 dev_info._pad = 0; 695 dev_info.ids_flags = 0; 696 if (adev->flags & AMD_IS_APU) 697 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 698 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 699 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 700 701 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 702 vm_size -= AMDGPU_VA_RESERVED_SIZE; 703 704 /* Older VCE FW versions are buggy and can handle only 40bits */ 705 if (adev->vce.fw_version && 706 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 707 vm_size = min(vm_size, 1ULL << 40); 708 709 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 710 dev_info.virtual_address_max = 711 min(vm_size, AMDGPU_GMC_HOLE_START); 712 713 if (vm_size > AMDGPU_GMC_HOLE_START) { 714 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 715 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 716 } 717 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 718 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 719 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 720 dev_info.cu_active_number = adev->gfx.cu_info.number; 721 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 722 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 723 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 724 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 725 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 726 sizeof(adev->gfx.cu_info.bitmap)); 727 dev_info.vram_type = adev->gmc.vram_type; 728 dev_info.vram_bit_width = adev->gmc.vram_width; 729 dev_info.vce_harvest_config = adev->vce.harvest_config; 730 dev_info.gc_double_offchip_lds_buf = 731 adev->gfx.config.double_offchip_lds_buf; 732 733 if (amdgpu_ngg) { 734 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 735 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 736 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 737 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 738 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 739 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 740 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 741 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 742 } 743 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 744 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 745 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 746 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 747 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 748 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 749 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 750 751 if (adev->family >= AMDGPU_FAMILY_NV) 752 dev_info.pa_sc_tile_steering_override = 753 adev->gfx.config.pa_sc_tile_steering_override; 754 755 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 756 757 return copy_to_user(out, &dev_info, 758 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 759 } 760 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 761 unsigned i; 762 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 763 struct amd_vce_state *vce_state; 764 765 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 766 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 767 if (vce_state) { 768 vce_clk_table.entries[i].sclk = vce_state->sclk; 769 vce_clk_table.entries[i].mclk = vce_state->mclk; 770 vce_clk_table.entries[i].eclk = vce_state->evclk; 771 vce_clk_table.num_valid_entries++; 772 } 773 } 774 775 return copy_to_user(out, &vce_clk_table, 776 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 777 } 778 case AMDGPU_INFO_VBIOS: { 779 uint32_t bios_size = adev->bios_size; 780 781 switch (info->vbios_info.type) { 782 case AMDGPU_INFO_VBIOS_SIZE: 783 return copy_to_user(out, &bios_size, 784 min((size_t)size, sizeof(bios_size))) 785 ? -EFAULT : 0; 786 case AMDGPU_INFO_VBIOS_IMAGE: { 787 uint8_t *bios; 788 uint32_t bios_offset = info->vbios_info.offset; 789 790 if (bios_offset >= bios_size) 791 return -EINVAL; 792 793 bios = adev->bios + bios_offset; 794 return copy_to_user(out, bios, 795 min((size_t)size, (size_t)(bios_size - bios_offset))) 796 ? -EFAULT : 0; 797 } 798 default: 799 DRM_DEBUG_KMS("Invalid request %d\n", 800 info->vbios_info.type); 801 return -EINVAL; 802 } 803 } 804 case AMDGPU_INFO_NUM_HANDLES: { 805 struct drm_amdgpu_info_num_handles handle; 806 807 switch (info->query_hw_ip.type) { 808 case AMDGPU_HW_IP_UVD: 809 /* Starting Polaris, we support unlimited UVD handles */ 810 if (adev->asic_type < CHIP_POLARIS10) { 811 handle.uvd_max_handles = adev->uvd.max_handles; 812 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 813 814 return copy_to_user(out, &handle, 815 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 816 } else { 817 return -ENODATA; 818 } 819 820 break; 821 default: 822 return -EINVAL; 823 } 824 } 825 case AMDGPU_INFO_SENSOR: { 826 if (!adev->pm.dpm_enabled) 827 return -ENOENT; 828 829 switch (info->sensor_info.type) { 830 case AMDGPU_INFO_SENSOR_GFX_SCLK: 831 /* get sclk in Mhz */ 832 if (amdgpu_dpm_read_sensor(adev, 833 AMDGPU_PP_SENSOR_GFX_SCLK, 834 (void *)&ui32, &ui32_size)) { 835 return -EINVAL; 836 } 837 ui32 /= 100; 838 break; 839 case AMDGPU_INFO_SENSOR_GFX_MCLK: 840 /* get mclk in Mhz */ 841 if (amdgpu_dpm_read_sensor(adev, 842 AMDGPU_PP_SENSOR_GFX_MCLK, 843 (void *)&ui32, &ui32_size)) { 844 return -EINVAL; 845 } 846 ui32 /= 100; 847 break; 848 case AMDGPU_INFO_SENSOR_GPU_TEMP: 849 /* get temperature in millidegrees C */ 850 if (amdgpu_dpm_read_sensor(adev, 851 AMDGPU_PP_SENSOR_GPU_TEMP, 852 (void *)&ui32, &ui32_size)) { 853 return -EINVAL; 854 } 855 break; 856 case AMDGPU_INFO_SENSOR_GPU_LOAD: 857 /* get GPU load */ 858 if (amdgpu_dpm_read_sensor(adev, 859 AMDGPU_PP_SENSOR_GPU_LOAD, 860 (void *)&ui32, &ui32_size)) { 861 return -EINVAL; 862 } 863 break; 864 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 865 /* get average GPU power */ 866 if (amdgpu_dpm_read_sensor(adev, 867 AMDGPU_PP_SENSOR_GPU_POWER, 868 (void *)&ui32, &ui32_size)) { 869 return -EINVAL; 870 } 871 ui32 >>= 8; 872 break; 873 case AMDGPU_INFO_SENSOR_VDDNB: 874 /* get VDDNB in millivolts */ 875 if (amdgpu_dpm_read_sensor(adev, 876 AMDGPU_PP_SENSOR_VDDNB, 877 (void *)&ui32, &ui32_size)) { 878 return -EINVAL; 879 } 880 break; 881 case AMDGPU_INFO_SENSOR_VDDGFX: 882 /* get VDDGFX in millivolts */ 883 if (amdgpu_dpm_read_sensor(adev, 884 AMDGPU_PP_SENSOR_VDDGFX, 885 (void *)&ui32, &ui32_size)) { 886 return -EINVAL; 887 } 888 break; 889 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 890 /* get stable pstate sclk in Mhz */ 891 if (amdgpu_dpm_read_sensor(adev, 892 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 893 (void *)&ui32, &ui32_size)) { 894 return -EINVAL; 895 } 896 ui32 /= 100; 897 break; 898 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 899 /* get stable pstate mclk in Mhz */ 900 if (amdgpu_dpm_read_sensor(adev, 901 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 902 (void *)&ui32, &ui32_size)) { 903 return -EINVAL; 904 } 905 ui32 /= 100; 906 break; 907 default: 908 DRM_DEBUG_KMS("Invalid request %d\n", 909 info->sensor_info.type); 910 return -EINVAL; 911 } 912 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 913 } 914 case AMDGPU_INFO_VRAM_LOST_COUNTER: 915 ui32 = atomic_read(&adev->vram_lost_counter); 916 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 917 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 918 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 919 uint64_t ras_mask; 920 921 if (!ras) 922 return -EINVAL; 923 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 924 925 return copy_to_user(out, &ras_mask, 926 min_t(u64, size, sizeof(ras_mask))) ? 927 -EFAULT : 0; 928 } 929 default: 930 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 931 return -EINVAL; 932 } 933 return 0; 934 } 935 936 937 /* 938 * Outdated mess for old drm with Xorg being in charge (void function now). 939 */ 940 /** 941 * amdgpu_driver_lastclose_kms - drm callback for last close 942 * 943 * @dev: drm dev pointer 944 * 945 * Switch vga_switcheroo state after last close (all asics). 946 */ 947 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 948 { 949 drm_fb_helper_lastclose(dev); 950 vga_switcheroo_process_delayed_switch(); 951 } 952 953 /** 954 * amdgpu_driver_open_kms - drm callback for open 955 * 956 * @dev: drm dev pointer 957 * @file_priv: drm file 958 * 959 * On device open, init vm on cayman+ (all asics). 960 * Returns 0 on success, error on failure. 961 */ 962 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 963 { 964 struct amdgpu_device *adev = dev->dev_private; 965 struct amdgpu_fpriv *fpriv; 966 int r, pasid; 967 968 /* Ensure IB tests are run on ring */ 969 flush_delayed_work(&adev->delayed_init_work); 970 971 file_priv->driver_priv = NULL; 972 973 r = pm_runtime_get_sync(dev->dev); 974 if (r < 0) 975 return r; 976 977 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 978 if (unlikely(!fpriv)) { 979 r = -ENOMEM; 980 goto out_suspend; 981 } 982 983 pasid = amdgpu_pasid_alloc(16); 984 if (pasid < 0) { 985 dev_warn(adev->dev, "No more PASIDs available!"); 986 pasid = 0; 987 } 988 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 989 if (r) 990 goto error_pasid; 991 992 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 993 if (!fpriv->prt_va) { 994 r = -ENOMEM; 995 goto error_vm; 996 } 997 998 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 999 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1000 1001 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1002 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1003 if (r) 1004 goto error_vm; 1005 } 1006 1007 mutex_init(&fpriv->bo_list_lock); 1008 idr_init(&fpriv->bo_list_handles); 1009 1010 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1011 1012 file_priv->driver_priv = fpriv; 1013 goto out_suspend; 1014 1015 error_vm: 1016 amdgpu_vm_fini(adev, &fpriv->vm); 1017 1018 error_pasid: 1019 if (pasid) 1020 amdgpu_pasid_free(pasid); 1021 1022 kfree(fpriv); 1023 1024 out_suspend: 1025 pm_runtime_mark_last_busy(dev->dev); 1026 pm_runtime_put_autosuspend(dev->dev); 1027 1028 return r; 1029 } 1030 1031 /** 1032 * amdgpu_driver_postclose_kms - drm callback for post close 1033 * 1034 * @dev: drm dev pointer 1035 * @file_priv: drm file 1036 * 1037 * On device post close, tear down vm on cayman+ (all asics). 1038 */ 1039 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1040 struct drm_file *file_priv) 1041 { 1042 struct amdgpu_device *adev = dev->dev_private; 1043 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1044 struct amdgpu_bo_list *list; 1045 struct amdgpu_bo *pd; 1046 unsigned int pasid; 1047 int handle; 1048 1049 if (!fpriv) 1050 return; 1051 1052 pm_runtime_get_sync(dev->dev); 1053 1054 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1055 amdgpu_uvd_free_handles(adev, file_priv); 1056 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1057 amdgpu_vce_free_handles(adev, file_priv); 1058 1059 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1060 1061 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1062 /* TODO: how to handle reserve failure */ 1063 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1064 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1065 fpriv->csa_va = NULL; 1066 amdgpu_bo_unreserve(adev->virt.csa_obj); 1067 } 1068 1069 pasid = fpriv->vm.pasid; 1070 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1071 1072 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1073 amdgpu_vm_fini(adev, &fpriv->vm); 1074 1075 if (pasid) 1076 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1077 amdgpu_bo_unref(&pd); 1078 1079 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1080 amdgpu_bo_list_put(list); 1081 1082 idr_destroy(&fpriv->bo_list_handles); 1083 mutex_destroy(&fpriv->bo_list_lock); 1084 1085 kfree(fpriv); 1086 file_priv->driver_priv = NULL; 1087 1088 pm_runtime_mark_last_busy(dev->dev); 1089 pm_runtime_put_autosuspend(dev->dev); 1090 } 1091 1092 /* 1093 * VBlank related functions. 1094 */ 1095 /** 1096 * amdgpu_get_vblank_counter_kms - get frame count 1097 * 1098 * @dev: drm dev pointer 1099 * @pipe: crtc to get the frame count from 1100 * 1101 * Gets the frame count on the requested crtc (all asics). 1102 * Returns frame count on success, -EINVAL on failure. 1103 */ 1104 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 1105 { 1106 struct amdgpu_device *adev = dev->dev_private; 1107 int vpos, hpos, stat; 1108 u32 count; 1109 1110 if (pipe >= adev->mode_info.num_crtc) { 1111 DRM_ERROR("Invalid crtc %u\n", pipe); 1112 return -EINVAL; 1113 } 1114 1115 /* The hw increments its frame counter at start of vsync, not at start 1116 * of vblank, as is required by DRM core vblank counter handling. 1117 * Cook the hw count here to make it appear to the caller as if it 1118 * incremented at start of vblank. We measure distance to start of 1119 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1120 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1121 * result by 1 to give the proper appearance to caller. 1122 */ 1123 if (adev->mode_info.crtcs[pipe]) { 1124 /* Repeat readout if needed to provide stable result if 1125 * we cross start of vsync during the queries. 1126 */ 1127 do { 1128 count = amdgpu_display_vblank_get_counter(adev, pipe); 1129 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1130 * vpos as distance to start of vblank, instead of 1131 * regular vertical scanout pos. 1132 */ 1133 stat = amdgpu_display_get_crtc_scanoutpos( 1134 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1135 &vpos, &hpos, NULL, NULL, 1136 &adev->mode_info.crtcs[pipe]->base.hwmode); 1137 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1138 1139 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1140 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1141 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1142 } else { 1143 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1144 pipe, vpos); 1145 1146 /* Bump counter if we are at >= leading edge of vblank, 1147 * but before vsync where vpos would turn negative and 1148 * the hw counter really increments. 1149 */ 1150 if (vpos >= 0) 1151 count++; 1152 } 1153 } else { 1154 /* Fallback to use value as is. */ 1155 count = amdgpu_display_vblank_get_counter(adev, pipe); 1156 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1157 } 1158 1159 return count; 1160 } 1161 1162 /** 1163 * amdgpu_enable_vblank_kms - enable vblank interrupt 1164 * 1165 * @dev: drm dev pointer 1166 * @pipe: crtc to enable vblank interrupt for 1167 * 1168 * Enable the interrupt on the requested crtc (all asics). 1169 * Returns 0 on success, -EINVAL on failure. 1170 */ 1171 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1172 { 1173 struct amdgpu_device *adev = dev->dev_private; 1174 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1175 1176 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1177 } 1178 1179 /** 1180 * amdgpu_disable_vblank_kms - disable vblank interrupt 1181 * 1182 * @dev: drm dev pointer 1183 * @pipe: crtc to disable vblank interrupt for 1184 * 1185 * Disable the interrupt on the requested crtc (all asics). 1186 */ 1187 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1188 { 1189 struct amdgpu_device *adev = dev->dev_private; 1190 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1191 1192 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1193 } 1194 1195 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1196 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1197 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1198 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1199 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1200 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1201 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1202 /* KMS */ 1203 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1204 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1205 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1206 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1207 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1208 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1209 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1210 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1211 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1212 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1213 }; 1214 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1215 1216 /* 1217 * Debugfs info 1218 */ 1219 #if defined(CONFIG_DEBUG_FS) 1220 1221 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1222 { 1223 struct drm_info_node *node = (struct drm_info_node *) m->private; 1224 struct drm_device *dev = node->minor->dev; 1225 struct amdgpu_device *adev = dev->dev_private; 1226 struct drm_amdgpu_info_firmware fw_info; 1227 struct drm_amdgpu_query_fw query_fw; 1228 struct atom_context *ctx = adev->mode_info.atom_context; 1229 int ret, i; 1230 1231 /* VCE */ 1232 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1233 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1234 if (ret) 1235 return ret; 1236 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1237 fw_info.feature, fw_info.ver); 1238 1239 /* UVD */ 1240 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1241 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1242 if (ret) 1243 return ret; 1244 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1245 fw_info.feature, fw_info.ver); 1246 1247 /* GMC */ 1248 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1249 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1250 if (ret) 1251 return ret; 1252 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1253 fw_info.feature, fw_info.ver); 1254 1255 /* ME */ 1256 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1257 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1258 if (ret) 1259 return ret; 1260 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1261 fw_info.feature, fw_info.ver); 1262 1263 /* PFP */ 1264 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1265 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1266 if (ret) 1267 return ret; 1268 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1269 fw_info.feature, fw_info.ver); 1270 1271 /* CE */ 1272 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1273 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1274 if (ret) 1275 return ret; 1276 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1277 fw_info.feature, fw_info.ver); 1278 1279 /* RLC */ 1280 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1281 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1282 if (ret) 1283 return ret; 1284 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1285 fw_info.feature, fw_info.ver); 1286 1287 /* RLC SAVE RESTORE LIST CNTL */ 1288 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1289 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1290 if (ret) 1291 return ret; 1292 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1293 fw_info.feature, fw_info.ver); 1294 1295 /* RLC SAVE RESTORE LIST GPM MEM */ 1296 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1297 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1298 if (ret) 1299 return ret; 1300 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1301 fw_info.feature, fw_info.ver); 1302 1303 /* RLC SAVE RESTORE LIST SRM MEM */ 1304 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1305 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1306 if (ret) 1307 return ret; 1308 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1309 fw_info.feature, fw_info.ver); 1310 1311 /* MEC */ 1312 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1313 query_fw.index = 0; 1314 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1315 if (ret) 1316 return ret; 1317 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1318 fw_info.feature, fw_info.ver); 1319 1320 /* MEC2 */ 1321 if (adev->asic_type == CHIP_KAVERI || 1322 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1323 query_fw.index = 1; 1324 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1325 if (ret) 1326 return ret; 1327 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1328 fw_info.feature, fw_info.ver); 1329 } 1330 1331 /* PSP SOS */ 1332 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1333 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1334 if (ret) 1335 return ret; 1336 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1337 fw_info.feature, fw_info.ver); 1338 1339 1340 /* PSP ASD */ 1341 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1342 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1343 if (ret) 1344 return ret; 1345 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1346 fw_info.feature, fw_info.ver); 1347 1348 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1349 for (i = 0; i < 2; i++) { 1350 query_fw.index = i; 1351 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1352 if (ret) 1353 continue; 1354 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1355 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1356 } 1357 1358 /* SMC */ 1359 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1360 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1361 if (ret) 1362 return ret; 1363 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1364 fw_info.feature, fw_info.ver); 1365 1366 /* SDMA */ 1367 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1368 for (i = 0; i < adev->sdma.num_instances; i++) { 1369 query_fw.index = i; 1370 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1371 if (ret) 1372 return ret; 1373 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1374 i, fw_info.feature, fw_info.ver); 1375 } 1376 1377 /* VCN */ 1378 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1379 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1380 if (ret) 1381 return ret; 1382 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1383 fw_info.feature, fw_info.ver); 1384 1385 /* DMCU */ 1386 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1387 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1388 if (ret) 1389 return ret; 1390 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1391 fw_info.feature, fw_info.ver); 1392 1393 1394 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1395 1396 return 0; 1397 } 1398 1399 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1400 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1401 }; 1402 #endif 1403 1404 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1405 { 1406 #if defined(CONFIG_DEBUG_FS) 1407 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1408 ARRAY_SIZE(amdgpu_firmware_info_list)); 1409 #else 1410 return 0; 1411 #endif 1412 } 1413