1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 98 amdgpu_device_fini(adev); 99 100 done_free: 101 kfree(adev); 102 dev->dev_private = NULL; 103 } 104 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 106 { 107 struct amdgpu_gpu_instance *gpu_instance; 108 109 mutex_lock(&mgpu_info.mutex); 110 111 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 112 DRM_ERROR("Cannot register more gpu instance\n"); 113 mutex_unlock(&mgpu_info.mutex); 114 return; 115 } 116 117 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 118 gpu_instance->adev = adev; 119 gpu_instance->mgpu_fan_enabled = 0; 120 121 mgpu_info.num_gpu++; 122 if (adev->flags & AMD_IS_APU) 123 mgpu_info.num_apu++; 124 else 125 mgpu_info.num_dgpu++; 126 127 mutex_unlock(&mgpu_info.mutex); 128 } 129 130 /** 131 * amdgpu_driver_load_kms - Main load function for KMS. 132 * 133 * @dev: drm dev pointer 134 * @flags: device flags 135 * 136 * This is the main load function for KMS (all asics). 137 * Returns 0 on success, error on failure. 138 */ 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 140 { 141 struct amdgpu_device *adev; 142 int r, acpi_status; 143 144 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 145 if (adev == NULL) { 146 return -ENOMEM; 147 } 148 dev->dev_private = (void *)adev; 149 150 if (amdgpu_has_atpx() && 151 (amdgpu_is_atpx_hybrid() || 152 amdgpu_has_atpx_dgpu_power_cntl()) && 153 ((flags & AMD_IS_APU) == 0) && 154 !pci_is_thunderbolt_attached(dev->pdev)) 155 flags |= AMD_IS_PX; 156 157 /* amdgpu_device_init should report only fatal error 158 * like memory allocation failure or iomapping failure, 159 * or memory manager initialization failure, it must 160 * properly initialize the GPU MC controller and permit 161 * VRAM allocation 162 */ 163 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 164 if (r) { 165 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 166 goto out; 167 } 168 169 if (amdgpu_device_supports_boco(dev) && 170 (amdgpu_runtime_pm != 0)) /* enable runpm by default for boco */ 171 adev->runpm = true; 172 else if (amdgpu_device_supports_baco(dev) && 173 (amdgpu_runtime_pm != 0) && 174 (adev->asic_type >= CHIP_TOPAZ) && 175 (adev->asic_type != CHIP_VEGA20) && 176 (adev->asic_type != CHIP_ARCTURUS)) /* enable runpm on VI+ */ 177 adev->runpm = true; 178 else if (amdgpu_device_supports_baco(dev) && 179 (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 on CI */ 180 adev->runpm = true; 181 182 /* Call ACPI methods: require modeset init 183 * but failure is not fatal 184 */ 185 if (!r) { 186 acpi_status = amdgpu_acpi_init(adev); 187 if (acpi_status) 188 dev_dbg(&dev->pdev->dev, 189 "Error during ACPI methods call\n"); 190 } 191 192 if (adev->runpm) { 193 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); 194 pm_runtime_use_autosuspend(dev->dev); 195 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 196 pm_runtime_set_active(dev->dev); 197 pm_runtime_allow(dev->dev); 198 pm_runtime_mark_last_busy(dev->dev); 199 pm_runtime_put_autosuspend(dev->dev); 200 } 201 202 out: 203 if (r) { 204 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 205 if (adev->rmmio && adev->runpm) 206 pm_runtime_put_noidle(dev->dev); 207 amdgpu_driver_unload_kms(dev); 208 } 209 210 return r; 211 } 212 213 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 214 struct drm_amdgpu_query_fw *query_fw, 215 struct amdgpu_device *adev) 216 { 217 switch (query_fw->fw_type) { 218 case AMDGPU_INFO_FW_VCE: 219 fw_info->ver = adev->vce.fw_version; 220 fw_info->feature = adev->vce.fb_version; 221 break; 222 case AMDGPU_INFO_FW_UVD: 223 fw_info->ver = adev->uvd.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_VCN: 227 fw_info->ver = adev->vcn.fw_version; 228 fw_info->feature = 0; 229 break; 230 case AMDGPU_INFO_FW_GMC: 231 fw_info->ver = adev->gmc.fw_version; 232 fw_info->feature = 0; 233 break; 234 case AMDGPU_INFO_FW_GFX_ME: 235 fw_info->ver = adev->gfx.me_fw_version; 236 fw_info->feature = adev->gfx.me_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_PFP: 239 fw_info->ver = adev->gfx.pfp_fw_version; 240 fw_info->feature = adev->gfx.pfp_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_CE: 243 fw_info->ver = adev->gfx.ce_fw_version; 244 fw_info->feature = adev->gfx.ce_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC: 247 fw_info->ver = adev->gfx.rlc_fw_version; 248 fw_info->feature = adev->gfx.rlc_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 251 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 252 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 255 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 256 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 259 fw_info->ver = adev->gfx.rlc_srls_fw_version; 260 fw_info->feature = adev->gfx.rlc_srls_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_MEC: 263 if (query_fw->index == 0) { 264 fw_info->ver = adev->gfx.mec_fw_version; 265 fw_info->feature = adev->gfx.mec_feature_version; 266 } else if (query_fw->index == 1) { 267 fw_info->ver = adev->gfx.mec2_fw_version; 268 fw_info->feature = adev->gfx.mec2_feature_version; 269 } else 270 return -EINVAL; 271 break; 272 case AMDGPU_INFO_FW_SMC: 273 fw_info->ver = adev->pm.fw_version; 274 fw_info->feature = 0; 275 break; 276 case AMDGPU_INFO_FW_TA: 277 if (query_fw->index > 1) 278 return -EINVAL; 279 if (query_fw->index == 0) { 280 fw_info->ver = adev->psp.ta_fw_version; 281 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 282 } else { 283 fw_info->ver = adev->psp.ta_fw_version; 284 fw_info->feature = adev->psp.ta_ras_ucode_version; 285 } 286 break; 287 case AMDGPU_INFO_FW_SDMA: 288 if (query_fw->index >= adev->sdma.num_instances) 289 return -EINVAL; 290 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 291 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 292 break; 293 case AMDGPU_INFO_FW_SOS: 294 fw_info->ver = adev->psp.sos_fw_version; 295 fw_info->feature = adev->psp.sos_feature_version; 296 break; 297 case AMDGPU_INFO_FW_ASD: 298 fw_info->ver = adev->psp.asd_fw_version; 299 fw_info->feature = adev->psp.asd_feature_version; 300 break; 301 case AMDGPU_INFO_FW_DMCU: 302 fw_info->ver = adev->dm.dmcu_fw_version; 303 fw_info->feature = 0; 304 break; 305 case AMDGPU_INFO_FW_DMCUB: 306 fw_info->ver = adev->dm.dmcub_fw_version; 307 fw_info->feature = 0; 308 break; 309 default: 310 return -EINVAL; 311 } 312 return 0; 313 } 314 315 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 316 struct drm_amdgpu_info *info, 317 struct drm_amdgpu_info_hw_ip *result) 318 { 319 uint32_t ib_start_alignment = 0; 320 uint32_t ib_size_alignment = 0; 321 enum amd_ip_block_type type; 322 unsigned int num_rings = 0; 323 unsigned int i, j; 324 325 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 326 return -EINVAL; 327 328 switch (info->query_hw_ip.type) { 329 case AMDGPU_HW_IP_GFX: 330 type = AMD_IP_BLOCK_TYPE_GFX; 331 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 332 if (adev->gfx.gfx_ring[i].sched.ready) 333 ++num_rings; 334 ib_start_alignment = 32; 335 ib_size_alignment = 32; 336 break; 337 case AMDGPU_HW_IP_COMPUTE: 338 type = AMD_IP_BLOCK_TYPE_GFX; 339 for (i = 0; i < adev->gfx.num_compute_rings; i++) 340 if (adev->gfx.compute_ring[i].sched.ready) 341 ++num_rings; 342 ib_start_alignment = 32; 343 ib_size_alignment = 32; 344 break; 345 case AMDGPU_HW_IP_DMA: 346 type = AMD_IP_BLOCK_TYPE_SDMA; 347 for (i = 0; i < adev->sdma.num_instances; i++) 348 if (adev->sdma.instance[i].ring.sched.ready) 349 ++num_rings; 350 ib_start_alignment = 256; 351 ib_size_alignment = 4; 352 break; 353 case AMDGPU_HW_IP_UVD: 354 type = AMD_IP_BLOCK_TYPE_UVD; 355 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 356 if (adev->uvd.harvest_config & (1 << i)) 357 continue; 358 359 if (adev->uvd.inst[i].ring.sched.ready) 360 ++num_rings; 361 } 362 ib_start_alignment = 64; 363 ib_size_alignment = 64; 364 break; 365 case AMDGPU_HW_IP_VCE: 366 type = AMD_IP_BLOCK_TYPE_VCE; 367 for (i = 0; i < adev->vce.num_rings; i++) 368 if (adev->vce.ring[i].sched.ready) 369 ++num_rings; 370 ib_start_alignment = 4; 371 ib_size_alignment = 1; 372 break; 373 case AMDGPU_HW_IP_UVD_ENC: 374 type = AMD_IP_BLOCK_TYPE_UVD; 375 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 376 if (adev->uvd.harvest_config & (1 << i)) 377 continue; 378 379 for (j = 0; j < adev->uvd.num_enc_rings; j++) 380 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 381 ++num_rings; 382 } 383 ib_start_alignment = 64; 384 ib_size_alignment = 64; 385 break; 386 case AMDGPU_HW_IP_VCN_DEC: 387 type = AMD_IP_BLOCK_TYPE_VCN; 388 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 389 if (adev->uvd.harvest_config & (1 << i)) 390 continue; 391 392 if (adev->vcn.inst[i].ring_dec.sched.ready) 393 ++num_rings; 394 } 395 ib_start_alignment = 16; 396 ib_size_alignment = 16; 397 break; 398 case AMDGPU_HW_IP_VCN_ENC: 399 type = AMD_IP_BLOCK_TYPE_VCN; 400 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 401 if (adev->uvd.harvest_config & (1 << i)) 402 continue; 403 404 for (j = 0; j < adev->vcn.num_enc_rings; j++) 405 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 406 ++num_rings; 407 } 408 ib_start_alignment = 64; 409 ib_size_alignment = 1; 410 break; 411 case AMDGPU_HW_IP_VCN_JPEG: 412 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 413 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 414 415 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 416 if (adev->jpeg.harvest_config & (1 << i)) 417 continue; 418 419 if (adev->jpeg.inst[i].ring_dec.sched.ready) 420 ++num_rings; 421 } 422 ib_start_alignment = 16; 423 ib_size_alignment = 16; 424 break; 425 default: 426 return -EINVAL; 427 } 428 429 for (i = 0; i < adev->num_ip_blocks; i++) 430 if (adev->ip_blocks[i].version->type == type && 431 adev->ip_blocks[i].status.valid) 432 break; 433 434 if (i == adev->num_ip_blocks) 435 return 0; 436 437 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 438 num_rings); 439 440 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 441 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 442 result->capabilities_flags = 0; 443 result->available_rings = (1 << num_rings) - 1; 444 result->ib_start_alignment = ib_start_alignment; 445 result->ib_size_alignment = ib_size_alignment; 446 return 0; 447 } 448 449 /* 450 * Userspace get information ioctl 451 */ 452 /** 453 * amdgpu_info_ioctl - answer a device specific request. 454 * 455 * @adev: amdgpu device pointer 456 * @data: request object 457 * @filp: drm filp 458 * 459 * This function is used to pass device specific parameters to the userspace 460 * drivers. Examples include: pci device id, pipeline parms, tiling params, 461 * etc. (all asics). 462 * Returns 0 on success, -EINVAL on failure. 463 */ 464 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 465 { 466 struct amdgpu_device *adev = dev->dev_private; 467 struct drm_amdgpu_info *info = data; 468 struct amdgpu_mode_info *minfo = &adev->mode_info; 469 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 470 uint32_t size = info->return_size; 471 struct drm_crtc *crtc; 472 uint32_t ui32 = 0; 473 uint64_t ui64 = 0; 474 int i, found; 475 int ui32_size = sizeof(ui32); 476 477 if (!info->return_size || !info->return_pointer) 478 return -EINVAL; 479 480 switch (info->query) { 481 case AMDGPU_INFO_ACCEL_WORKING: 482 ui32 = adev->accel_working; 483 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 484 case AMDGPU_INFO_CRTC_FROM_ID: 485 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 486 crtc = (struct drm_crtc *)minfo->crtcs[i]; 487 if (crtc && crtc->base.id == info->mode_crtc.id) { 488 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 489 ui32 = amdgpu_crtc->crtc_id; 490 found = 1; 491 break; 492 } 493 } 494 if (!found) { 495 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 496 return -EINVAL; 497 } 498 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 499 case AMDGPU_INFO_HW_IP_INFO: { 500 struct drm_amdgpu_info_hw_ip ip = {}; 501 int ret; 502 503 ret = amdgpu_hw_ip_info(adev, info, &ip); 504 if (ret) 505 return ret; 506 507 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 508 return ret ? -EFAULT : 0; 509 } 510 case AMDGPU_INFO_HW_IP_COUNT: { 511 enum amd_ip_block_type type; 512 uint32_t count = 0; 513 514 switch (info->query_hw_ip.type) { 515 case AMDGPU_HW_IP_GFX: 516 type = AMD_IP_BLOCK_TYPE_GFX; 517 break; 518 case AMDGPU_HW_IP_COMPUTE: 519 type = AMD_IP_BLOCK_TYPE_GFX; 520 break; 521 case AMDGPU_HW_IP_DMA: 522 type = AMD_IP_BLOCK_TYPE_SDMA; 523 break; 524 case AMDGPU_HW_IP_UVD: 525 type = AMD_IP_BLOCK_TYPE_UVD; 526 break; 527 case AMDGPU_HW_IP_VCE: 528 type = AMD_IP_BLOCK_TYPE_VCE; 529 break; 530 case AMDGPU_HW_IP_UVD_ENC: 531 type = AMD_IP_BLOCK_TYPE_UVD; 532 break; 533 case AMDGPU_HW_IP_VCN_DEC: 534 case AMDGPU_HW_IP_VCN_ENC: 535 type = AMD_IP_BLOCK_TYPE_VCN; 536 break; 537 case AMDGPU_HW_IP_VCN_JPEG: 538 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 539 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 540 break; 541 default: 542 return -EINVAL; 543 } 544 545 for (i = 0; i < adev->num_ip_blocks; i++) 546 if (adev->ip_blocks[i].version->type == type && 547 adev->ip_blocks[i].status.valid && 548 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 549 count++; 550 551 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 552 } 553 case AMDGPU_INFO_TIMESTAMP: 554 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 555 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 556 case AMDGPU_INFO_FW_VERSION: { 557 struct drm_amdgpu_info_firmware fw_info; 558 int ret; 559 560 /* We only support one instance of each IP block right now. */ 561 if (info->query_fw.ip_instance != 0) 562 return -EINVAL; 563 564 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 565 if (ret) 566 return ret; 567 568 return copy_to_user(out, &fw_info, 569 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 570 } 571 case AMDGPU_INFO_NUM_BYTES_MOVED: 572 ui64 = atomic64_read(&adev->num_bytes_moved); 573 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 574 case AMDGPU_INFO_NUM_EVICTIONS: 575 ui64 = atomic64_read(&adev->num_evictions); 576 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 577 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 578 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 579 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 580 case AMDGPU_INFO_VRAM_USAGE: 581 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 582 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 583 case AMDGPU_INFO_VIS_VRAM_USAGE: 584 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 585 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 586 case AMDGPU_INFO_GTT_USAGE: 587 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 588 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 589 case AMDGPU_INFO_GDS_CONFIG: { 590 struct drm_amdgpu_info_gds gds_info; 591 592 memset(&gds_info, 0, sizeof(gds_info)); 593 gds_info.compute_partition_size = adev->gds.gds_size; 594 gds_info.gds_total_size = adev->gds.gds_size; 595 gds_info.gws_per_compute_partition = adev->gds.gws_size; 596 gds_info.oa_per_compute_partition = adev->gds.oa_size; 597 return copy_to_user(out, &gds_info, 598 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 599 } 600 case AMDGPU_INFO_VRAM_GTT: { 601 struct drm_amdgpu_info_vram_gtt vram_gtt; 602 603 vram_gtt.vram_size = adev->gmc.real_vram_size - 604 atomic64_read(&adev->vram_pin_size) - 605 AMDGPU_VM_RESERVED_VRAM; 606 vram_gtt.vram_cpu_accessible_size = 607 min(adev->gmc.visible_vram_size - 608 atomic64_read(&adev->visible_pin_size), 609 vram_gtt.vram_size); 610 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 611 vram_gtt.gtt_size *= PAGE_SIZE; 612 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 613 return copy_to_user(out, &vram_gtt, 614 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 615 } 616 case AMDGPU_INFO_MEMORY: { 617 struct drm_amdgpu_memory_info mem; 618 619 memset(&mem, 0, sizeof(mem)); 620 mem.vram.total_heap_size = adev->gmc.real_vram_size; 621 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 622 atomic64_read(&adev->vram_pin_size) - 623 AMDGPU_VM_RESERVED_VRAM; 624 mem.vram.heap_usage = 625 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 626 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 627 628 mem.cpu_accessible_vram.total_heap_size = 629 adev->gmc.visible_vram_size; 630 mem.cpu_accessible_vram.usable_heap_size = 631 min(adev->gmc.visible_vram_size - 632 atomic64_read(&adev->visible_pin_size), 633 mem.vram.usable_heap_size); 634 mem.cpu_accessible_vram.heap_usage = 635 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 636 mem.cpu_accessible_vram.max_allocation = 637 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 638 639 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 640 mem.gtt.total_heap_size *= PAGE_SIZE; 641 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 642 atomic64_read(&adev->gart_pin_size); 643 mem.gtt.heap_usage = 644 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 645 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 646 647 return copy_to_user(out, &mem, 648 min((size_t)size, sizeof(mem))) 649 ? -EFAULT : 0; 650 } 651 case AMDGPU_INFO_READ_MMR_REG: { 652 unsigned n, alloc_size; 653 uint32_t *regs; 654 unsigned se_num = (info->read_mmr_reg.instance >> 655 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 656 AMDGPU_INFO_MMR_SE_INDEX_MASK; 657 unsigned sh_num = (info->read_mmr_reg.instance >> 658 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 659 AMDGPU_INFO_MMR_SH_INDEX_MASK; 660 661 /* set full masks if the userspace set all bits 662 * in the bitfields */ 663 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 664 se_num = 0xffffffff; 665 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 666 sh_num = 0xffffffff; 667 668 if (info->read_mmr_reg.count > 128) 669 return -EINVAL; 670 671 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 672 if (!regs) 673 return -ENOMEM; 674 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 675 676 amdgpu_gfx_off_ctrl(adev, false); 677 for (i = 0; i < info->read_mmr_reg.count; i++) { 678 if (amdgpu_asic_read_register(adev, se_num, sh_num, 679 info->read_mmr_reg.dword_offset + i, 680 ®s[i])) { 681 DRM_DEBUG_KMS("unallowed offset %#x\n", 682 info->read_mmr_reg.dword_offset + i); 683 kfree(regs); 684 amdgpu_gfx_off_ctrl(adev, true); 685 return -EFAULT; 686 } 687 } 688 amdgpu_gfx_off_ctrl(adev, true); 689 n = copy_to_user(out, regs, min(size, alloc_size)); 690 kfree(regs); 691 return n ? -EFAULT : 0; 692 } 693 case AMDGPU_INFO_DEV_INFO: { 694 struct drm_amdgpu_info_device dev_info = {}; 695 uint64_t vm_size; 696 697 dev_info.device_id = dev->pdev->device; 698 dev_info.chip_rev = adev->rev_id; 699 dev_info.external_rev = adev->external_rev_id; 700 dev_info.pci_rev = dev->pdev->revision; 701 dev_info.family = adev->family; 702 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 703 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 704 /* return all clocks in KHz */ 705 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 706 if (adev->pm.dpm_enabled) { 707 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 708 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 709 } else { 710 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 711 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 712 } 713 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 714 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 715 adev->gfx.config.max_shader_engines; 716 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 717 dev_info._pad = 0; 718 dev_info.ids_flags = 0; 719 if (adev->flags & AMD_IS_APU) 720 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 721 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 722 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 723 724 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 725 vm_size -= AMDGPU_VA_RESERVED_SIZE; 726 727 /* Older VCE FW versions are buggy and can handle only 40bits */ 728 if (adev->vce.fw_version && 729 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 730 vm_size = min(vm_size, 1ULL << 40); 731 732 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 733 dev_info.virtual_address_max = 734 min(vm_size, AMDGPU_GMC_HOLE_START); 735 736 if (vm_size > AMDGPU_GMC_HOLE_START) { 737 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 738 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 739 } 740 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 741 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 742 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 743 dev_info.cu_active_number = adev->gfx.cu_info.number; 744 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 745 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 746 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 747 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 748 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 749 sizeof(adev->gfx.cu_info.bitmap)); 750 dev_info.vram_type = adev->gmc.vram_type; 751 dev_info.vram_bit_width = adev->gmc.vram_width; 752 dev_info.vce_harvest_config = adev->vce.harvest_config; 753 dev_info.gc_double_offchip_lds_buf = 754 adev->gfx.config.double_offchip_lds_buf; 755 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 756 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 757 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 758 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 759 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 760 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 761 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 762 763 if (adev->family >= AMDGPU_FAMILY_NV) 764 dev_info.pa_sc_tile_steering_override = 765 adev->gfx.config.pa_sc_tile_steering_override; 766 767 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 768 769 return copy_to_user(out, &dev_info, 770 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 771 } 772 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 773 unsigned i; 774 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 775 struct amd_vce_state *vce_state; 776 777 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 778 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 779 if (vce_state) { 780 vce_clk_table.entries[i].sclk = vce_state->sclk; 781 vce_clk_table.entries[i].mclk = vce_state->mclk; 782 vce_clk_table.entries[i].eclk = vce_state->evclk; 783 vce_clk_table.num_valid_entries++; 784 } 785 } 786 787 return copy_to_user(out, &vce_clk_table, 788 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 789 } 790 case AMDGPU_INFO_VBIOS: { 791 uint32_t bios_size = adev->bios_size; 792 793 switch (info->vbios_info.type) { 794 case AMDGPU_INFO_VBIOS_SIZE: 795 return copy_to_user(out, &bios_size, 796 min((size_t)size, sizeof(bios_size))) 797 ? -EFAULT : 0; 798 case AMDGPU_INFO_VBIOS_IMAGE: { 799 uint8_t *bios; 800 uint32_t bios_offset = info->vbios_info.offset; 801 802 if (bios_offset >= bios_size) 803 return -EINVAL; 804 805 bios = adev->bios + bios_offset; 806 return copy_to_user(out, bios, 807 min((size_t)size, (size_t)(bios_size - bios_offset))) 808 ? -EFAULT : 0; 809 } 810 default: 811 DRM_DEBUG_KMS("Invalid request %d\n", 812 info->vbios_info.type); 813 return -EINVAL; 814 } 815 } 816 case AMDGPU_INFO_NUM_HANDLES: { 817 struct drm_amdgpu_info_num_handles handle; 818 819 switch (info->query_hw_ip.type) { 820 case AMDGPU_HW_IP_UVD: 821 /* Starting Polaris, we support unlimited UVD handles */ 822 if (adev->asic_type < CHIP_POLARIS10) { 823 handle.uvd_max_handles = adev->uvd.max_handles; 824 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 825 826 return copy_to_user(out, &handle, 827 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 828 } else { 829 return -ENODATA; 830 } 831 832 break; 833 default: 834 return -EINVAL; 835 } 836 } 837 case AMDGPU_INFO_SENSOR: { 838 if (!adev->pm.dpm_enabled) 839 return -ENOENT; 840 841 switch (info->sensor_info.type) { 842 case AMDGPU_INFO_SENSOR_GFX_SCLK: 843 /* get sclk in Mhz */ 844 if (amdgpu_dpm_read_sensor(adev, 845 AMDGPU_PP_SENSOR_GFX_SCLK, 846 (void *)&ui32, &ui32_size)) { 847 return -EINVAL; 848 } 849 ui32 /= 100; 850 break; 851 case AMDGPU_INFO_SENSOR_GFX_MCLK: 852 /* get mclk in Mhz */ 853 if (amdgpu_dpm_read_sensor(adev, 854 AMDGPU_PP_SENSOR_GFX_MCLK, 855 (void *)&ui32, &ui32_size)) { 856 return -EINVAL; 857 } 858 ui32 /= 100; 859 break; 860 case AMDGPU_INFO_SENSOR_GPU_TEMP: 861 /* get temperature in millidegrees C */ 862 if (amdgpu_dpm_read_sensor(adev, 863 AMDGPU_PP_SENSOR_GPU_TEMP, 864 (void *)&ui32, &ui32_size)) { 865 return -EINVAL; 866 } 867 break; 868 case AMDGPU_INFO_SENSOR_GPU_LOAD: 869 /* get GPU load */ 870 if (amdgpu_dpm_read_sensor(adev, 871 AMDGPU_PP_SENSOR_GPU_LOAD, 872 (void *)&ui32, &ui32_size)) { 873 return -EINVAL; 874 } 875 break; 876 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 877 /* get average GPU power */ 878 if (amdgpu_dpm_read_sensor(adev, 879 AMDGPU_PP_SENSOR_GPU_POWER, 880 (void *)&ui32, &ui32_size)) { 881 return -EINVAL; 882 } 883 ui32 >>= 8; 884 break; 885 case AMDGPU_INFO_SENSOR_VDDNB: 886 /* get VDDNB in millivolts */ 887 if (amdgpu_dpm_read_sensor(adev, 888 AMDGPU_PP_SENSOR_VDDNB, 889 (void *)&ui32, &ui32_size)) { 890 return -EINVAL; 891 } 892 break; 893 case AMDGPU_INFO_SENSOR_VDDGFX: 894 /* get VDDGFX in millivolts */ 895 if (amdgpu_dpm_read_sensor(adev, 896 AMDGPU_PP_SENSOR_VDDGFX, 897 (void *)&ui32, &ui32_size)) { 898 return -EINVAL; 899 } 900 break; 901 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 902 /* get stable pstate sclk in Mhz */ 903 if (amdgpu_dpm_read_sensor(adev, 904 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 905 (void *)&ui32, &ui32_size)) { 906 return -EINVAL; 907 } 908 ui32 /= 100; 909 break; 910 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 911 /* get stable pstate mclk in Mhz */ 912 if (amdgpu_dpm_read_sensor(adev, 913 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 914 (void *)&ui32, &ui32_size)) { 915 return -EINVAL; 916 } 917 ui32 /= 100; 918 break; 919 default: 920 DRM_DEBUG_KMS("Invalid request %d\n", 921 info->sensor_info.type); 922 return -EINVAL; 923 } 924 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 925 } 926 case AMDGPU_INFO_VRAM_LOST_COUNTER: 927 ui32 = atomic_read(&adev->vram_lost_counter); 928 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 929 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 930 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 931 uint64_t ras_mask; 932 933 if (!ras) 934 return -EINVAL; 935 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 936 937 return copy_to_user(out, &ras_mask, 938 min_t(u64, size, sizeof(ras_mask))) ? 939 -EFAULT : 0; 940 } 941 default: 942 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 943 return -EINVAL; 944 } 945 return 0; 946 } 947 948 949 /* 950 * Outdated mess for old drm with Xorg being in charge (void function now). 951 */ 952 /** 953 * amdgpu_driver_lastclose_kms - drm callback for last close 954 * 955 * @dev: drm dev pointer 956 * 957 * Switch vga_switcheroo state after last close (all asics). 958 */ 959 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 960 { 961 drm_fb_helper_lastclose(dev); 962 vga_switcheroo_process_delayed_switch(); 963 } 964 965 /** 966 * amdgpu_driver_open_kms - drm callback for open 967 * 968 * @dev: drm dev pointer 969 * @file_priv: drm file 970 * 971 * On device open, init vm on cayman+ (all asics). 972 * Returns 0 on success, error on failure. 973 */ 974 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 975 { 976 struct amdgpu_device *adev = dev->dev_private; 977 struct amdgpu_fpriv *fpriv; 978 int r, pasid; 979 980 /* Ensure IB tests are run on ring */ 981 flush_delayed_work(&adev->delayed_init_work); 982 983 984 if (amdgpu_ras_intr_triggered()) { 985 DRM_ERROR("RAS Intr triggered, device disabled!!"); 986 return -EHWPOISON; 987 } 988 989 file_priv->driver_priv = NULL; 990 991 r = pm_runtime_get_sync(dev->dev); 992 if (r < 0) 993 return r; 994 995 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 996 if (unlikely(!fpriv)) { 997 r = -ENOMEM; 998 goto out_suspend; 999 } 1000 1001 pasid = amdgpu_pasid_alloc(16); 1002 if (pasid < 0) { 1003 dev_warn(adev->dev, "No more PASIDs available!"); 1004 pasid = 0; 1005 } 1006 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1007 if (r) 1008 goto error_pasid; 1009 1010 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1011 if (!fpriv->prt_va) { 1012 r = -ENOMEM; 1013 goto error_vm; 1014 } 1015 1016 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1017 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1018 1019 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1020 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1021 if (r) 1022 goto error_vm; 1023 } 1024 1025 mutex_init(&fpriv->bo_list_lock); 1026 idr_init(&fpriv->bo_list_handles); 1027 1028 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1029 1030 file_priv->driver_priv = fpriv; 1031 goto out_suspend; 1032 1033 error_vm: 1034 amdgpu_vm_fini(adev, &fpriv->vm); 1035 1036 error_pasid: 1037 if (pasid) 1038 amdgpu_pasid_free(pasid); 1039 1040 kfree(fpriv); 1041 1042 out_suspend: 1043 pm_runtime_mark_last_busy(dev->dev); 1044 pm_runtime_put_autosuspend(dev->dev); 1045 1046 return r; 1047 } 1048 1049 /** 1050 * amdgpu_driver_postclose_kms - drm callback for post close 1051 * 1052 * @dev: drm dev pointer 1053 * @file_priv: drm file 1054 * 1055 * On device post close, tear down vm on cayman+ (all asics). 1056 */ 1057 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1058 struct drm_file *file_priv) 1059 { 1060 struct amdgpu_device *adev = dev->dev_private; 1061 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1062 struct amdgpu_bo_list *list; 1063 struct amdgpu_bo *pd; 1064 unsigned int pasid; 1065 int handle; 1066 1067 if (!fpriv) 1068 return; 1069 1070 pm_runtime_get_sync(dev->dev); 1071 1072 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1073 amdgpu_uvd_free_handles(adev, file_priv); 1074 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1075 amdgpu_vce_free_handles(adev, file_priv); 1076 1077 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1078 1079 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1080 /* TODO: how to handle reserve failure */ 1081 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1082 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1083 fpriv->csa_va = NULL; 1084 amdgpu_bo_unreserve(adev->virt.csa_obj); 1085 } 1086 1087 pasid = fpriv->vm.pasid; 1088 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1089 1090 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1091 amdgpu_vm_fini(adev, &fpriv->vm); 1092 1093 if (pasid) 1094 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1095 amdgpu_bo_unref(&pd); 1096 1097 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1098 amdgpu_bo_list_put(list); 1099 1100 idr_destroy(&fpriv->bo_list_handles); 1101 mutex_destroy(&fpriv->bo_list_lock); 1102 1103 kfree(fpriv); 1104 file_priv->driver_priv = NULL; 1105 1106 pm_runtime_mark_last_busy(dev->dev); 1107 pm_runtime_put_autosuspend(dev->dev); 1108 } 1109 1110 /* 1111 * VBlank related functions. 1112 */ 1113 /** 1114 * amdgpu_get_vblank_counter_kms - get frame count 1115 * 1116 * @crtc: crtc to get the frame count from 1117 * 1118 * Gets the frame count on the requested crtc (all asics). 1119 * Returns frame count on success, -EINVAL on failure. 1120 */ 1121 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1122 { 1123 struct drm_device *dev = crtc->dev; 1124 unsigned int pipe = crtc->index; 1125 struct amdgpu_device *adev = dev->dev_private; 1126 int vpos, hpos, stat; 1127 u32 count; 1128 1129 if (pipe >= adev->mode_info.num_crtc) { 1130 DRM_ERROR("Invalid crtc %u\n", pipe); 1131 return -EINVAL; 1132 } 1133 1134 /* The hw increments its frame counter at start of vsync, not at start 1135 * of vblank, as is required by DRM core vblank counter handling. 1136 * Cook the hw count here to make it appear to the caller as if it 1137 * incremented at start of vblank. We measure distance to start of 1138 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1139 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1140 * result by 1 to give the proper appearance to caller. 1141 */ 1142 if (adev->mode_info.crtcs[pipe]) { 1143 /* Repeat readout if needed to provide stable result if 1144 * we cross start of vsync during the queries. 1145 */ 1146 do { 1147 count = amdgpu_display_vblank_get_counter(adev, pipe); 1148 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1149 * vpos as distance to start of vblank, instead of 1150 * regular vertical scanout pos. 1151 */ 1152 stat = amdgpu_display_get_crtc_scanoutpos( 1153 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1154 &vpos, &hpos, NULL, NULL, 1155 &adev->mode_info.crtcs[pipe]->base.hwmode); 1156 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1157 1158 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1159 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1160 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1161 } else { 1162 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1163 pipe, vpos); 1164 1165 /* Bump counter if we are at >= leading edge of vblank, 1166 * but before vsync where vpos would turn negative and 1167 * the hw counter really increments. 1168 */ 1169 if (vpos >= 0) 1170 count++; 1171 } 1172 } else { 1173 /* Fallback to use value as is. */ 1174 count = amdgpu_display_vblank_get_counter(adev, pipe); 1175 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1176 } 1177 1178 return count; 1179 } 1180 1181 /** 1182 * amdgpu_enable_vblank_kms - enable vblank interrupt 1183 * 1184 * @crtc: crtc to enable vblank interrupt for 1185 * 1186 * Enable the interrupt on the requested crtc (all asics). 1187 * Returns 0 on success, -EINVAL on failure. 1188 */ 1189 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1190 { 1191 struct drm_device *dev = crtc->dev; 1192 unsigned int pipe = crtc->index; 1193 struct amdgpu_device *adev = dev->dev_private; 1194 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1195 1196 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1197 } 1198 1199 /** 1200 * amdgpu_disable_vblank_kms - disable vblank interrupt 1201 * 1202 * @crtc: crtc to disable vblank interrupt for 1203 * 1204 * Disable the interrupt on the requested crtc (all asics). 1205 */ 1206 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1207 { 1208 struct drm_device *dev = crtc->dev; 1209 unsigned int pipe = crtc->index; 1210 struct amdgpu_device *adev = dev->dev_private; 1211 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1212 1213 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1214 } 1215 1216 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1217 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1218 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1219 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1220 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1221 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1222 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1223 /* KMS */ 1224 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1225 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1226 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1227 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1228 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1229 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1230 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1231 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1232 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1233 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1234 }; 1235 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1236 1237 /* 1238 * Debugfs info 1239 */ 1240 #if defined(CONFIG_DEBUG_FS) 1241 1242 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1243 { 1244 struct drm_info_node *node = (struct drm_info_node *) m->private; 1245 struct drm_device *dev = node->minor->dev; 1246 struct amdgpu_device *adev = dev->dev_private; 1247 struct drm_amdgpu_info_firmware fw_info; 1248 struct drm_amdgpu_query_fw query_fw; 1249 struct atom_context *ctx = adev->mode_info.atom_context; 1250 int ret, i; 1251 1252 /* VCE */ 1253 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1254 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1255 if (ret) 1256 return ret; 1257 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1258 fw_info.feature, fw_info.ver); 1259 1260 /* UVD */ 1261 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1262 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1263 if (ret) 1264 return ret; 1265 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1266 fw_info.feature, fw_info.ver); 1267 1268 /* GMC */ 1269 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1270 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1271 if (ret) 1272 return ret; 1273 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1274 fw_info.feature, fw_info.ver); 1275 1276 /* ME */ 1277 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1278 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1279 if (ret) 1280 return ret; 1281 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1282 fw_info.feature, fw_info.ver); 1283 1284 /* PFP */ 1285 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1286 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1287 if (ret) 1288 return ret; 1289 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1290 fw_info.feature, fw_info.ver); 1291 1292 /* CE */ 1293 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1294 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1295 if (ret) 1296 return ret; 1297 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1298 fw_info.feature, fw_info.ver); 1299 1300 /* RLC */ 1301 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1302 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1303 if (ret) 1304 return ret; 1305 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1306 fw_info.feature, fw_info.ver); 1307 1308 /* RLC SAVE RESTORE LIST CNTL */ 1309 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1310 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1311 if (ret) 1312 return ret; 1313 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1314 fw_info.feature, fw_info.ver); 1315 1316 /* RLC SAVE RESTORE LIST GPM MEM */ 1317 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1318 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1319 if (ret) 1320 return ret; 1321 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1322 fw_info.feature, fw_info.ver); 1323 1324 /* RLC SAVE RESTORE LIST SRM MEM */ 1325 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1326 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1327 if (ret) 1328 return ret; 1329 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1330 fw_info.feature, fw_info.ver); 1331 1332 /* MEC */ 1333 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1334 query_fw.index = 0; 1335 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1336 if (ret) 1337 return ret; 1338 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1339 fw_info.feature, fw_info.ver); 1340 1341 /* MEC2 */ 1342 if (adev->asic_type == CHIP_KAVERI || 1343 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1344 query_fw.index = 1; 1345 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1346 if (ret) 1347 return ret; 1348 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1349 fw_info.feature, fw_info.ver); 1350 } 1351 1352 /* PSP SOS */ 1353 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1354 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1355 if (ret) 1356 return ret; 1357 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1358 fw_info.feature, fw_info.ver); 1359 1360 1361 /* PSP ASD */ 1362 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1363 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1364 if (ret) 1365 return ret; 1366 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1367 fw_info.feature, fw_info.ver); 1368 1369 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1370 for (i = 0; i < 2; i++) { 1371 query_fw.index = i; 1372 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1373 if (ret) 1374 continue; 1375 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1376 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1377 } 1378 1379 /* SMC */ 1380 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1381 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1382 if (ret) 1383 return ret; 1384 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1385 fw_info.feature, fw_info.ver); 1386 1387 /* SDMA */ 1388 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1389 for (i = 0; i < adev->sdma.num_instances; i++) { 1390 query_fw.index = i; 1391 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1392 if (ret) 1393 return ret; 1394 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1395 i, fw_info.feature, fw_info.ver); 1396 } 1397 1398 /* VCN */ 1399 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1400 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1401 if (ret) 1402 return ret; 1403 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1404 fw_info.feature, fw_info.ver); 1405 1406 /* DMCU */ 1407 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1408 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1409 if (ret) 1410 return ret; 1411 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1412 fw_info.feature, fw_info.ver); 1413 1414 /* DMCUB */ 1415 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1416 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1417 if (ret) 1418 return ret; 1419 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1420 fw_info.feature, fw_info.ver); 1421 1422 1423 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1424 1425 return 0; 1426 } 1427 1428 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1429 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1430 }; 1431 #endif 1432 1433 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1434 { 1435 #if defined(CONFIG_DEBUG_FS) 1436 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1437 ARRAY_SIZE(amdgpu_firmware_info_list)); 1438 #else 1439 return 0; 1440 #endif 1441 } 1442