1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 34 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 35 { 36 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 37 struct amdgpu_job *job = to_amdgpu_job(s_job); 38 struct amdgpu_task_info ti; 39 struct amdgpu_device *adev = ring->adev; 40 int idx; 41 int r; 42 43 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 44 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s", 45 __func__, s_job->sched->name); 46 47 /* Effectively the job is aborted as the device is gone */ 48 return DRM_GPU_SCHED_STAT_ENODEV; 49 } 50 51 memset(&ti, 0, sizeof(struct amdgpu_task_info)); 52 adev->job_hang = true; 53 54 if (amdgpu_gpu_recovery && 55 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 56 DRM_ERROR("ring %s timeout, but soft recovered\n", 57 s_job->sched->name); 58 goto exit; 59 } 60 61 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); 62 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n", 63 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 64 ring->fence_drv.sync_seq); 65 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n", 66 ti.process_name, ti.tgid, ti.task_name, ti.pid); 67 68 if (amdgpu_device_should_recover_gpu(ring->adev)) { 69 struct amdgpu_reset_context reset_context; 70 memset(&reset_context, 0, sizeof(reset_context)); 71 72 reset_context.method = AMD_RESET_METHOD_NONE; 73 reset_context.reset_req_dev = adev; 74 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 75 clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags); 76 77 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 78 if (r) 79 DRM_ERROR("GPU Recovery Failed: %d\n", r); 80 } else { 81 drm_sched_suspend_timeout(&ring->sched); 82 if (amdgpu_sriov_vf(adev)) 83 adev->virt.tdr_debug = true; 84 } 85 86 exit: 87 adev->job_hang = false; 88 drm_dev_exit(idx); 89 return DRM_GPU_SCHED_STAT_NOMINAL; 90 } 91 92 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 93 struct amdgpu_job **job, struct amdgpu_vm *vm) 94 { 95 if (num_ibs == 0) 96 return -EINVAL; 97 98 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 99 if (!*job) 100 return -ENOMEM; 101 102 /* 103 * Initialize the scheduler to at least some ring so that we always 104 * have a pointer to adev. 105 */ 106 (*job)->base.sched = &adev->rings[0]->sched; 107 (*job)->vm = vm; 108 109 amdgpu_sync_create(&(*job)->sync); 110 amdgpu_sync_create(&(*job)->sched_sync); 111 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 112 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 113 114 return 0; 115 } 116 117 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 118 enum amdgpu_ib_pool_type pool_type, 119 struct amdgpu_job **job) 120 { 121 int r; 122 123 r = amdgpu_job_alloc(adev, 1, job, NULL); 124 if (r) 125 return r; 126 127 (*job)->num_ibs = 1; 128 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 129 if (r) 130 kfree(*job); 131 132 return r; 133 } 134 135 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds, 136 struct amdgpu_bo *gws, struct amdgpu_bo *oa) 137 { 138 if (gds) { 139 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; 140 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; 141 } 142 if (gws) { 143 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT; 144 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT; 145 } 146 if (oa) { 147 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT; 148 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT; 149 } 150 } 151 152 void amdgpu_job_free_resources(struct amdgpu_job *job) 153 { 154 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 155 struct dma_fence *f; 156 unsigned i; 157 158 /* use sched fence if available */ 159 f = job->base.s_fence ? &job->base.s_fence->finished : &job->hw_fence; 160 for (i = 0; i < job->num_ibs; ++i) 161 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 162 } 163 164 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 165 { 166 struct amdgpu_job *job = to_amdgpu_job(s_job); 167 168 drm_sched_job_cleanup(s_job); 169 170 amdgpu_sync_free(&job->sync); 171 amdgpu_sync_free(&job->sched_sync); 172 173 dma_fence_put(&job->hw_fence); 174 } 175 176 void amdgpu_job_set_gang_leader(struct amdgpu_job *job, 177 struct amdgpu_job *leader) 178 { 179 struct dma_fence *fence = &leader->base.s_fence->scheduled; 180 181 WARN_ON(job->gang_submit); 182 183 /* 184 * Don't add a reference when we are the gang leader to avoid circle 185 * dependency. 186 */ 187 if (job != leader) 188 dma_fence_get(fence); 189 job->gang_submit = fence; 190 } 191 192 void amdgpu_job_free(struct amdgpu_job *job) 193 { 194 amdgpu_job_free_resources(job); 195 amdgpu_sync_free(&job->sync); 196 amdgpu_sync_free(&job->sched_sync); 197 if (job->gang_submit != &job->base.s_fence->scheduled) 198 dma_fence_put(job->gang_submit); 199 200 if (!job->hw_fence.ops) 201 kfree(job); 202 else 203 dma_fence_put(&job->hw_fence); 204 } 205 206 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 207 void *owner, struct dma_fence **f) 208 { 209 int r; 210 211 if (!f) 212 return -EINVAL; 213 214 r = drm_sched_job_init(&job->base, entity, owner); 215 if (r) 216 return r; 217 218 drm_sched_job_arm(&job->base); 219 220 *f = dma_fence_get(&job->base.s_fence->finished); 221 amdgpu_job_free_resources(job); 222 drm_sched_entity_push_job(&job->base); 223 224 return 0; 225 } 226 227 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 228 struct dma_fence **fence) 229 { 230 int r; 231 232 job->base.sched = &ring->sched; 233 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 234 235 if (r) 236 return r; 237 238 amdgpu_job_free(job); 239 return 0; 240 } 241 242 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, 243 struct drm_sched_entity *s_entity) 244 { 245 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 246 struct amdgpu_job *job = to_amdgpu_job(sched_job); 247 struct amdgpu_vm *vm = job->vm; 248 struct dma_fence *fence; 249 int r; 250 251 fence = amdgpu_sync_get_fence(&job->sync); 252 if (fence && drm_sched_dependency_optimized(fence, s_entity)) { 253 r = amdgpu_sync_fence(&job->sched_sync, fence); 254 if (r) 255 DRM_ERROR("Error adding fence (%d)\n", r); 256 } 257 258 while (fence == NULL && vm && !job->vmid) { 259 r = amdgpu_vmid_grab(vm, ring, &job->sync, 260 &job->base.s_fence->finished, 261 job); 262 if (r) 263 DRM_ERROR("Error getting VM ID (%d)\n", r); 264 265 fence = amdgpu_sync_get_fence(&job->sync); 266 } 267 268 if (!fence && job->gang_submit) 269 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit); 270 271 return fence; 272 } 273 274 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 275 { 276 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 277 struct amdgpu_device *adev = ring->adev; 278 struct dma_fence *fence = NULL, *finished; 279 struct amdgpu_job *job; 280 int r = 0; 281 282 job = to_amdgpu_job(sched_job); 283 finished = &job->base.s_fence->finished; 284 285 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); 286 287 trace_amdgpu_sched_run_job(job); 288 289 /* Skip job if VRAM is lost and never resubmit gangs */ 290 if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) || 291 (job->job_run_counter && job->gang_submit)) 292 dma_fence_set_error(finished, -ECANCELED); 293 294 if (finished->error < 0) { 295 DRM_INFO("Skip scheduling IBs!\n"); 296 } else { 297 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 298 &fence); 299 if (r) 300 DRM_ERROR("Error scheduling IBs (%d)\n", r); 301 } 302 303 job->job_run_counter++; 304 amdgpu_job_free_resources(job); 305 306 fence = r ? ERR_PTR(r) : fence; 307 return fence; 308 } 309 310 #define to_drm_sched_job(sched_job) \ 311 container_of((sched_job), struct drm_sched_job, queue_node) 312 313 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 314 { 315 struct drm_sched_job *s_job; 316 struct drm_sched_entity *s_entity = NULL; 317 int i; 318 319 /* Signal all jobs not yet scheduled */ 320 for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { 321 struct drm_sched_rq *rq = &sched->sched_rq[i]; 322 spin_lock(&rq->lock); 323 list_for_each_entry(s_entity, &rq->entities, list) { 324 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 325 struct drm_sched_fence *s_fence = s_job->s_fence; 326 327 dma_fence_signal(&s_fence->scheduled); 328 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 329 dma_fence_signal(&s_fence->finished); 330 } 331 } 332 spin_unlock(&rq->lock); 333 } 334 335 /* Signal all jobs already scheduled to HW */ 336 list_for_each_entry(s_job, &sched->pending_list, list) { 337 struct drm_sched_fence *s_fence = s_job->s_fence; 338 339 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 340 dma_fence_signal(&s_fence->finished); 341 } 342 } 343 344 const struct drm_sched_backend_ops amdgpu_sched_ops = { 345 .dependency = amdgpu_job_dependency, 346 .run_job = amdgpu_job_run, 347 .timedout_job = amdgpu_job_timedout, 348 .free_job = amdgpu_job_free_cb 349 }; 350