1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #include <linux/kthread.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 
28 #include "amdgpu.h"
29 #include "amdgpu_trace.h"
30 
31 static void amdgpu_job_timedout(struct drm_sched_job *s_job)
32 {
33 	struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
34 	struct amdgpu_job *job = to_amdgpu_job(s_job);
35 	struct amdgpu_task_info ti;
36 	struct amdgpu_device *adev = ring->adev;
37 
38 	memset(&ti, 0, sizeof(struct amdgpu_task_info));
39 
40 	if (amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
41 		DRM_ERROR("ring %s timeout, but soft recovered\n",
42 			  s_job->sched->name);
43 		return;
44 	}
45 
46 	amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
47 	DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
48 		  job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
49 		  ring->fence_drv.sync_seq);
50 	DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
51 		  ti.process_name, ti.tgid, ti.task_name, ti.pid);
52 
53 	if (amdgpu_device_should_recover_gpu(ring->adev)) {
54 		amdgpu_device_gpu_recover(ring->adev, job);
55 	} else {
56 		drm_sched_suspend_timeout(&ring->sched);
57 		if (amdgpu_sriov_vf(adev))
58 			adev->virt.tdr_debug = true;
59 	}
60 }
61 
62 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
63 		     struct amdgpu_job **job, struct amdgpu_vm *vm)
64 {
65 	size_t size = sizeof(struct amdgpu_job);
66 
67 	if (num_ibs == 0)
68 		return -EINVAL;
69 
70 	size += sizeof(struct amdgpu_ib) * num_ibs;
71 
72 	*job = kzalloc(size, GFP_KERNEL);
73 	if (!*job)
74 		return -ENOMEM;
75 
76 	/*
77 	 * Initialize the scheduler to at least some ring so that we always
78 	 * have a pointer to adev.
79 	 */
80 	(*job)->base.sched = &adev->rings[0]->sched;
81 	(*job)->vm = vm;
82 	(*job)->ibs = (void *)&(*job)[1];
83 	(*job)->num_ibs = num_ibs;
84 
85 	amdgpu_sync_create(&(*job)->sync);
86 	amdgpu_sync_create(&(*job)->sched_sync);
87 	(*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
88 	(*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
89 
90 	return 0;
91 }
92 
93 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
94 		enum amdgpu_ib_pool_type pool_type,
95 		struct amdgpu_job **job)
96 {
97 	int r;
98 
99 	r = amdgpu_job_alloc(adev, 1, job, NULL);
100 	if (r)
101 		return r;
102 
103 	r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
104 	if (r)
105 		kfree(*job);
106 
107 	return r;
108 }
109 
110 void amdgpu_job_free_resources(struct amdgpu_job *job)
111 {
112 	struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
113 	struct dma_fence *f;
114 	unsigned i;
115 
116 	/* use sched fence if available */
117 	f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
118 
119 	for (i = 0; i < job->num_ibs; ++i)
120 		amdgpu_ib_free(ring->adev, &job->ibs[i], f);
121 }
122 
123 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
124 {
125 	struct amdgpu_job *job = to_amdgpu_job(s_job);
126 
127 	drm_sched_job_cleanup(s_job);
128 
129 	dma_fence_put(job->fence);
130 	amdgpu_sync_free(&job->sync);
131 	amdgpu_sync_free(&job->sched_sync);
132 	kfree(job);
133 }
134 
135 void amdgpu_job_free(struct amdgpu_job *job)
136 {
137 	amdgpu_job_free_resources(job);
138 
139 	dma_fence_put(job->fence);
140 	amdgpu_sync_free(&job->sync);
141 	amdgpu_sync_free(&job->sched_sync);
142 	kfree(job);
143 }
144 
145 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
146 		      void *owner, struct dma_fence **f)
147 {
148 	enum drm_sched_priority priority;
149 	int r;
150 
151 	if (!f)
152 		return -EINVAL;
153 
154 	r = drm_sched_job_init(&job->base, entity, owner);
155 	if (r)
156 		return r;
157 
158 	*f = dma_fence_get(&job->base.s_fence->finished);
159 	amdgpu_job_free_resources(job);
160 	priority = job->base.s_priority;
161 	drm_sched_entity_push_job(&job->base, entity);
162 
163 	return 0;
164 }
165 
166 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
167 			     struct dma_fence **fence)
168 {
169 	int r;
170 
171 	job->base.sched = &ring->sched;
172 	r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence);
173 	job->fence = dma_fence_get(*fence);
174 	if (r)
175 		return r;
176 
177 	amdgpu_job_free(job);
178 	return 0;
179 }
180 
181 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
182 					       struct drm_sched_entity *s_entity)
183 {
184 	struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
185 	struct amdgpu_job *job = to_amdgpu_job(sched_job);
186 	struct amdgpu_vm *vm = job->vm;
187 	struct dma_fence *fence;
188 	bool explicit = false;
189 	int r;
190 
191 	fence = amdgpu_sync_get_fence(&job->sync, &explicit);
192 	if (fence && explicit) {
193 		if (drm_sched_dependency_optimized(fence, s_entity)) {
194 			r = amdgpu_sync_fence(&job->sched_sync, fence, false);
195 			if (r)
196 				DRM_ERROR("Error adding fence (%d)\n", r);
197 		}
198 	}
199 
200 	while (fence == NULL && vm && !job->vmid) {
201 		r = amdgpu_vmid_grab(vm, ring, &job->sync,
202 				     &job->base.s_fence->finished,
203 				     job);
204 		if (r)
205 			DRM_ERROR("Error getting VM ID (%d)\n", r);
206 
207 		fence = amdgpu_sync_get_fence(&job->sync, NULL);
208 	}
209 
210 	return fence;
211 }
212 
213 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
214 {
215 	struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
216 	struct dma_fence *fence = NULL, *finished;
217 	struct amdgpu_job *job;
218 	int r = 0;
219 
220 	job = to_amdgpu_job(sched_job);
221 	finished = &job->base.s_fence->finished;
222 
223 	BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
224 
225 	trace_amdgpu_sched_run_job(job);
226 
227 	if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter))
228 		dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
229 
230 	if (finished->error < 0) {
231 		DRM_INFO("Skip scheduling IBs!\n");
232 	} else {
233 		r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
234 				       &fence);
235 		if (r)
236 			DRM_ERROR("Error scheduling IBs (%d)\n", r);
237 	}
238 	/* if gpu reset, hw fence will be replaced here */
239 	dma_fence_put(job->fence);
240 	job->fence = dma_fence_get(fence);
241 
242 	amdgpu_job_free_resources(job);
243 
244 	fence = r ? ERR_PTR(r) : fence;
245 	return fence;
246 }
247 
248 #define to_drm_sched_job(sched_job)		\
249 		container_of((sched_job), struct drm_sched_job, queue_node)
250 
251 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
252 {
253 	struct drm_sched_job *s_job;
254 	struct drm_sched_entity *s_entity = NULL;
255 	int i;
256 
257 	/* Signal all jobs not yet scheduled */
258 	for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
259 		struct drm_sched_rq *rq = &sched->sched_rq[i];
260 
261 		if (!rq)
262 			continue;
263 
264 		spin_lock(&rq->lock);
265 		list_for_each_entry(s_entity, &rq->entities, list) {
266 			while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
267 				struct drm_sched_fence *s_fence = s_job->s_fence;
268 
269 				dma_fence_signal(&s_fence->scheduled);
270 				dma_fence_set_error(&s_fence->finished, -EHWPOISON);
271 				dma_fence_signal(&s_fence->finished);
272 			}
273 		}
274 		spin_unlock(&rq->lock);
275 	}
276 
277 	/* Signal all jobs already scheduled to HW */
278 	list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
279 		struct drm_sched_fence *s_fence = s_job->s_fence;
280 
281 		dma_fence_set_error(&s_fence->finished, -EHWPOISON);
282 		dma_fence_signal(&s_fence->finished);
283 	}
284 }
285 
286 const struct drm_sched_backend_ops amdgpu_sched_ops = {
287 	.dependency = amdgpu_job_dependency,
288 	.run_job = amdgpu_job_run,
289 	.timedout_job = amdgpu_job_timedout,
290 	.free_job = amdgpu_job_free_cb
291 };
292