1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 33 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 34 { 35 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 36 struct amdgpu_job *job = to_amdgpu_job(s_job); 37 struct amdgpu_task_info ti; 38 struct amdgpu_device *adev = ring->adev; 39 int idx; 40 int r; 41 42 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 43 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s", 44 __func__, s_job->sched->name); 45 46 /* Effectively the job is aborted as the device is gone */ 47 return DRM_GPU_SCHED_STAT_ENODEV; 48 } 49 50 memset(&ti, 0, sizeof(struct amdgpu_task_info)); 51 52 if (amdgpu_gpu_recovery && 53 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 54 DRM_ERROR("ring %s timeout, but soft recovered\n", 55 s_job->sched->name); 56 goto exit; 57 } 58 59 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); 60 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n", 61 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 62 ring->fence_drv.sync_seq); 63 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n", 64 ti.process_name, ti.tgid, ti.task_name, ti.pid); 65 66 if (amdgpu_device_should_recover_gpu(ring->adev)) { 67 r = amdgpu_device_gpu_recover(ring->adev, job); 68 if (r) 69 DRM_ERROR("GPU Recovery Failed: %d\n", r); 70 71 } else { 72 drm_sched_suspend_timeout(&ring->sched); 73 if (amdgpu_sriov_vf(adev)) 74 adev->virt.tdr_debug = true; 75 } 76 77 exit: 78 drm_dev_exit(idx); 79 return DRM_GPU_SCHED_STAT_NOMINAL; 80 } 81 82 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 83 struct amdgpu_job **job, struct amdgpu_vm *vm) 84 { 85 size_t size = sizeof(struct amdgpu_job); 86 87 if (num_ibs == 0) 88 return -EINVAL; 89 90 size += sizeof(struct amdgpu_ib) * num_ibs; 91 92 *job = kzalloc(size, GFP_KERNEL); 93 if (!*job) 94 return -ENOMEM; 95 96 /* 97 * Initialize the scheduler to at least some ring so that we always 98 * have a pointer to adev. 99 */ 100 (*job)->base.sched = &adev->rings[0]->sched; 101 (*job)->vm = vm; 102 (*job)->ibs = (void *)&(*job)[1]; 103 (*job)->num_ibs = num_ibs; 104 105 amdgpu_sync_create(&(*job)->sync); 106 amdgpu_sync_create(&(*job)->sched_sync); 107 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 108 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 109 110 return 0; 111 } 112 113 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 114 enum amdgpu_ib_pool_type pool_type, 115 struct amdgpu_job **job) 116 { 117 int r; 118 119 r = amdgpu_job_alloc(adev, 1, job, NULL); 120 if (r) 121 return r; 122 123 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 124 if (r) 125 kfree(*job); 126 127 return r; 128 } 129 130 void amdgpu_job_free_resources(struct amdgpu_job *job) 131 { 132 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 133 struct dma_fence *f; 134 struct dma_fence *hw_fence; 135 unsigned i; 136 137 if (job->hw_fence.ops == NULL) 138 hw_fence = job->external_hw_fence; 139 else 140 hw_fence = &job->hw_fence; 141 142 /* use sched fence if available */ 143 f = job->base.s_fence ? &job->base.s_fence->finished : hw_fence; 144 for (i = 0; i < job->num_ibs; ++i) 145 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 146 } 147 148 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 149 { 150 struct amdgpu_job *job = to_amdgpu_job(s_job); 151 152 drm_sched_job_cleanup(s_job); 153 154 amdgpu_sync_free(&job->sync); 155 amdgpu_sync_free(&job->sched_sync); 156 157 /* only put the hw fence if has embedded fence */ 158 if (job->hw_fence.ops != NULL) 159 dma_fence_put(&job->hw_fence); 160 else 161 kfree(job); 162 } 163 164 void amdgpu_job_free(struct amdgpu_job *job) 165 { 166 amdgpu_job_free_resources(job); 167 amdgpu_sync_free(&job->sync); 168 amdgpu_sync_free(&job->sched_sync); 169 170 /* only put the hw fence if has embedded fence */ 171 if (job->hw_fence.ops != NULL) 172 dma_fence_put(&job->hw_fence); 173 else 174 kfree(job); 175 } 176 177 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 178 void *owner, struct dma_fence **f) 179 { 180 int r; 181 182 if (!f) 183 return -EINVAL; 184 185 r = drm_sched_job_init(&job->base, entity, owner); 186 if (r) 187 return r; 188 189 drm_sched_job_arm(&job->base); 190 191 *f = dma_fence_get(&job->base.s_fence->finished); 192 amdgpu_job_free_resources(job); 193 drm_sched_entity_push_job(&job->base); 194 195 return 0; 196 } 197 198 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 199 struct dma_fence **fence) 200 { 201 int r; 202 203 job->base.sched = &ring->sched; 204 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence); 205 /* record external_hw_fence for direct submit */ 206 job->external_hw_fence = dma_fence_get(*fence); 207 if (r) 208 return r; 209 210 amdgpu_job_free(job); 211 dma_fence_put(*fence); 212 213 return 0; 214 } 215 216 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, 217 struct drm_sched_entity *s_entity) 218 { 219 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 220 struct amdgpu_job *job = to_amdgpu_job(sched_job); 221 struct amdgpu_vm *vm = job->vm; 222 struct dma_fence *fence; 223 int r; 224 225 fence = amdgpu_sync_get_fence(&job->sync); 226 if (fence && drm_sched_dependency_optimized(fence, s_entity)) { 227 r = amdgpu_sync_fence(&job->sched_sync, fence); 228 if (r) 229 DRM_ERROR("Error adding fence (%d)\n", r); 230 } 231 232 while (fence == NULL && vm && !job->vmid) { 233 r = amdgpu_vmid_grab(vm, ring, &job->sync, 234 &job->base.s_fence->finished, 235 job); 236 if (r) 237 DRM_ERROR("Error getting VM ID (%d)\n", r); 238 239 fence = amdgpu_sync_get_fence(&job->sync); 240 } 241 242 return fence; 243 } 244 245 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 246 { 247 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 248 struct dma_fence *fence = NULL, *finished; 249 struct amdgpu_job *job; 250 int r = 0; 251 252 job = to_amdgpu_job(sched_job); 253 finished = &job->base.s_fence->finished; 254 255 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); 256 257 trace_amdgpu_sched_run_job(job); 258 259 if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter)) 260 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ 261 262 if (finished->error < 0) { 263 DRM_INFO("Skip scheduling IBs!\n"); 264 } else { 265 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 266 &fence); 267 if (r) 268 DRM_ERROR("Error scheduling IBs (%d)\n", r); 269 } 270 271 if (!job->job_run_counter) 272 dma_fence_get(fence); 273 else if (finished->error < 0) 274 dma_fence_put(&job->hw_fence); 275 job->job_run_counter++; 276 amdgpu_job_free_resources(job); 277 278 fence = r ? ERR_PTR(r) : fence; 279 return fence; 280 } 281 282 #define to_drm_sched_job(sched_job) \ 283 container_of((sched_job), struct drm_sched_job, queue_node) 284 285 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 286 { 287 struct drm_sched_job *s_job; 288 struct drm_sched_entity *s_entity = NULL; 289 int i; 290 291 /* Signal all jobs not yet scheduled */ 292 for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { 293 struct drm_sched_rq *rq = &sched->sched_rq[i]; 294 295 if (!rq) 296 continue; 297 298 spin_lock(&rq->lock); 299 list_for_each_entry(s_entity, &rq->entities, list) { 300 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 301 struct drm_sched_fence *s_fence = s_job->s_fence; 302 303 dma_fence_signal(&s_fence->scheduled); 304 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 305 dma_fence_signal(&s_fence->finished); 306 } 307 } 308 spin_unlock(&rq->lock); 309 } 310 311 /* Signal all jobs already scheduled to HW */ 312 list_for_each_entry(s_job, &sched->pending_list, list) { 313 struct drm_sched_fence *s_fence = s_job->s_fence; 314 315 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 316 dma_fence_signal(&s_fence->finished); 317 } 318 } 319 320 const struct drm_sched_backend_ops amdgpu_sched_ops = { 321 .dependency = amdgpu_job_dependency, 322 .run_job = amdgpu_job_run, 323 .timedout_job = amdgpu_job_timedout, 324 .free_job = amdgpu_job_free_cb 325 }; 326