1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 34 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 35 { 36 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 37 struct amdgpu_job *job = to_amdgpu_job(s_job); 38 struct amdgpu_task_info ti; 39 struct amdgpu_device *adev = ring->adev; 40 int idx; 41 int r; 42 43 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 44 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s", 45 __func__, s_job->sched->name); 46 47 /* Effectively the job is aborted as the device is gone */ 48 return DRM_GPU_SCHED_STAT_ENODEV; 49 } 50 51 memset(&ti, 0, sizeof(struct amdgpu_task_info)); 52 53 if (amdgpu_gpu_recovery && 54 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 55 DRM_ERROR("ring %s timeout, but soft recovered\n", 56 s_job->sched->name); 57 goto exit; 58 } 59 60 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); 61 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n", 62 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 63 ring->fence_drv.sync_seq); 64 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n", 65 ti.process_name, ti.tgid, ti.task_name, ti.pid); 66 67 if (amdgpu_device_should_recover_gpu(ring->adev)) { 68 struct amdgpu_reset_context reset_context; 69 memset(&reset_context, 0, sizeof(reset_context)); 70 71 reset_context.method = AMD_RESET_METHOD_NONE; 72 reset_context.reset_req_dev = adev; 73 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 74 75 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 76 if (r) 77 DRM_ERROR("GPU Recovery Failed: %d\n", r); 78 } else { 79 drm_sched_suspend_timeout(&ring->sched); 80 if (amdgpu_sriov_vf(adev)) 81 adev->virt.tdr_debug = true; 82 } 83 84 exit: 85 drm_dev_exit(idx); 86 return DRM_GPU_SCHED_STAT_NOMINAL; 87 } 88 89 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 90 struct amdgpu_job **job, struct amdgpu_vm *vm) 91 { 92 if (num_ibs == 0) 93 return -EINVAL; 94 95 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 96 if (!*job) 97 return -ENOMEM; 98 99 /* 100 * Initialize the scheduler to at least some ring so that we always 101 * have a pointer to adev. 102 */ 103 (*job)->base.sched = &adev->rings[0]->sched; 104 (*job)->vm = vm; 105 (*job)->num_ibs = num_ibs; 106 107 amdgpu_sync_create(&(*job)->sync); 108 amdgpu_sync_create(&(*job)->sched_sync); 109 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 110 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 111 112 return 0; 113 } 114 115 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 116 enum amdgpu_ib_pool_type pool_type, 117 struct amdgpu_job **job) 118 { 119 int r; 120 121 r = amdgpu_job_alloc(adev, 1, job, NULL); 122 if (r) 123 return r; 124 125 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 126 if (r) 127 kfree(*job); 128 129 return r; 130 } 131 132 void amdgpu_job_free_resources(struct amdgpu_job *job) 133 { 134 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 135 struct dma_fence *f; 136 unsigned i; 137 138 /* use sched fence if available */ 139 f = job->base.s_fence ? &job->base.s_fence->finished : &job->hw_fence; 140 for (i = 0; i < job->num_ibs; ++i) 141 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 142 } 143 144 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 145 { 146 struct amdgpu_job *job = to_amdgpu_job(s_job); 147 148 drm_sched_job_cleanup(s_job); 149 150 amdgpu_sync_free(&job->sync); 151 amdgpu_sync_free(&job->sched_sync); 152 153 dma_fence_put(&job->hw_fence); 154 } 155 156 void amdgpu_job_free(struct amdgpu_job *job) 157 { 158 amdgpu_job_free_resources(job); 159 amdgpu_sync_free(&job->sync); 160 amdgpu_sync_free(&job->sched_sync); 161 162 if (!job->hw_fence.ops) 163 kfree(job); 164 else 165 dma_fence_put(&job->hw_fence); 166 } 167 168 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 169 void *owner, struct dma_fence **f) 170 { 171 int r; 172 173 if (!f) 174 return -EINVAL; 175 176 r = drm_sched_job_init(&job->base, entity, owner); 177 if (r) 178 return r; 179 180 drm_sched_job_arm(&job->base); 181 182 *f = dma_fence_get(&job->base.s_fence->finished); 183 amdgpu_job_free_resources(job); 184 drm_sched_entity_push_job(&job->base); 185 186 return 0; 187 } 188 189 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 190 struct dma_fence **fence) 191 { 192 int r; 193 194 job->base.sched = &ring->sched; 195 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence); 196 197 if (r) 198 return r; 199 200 amdgpu_job_free(job); 201 return 0; 202 } 203 204 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, 205 struct drm_sched_entity *s_entity) 206 { 207 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 208 struct amdgpu_job *job = to_amdgpu_job(sched_job); 209 struct amdgpu_vm *vm = job->vm; 210 struct dma_fence *fence; 211 int r; 212 213 fence = amdgpu_sync_get_fence(&job->sync); 214 if (fence && drm_sched_dependency_optimized(fence, s_entity)) { 215 r = amdgpu_sync_fence(&job->sched_sync, fence); 216 if (r) 217 DRM_ERROR("Error adding fence (%d)\n", r); 218 } 219 220 while (fence == NULL && vm && !job->vmid) { 221 r = amdgpu_vmid_grab(vm, ring, &job->sync, 222 &job->base.s_fence->finished, 223 job); 224 if (r) 225 DRM_ERROR("Error getting VM ID (%d)\n", r); 226 227 fence = amdgpu_sync_get_fence(&job->sync); 228 } 229 230 return fence; 231 } 232 233 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 234 { 235 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 236 struct dma_fence *fence = NULL, *finished; 237 struct amdgpu_job *job; 238 int r = 0; 239 240 job = to_amdgpu_job(sched_job); 241 finished = &job->base.s_fence->finished; 242 243 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); 244 245 trace_amdgpu_sched_run_job(job); 246 247 if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter)) 248 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ 249 250 if (finished->error < 0) { 251 DRM_INFO("Skip scheduling IBs!\n"); 252 } else { 253 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 254 &fence); 255 if (r) 256 DRM_ERROR("Error scheduling IBs (%d)\n", r); 257 } 258 259 job->job_run_counter++; 260 amdgpu_job_free_resources(job); 261 262 fence = r ? ERR_PTR(r) : fence; 263 return fence; 264 } 265 266 #define to_drm_sched_job(sched_job) \ 267 container_of((sched_job), struct drm_sched_job, queue_node) 268 269 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 270 { 271 struct drm_sched_job *s_job; 272 struct drm_sched_entity *s_entity = NULL; 273 int i; 274 275 /* Signal all jobs not yet scheduled */ 276 for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { 277 struct drm_sched_rq *rq = &sched->sched_rq[i]; 278 spin_lock(&rq->lock); 279 list_for_each_entry(s_entity, &rq->entities, list) { 280 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 281 struct drm_sched_fence *s_fence = s_job->s_fence; 282 283 dma_fence_signal(&s_fence->scheduled); 284 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 285 dma_fence_signal(&s_fence->finished); 286 } 287 } 288 spin_unlock(&rq->lock); 289 } 290 291 /* Signal all jobs already scheduled to HW */ 292 list_for_each_entry(s_job, &sched->pending_list, list) { 293 struct drm_sched_fence *s_fence = s_job->s_fence; 294 295 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 296 dma_fence_signal(&s_fence->finished); 297 } 298 } 299 300 const struct drm_sched_backend_ops amdgpu_sched_ops = { 301 .dependency = amdgpu_job_dependency, 302 .run_job = amdgpu_job_run, 303 .timedout_job = amdgpu_job_timedout, 304 .free_job = amdgpu_job_free_cb 305 }; 306