1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 #include "amdgpu_reset.h" 33 34 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) 35 { 36 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 37 struct amdgpu_job *job = to_amdgpu_job(s_job); 38 struct amdgpu_task_info ti; 39 struct amdgpu_device *adev = ring->adev; 40 int idx; 41 int r; 42 43 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { 44 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s", 45 __func__, s_job->sched->name); 46 47 /* Effectively the job is aborted as the device is gone */ 48 return DRM_GPU_SCHED_STAT_ENODEV; 49 } 50 51 memset(&ti, 0, sizeof(struct amdgpu_task_info)); 52 53 if (amdgpu_gpu_recovery && 54 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 55 DRM_ERROR("ring %s timeout, but soft recovered\n", 56 s_job->sched->name); 57 goto exit; 58 } 59 60 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); 61 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n", 62 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 63 ring->fence_drv.sync_seq); 64 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n", 65 ti.process_name, ti.tgid, ti.task_name, ti.pid); 66 67 if (amdgpu_device_should_recover_gpu(ring->adev)) { 68 struct amdgpu_reset_context reset_context; 69 memset(&reset_context, 0, sizeof(reset_context)); 70 71 reset_context.method = AMD_RESET_METHOD_NONE; 72 reset_context.reset_req_dev = adev; 73 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 74 75 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); 76 if (r) 77 DRM_ERROR("GPU Recovery Failed: %d\n", r); 78 } else { 79 drm_sched_suspend_timeout(&ring->sched); 80 if (amdgpu_sriov_vf(adev)) 81 adev->virt.tdr_debug = true; 82 } 83 84 exit: 85 drm_dev_exit(idx); 86 return DRM_GPU_SCHED_STAT_NOMINAL; 87 } 88 89 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 90 struct amdgpu_job **job, struct amdgpu_vm *vm) 91 { 92 if (num_ibs == 0) 93 return -EINVAL; 94 95 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL); 96 if (!*job) 97 return -ENOMEM; 98 99 /* 100 * Initialize the scheduler to at least some ring so that we always 101 * have a pointer to adev. 102 */ 103 (*job)->base.sched = &adev->rings[0]->sched; 104 (*job)->vm = vm; 105 (*job)->num_ibs = num_ibs; 106 107 amdgpu_sync_create(&(*job)->sync); 108 amdgpu_sync_create(&(*job)->sched_sync); 109 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 110 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 111 112 return 0; 113 } 114 115 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 116 enum amdgpu_ib_pool_type pool_type, 117 struct amdgpu_job **job) 118 { 119 int r; 120 121 r = amdgpu_job_alloc(adev, 1, job, NULL); 122 if (r) 123 return r; 124 125 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]); 126 if (r) 127 kfree(*job); 128 129 return r; 130 } 131 132 void amdgpu_job_free_resources(struct amdgpu_job *job) 133 { 134 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 135 struct dma_fence *f; 136 struct dma_fence *hw_fence; 137 unsigned i; 138 139 if (job->hw_fence.ops == NULL) 140 hw_fence = job->external_hw_fence; 141 else 142 hw_fence = &job->hw_fence; 143 144 /* use sched fence if available */ 145 f = job->base.s_fence ? &job->base.s_fence->finished : hw_fence; 146 for (i = 0; i < job->num_ibs; ++i) 147 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 148 } 149 150 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 151 { 152 struct amdgpu_job *job = to_amdgpu_job(s_job); 153 154 drm_sched_job_cleanup(s_job); 155 156 amdgpu_sync_free(&job->sync); 157 amdgpu_sync_free(&job->sched_sync); 158 159 /* only put the hw fence if has embedded fence */ 160 if (job->hw_fence.ops != NULL) 161 dma_fence_put(&job->hw_fence); 162 else 163 kfree(job); 164 } 165 166 void amdgpu_job_free(struct amdgpu_job *job) 167 { 168 amdgpu_job_free_resources(job); 169 amdgpu_sync_free(&job->sync); 170 amdgpu_sync_free(&job->sched_sync); 171 172 /* only put the hw fence if has embedded fence */ 173 if (job->hw_fence.ops != NULL) 174 dma_fence_put(&job->hw_fence); 175 else 176 kfree(job); 177 } 178 179 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 180 void *owner, struct dma_fence **f) 181 { 182 int r; 183 184 if (!f) 185 return -EINVAL; 186 187 r = drm_sched_job_init(&job->base, entity, owner); 188 if (r) 189 return r; 190 191 drm_sched_job_arm(&job->base); 192 193 *f = dma_fence_get(&job->base.s_fence->finished); 194 amdgpu_job_free_resources(job); 195 drm_sched_entity_push_job(&job->base); 196 197 return 0; 198 } 199 200 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 201 struct dma_fence **fence) 202 { 203 int r; 204 205 job->base.sched = &ring->sched; 206 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence); 207 /* record external_hw_fence for direct submit */ 208 job->external_hw_fence = dma_fence_get(*fence); 209 if (r) 210 return r; 211 212 amdgpu_job_free(job); 213 dma_fence_put(*fence); 214 215 return 0; 216 } 217 218 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, 219 struct drm_sched_entity *s_entity) 220 { 221 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 222 struct amdgpu_job *job = to_amdgpu_job(sched_job); 223 struct amdgpu_vm *vm = job->vm; 224 struct dma_fence *fence; 225 int r; 226 227 fence = amdgpu_sync_get_fence(&job->sync); 228 if (fence && drm_sched_dependency_optimized(fence, s_entity)) { 229 r = amdgpu_sync_fence(&job->sched_sync, fence); 230 if (r) 231 DRM_ERROR("Error adding fence (%d)\n", r); 232 } 233 234 while (fence == NULL && vm && !job->vmid) { 235 r = amdgpu_vmid_grab(vm, ring, &job->sync, 236 &job->base.s_fence->finished, 237 job); 238 if (r) 239 DRM_ERROR("Error getting VM ID (%d)\n", r); 240 241 fence = amdgpu_sync_get_fence(&job->sync); 242 } 243 244 return fence; 245 } 246 247 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 248 { 249 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 250 struct dma_fence *fence = NULL, *finished; 251 struct amdgpu_job *job; 252 int r = 0; 253 254 job = to_amdgpu_job(sched_job); 255 finished = &job->base.s_fence->finished; 256 257 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); 258 259 trace_amdgpu_sched_run_job(job); 260 261 if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter)) 262 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ 263 264 if (finished->error < 0) { 265 DRM_INFO("Skip scheduling IBs!\n"); 266 } else { 267 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 268 &fence); 269 if (r) 270 DRM_ERROR("Error scheduling IBs (%d)\n", r); 271 } 272 273 job->job_run_counter++; 274 amdgpu_job_free_resources(job); 275 276 fence = r ? ERR_PTR(r) : fence; 277 return fence; 278 } 279 280 #define to_drm_sched_job(sched_job) \ 281 container_of((sched_job), struct drm_sched_job, queue_node) 282 283 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 284 { 285 struct drm_sched_job *s_job; 286 struct drm_sched_entity *s_entity = NULL; 287 int i; 288 289 /* Signal all jobs not yet scheduled */ 290 for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { 291 struct drm_sched_rq *rq = &sched->sched_rq[i]; 292 293 if (!rq) 294 continue; 295 296 spin_lock(&rq->lock); 297 list_for_each_entry(s_entity, &rq->entities, list) { 298 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 299 struct drm_sched_fence *s_fence = s_job->s_fence; 300 301 dma_fence_signal(&s_fence->scheduled); 302 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 303 dma_fence_signal(&s_fence->finished); 304 } 305 } 306 spin_unlock(&rq->lock); 307 } 308 309 /* Signal all jobs already scheduled to HW */ 310 list_for_each_entry(s_job, &sched->pending_list, list) { 311 struct drm_sched_fence *s_fence = s_job->s_fence; 312 313 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 314 dma_fence_signal(&s_fence->finished); 315 } 316 } 317 318 const struct drm_sched_backend_ops amdgpu_sched_ops = { 319 .dependency = amdgpu_job_dependency, 320 .run_job = amdgpu_job_run, 321 .timedout_job = amdgpu_job_timedout, 322 .free_job = amdgpu_job_free_cb 323 }; 324