1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_IRQ_H__ 25 #define __AMDGPU_IRQ_H__ 26 27 #include "amdgpu_ih.h" 28 29 #define AMDGPU_MAX_IRQ_SRC_ID 0x100 30 31 struct amdgpu_device; 32 struct amdgpu_iv_entry; 33 34 enum amdgpu_interrupt_state { 35 AMDGPU_IRQ_STATE_DISABLE, 36 AMDGPU_IRQ_STATE_ENABLE, 37 }; 38 39 struct amdgpu_irq_src { 40 unsigned num_types; 41 atomic_t *enabled_types; 42 const struct amdgpu_irq_src_funcs *funcs; 43 void *data; 44 }; 45 46 /* provided by interrupt generating IP blocks */ 47 struct amdgpu_irq_src_funcs { 48 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 49 unsigned type, enum amdgpu_interrupt_state state); 50 51 int (*process)(struct amdgpu_device *adev, 52 struct amdgpu_irq_src *source, 53 struct amdgpu_iv_entry *entry); 54 }; 55 56 struct amdgpu_irq { 57 bool installed; 58 spinlock_t lock; 59 /* interrupt sources */ 60 struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID]; 61 62 /* status, etc. */ 63 bool msi_enabled; /* msi enabled */ 64 65 /* interrupt ring */ 66 struct amdgpu_ih_ring ih; 67 const struct amdgpu_ih_funcs *ih_funcs; 68 }; 69 70 void amdgpu_irq_preinstall(struct drm_device *dev); 71 int amdgpu_irq_postinstall(struct drm_device *dev); 72 void amdgpu_irq_uninstall(struct drm_device *dev); 73 irqreturn_t amdgpu_irq_handler(int irq, void *arg); 74 75 int amdgpu_irq_init(struct amdgpu_device *adev); 76 void amdgpu_irq_fini(struct amdgpu_device *adev); 77 int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, 78 struct amdgpu_irq_src *source); 79 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 80 struct amdgpu_iv_entry *entry); 81 int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 82 unsigned type); 83 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 84 unsigned type); 85 bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, 86 struct amdgpu_irq_src *src, 87 unsigned type); 88 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 89 unsigned type); 90 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 91 unsigned type); 92 93 #endif 94