1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <drm/drmP.h> 47 #include <drm/drm_crtc_helper.h> 48 #include <drm/amdgpu_drm.h> 49 #include "amdgpu.h" 50 #include "amdgpu_ih.h" 51 #include "atom.h" 52 #include "amdgpu_connectors.h" 53 #include "amdgpu_trace.h" 54 #include "amdgpu_amdkfd.h" 55 56 #include <linux/pm_runtime.h> 57 58 #ifdef CONFIG_DRM_AMD_DC 59 #include "amdgpu_dm_irq.h" 60 #endif 61 62 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 63 64 /** 65 * amdgpu_hotplug_work_func - work handler for display hotplug event 66 * 67 * @work: work struct pointer 68 * 69 * This is the hotplug event work handler (all ASICs). 70 * The work gets scheduled from the IRQ handler if there 71 * was a hotplug interrupt. It walks through the connector table 72 * and calls hotplug handler for each connector. After this, it sends 73 * a DRM hotplug event to alert userspace. 74 * 75 * This design approach is required in order to defer hotplug event handling 76 * from the IRQ handler to a work handler because hotplug handler has to use 77 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 78 * sleep). 79 */ 80 static void amdgpu_hotplug_work_func(struct work_struct *work) 81 { 82 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 83 hotplug_work); 84 struct drm_device *dev = adev->ddev; 85 struct drm_mode_config *mode_config = &dev->mode_config; 86 struct drm_connector *connector; 87 88 mutex_lock(&mode_config->mutex); 89 list_for_each_entry(connector, &mode_config->connector_list, head) 90 amdgpu_connector_hotplug(connector); 91 mutex_unlock(&mode_config->mutex); 92 /* Just fire off a uevent and let userspace tell us what to do */ 93 drm_helper_hpd_irq_event(dev); 94 } 95 96 /** 97 * amdgpu_irq_disable_all - disable *all* interrupts 98 * 99 * @adev: amdgpu device pointer 100 * 101 * Disable all types of interrupts from all sources. 102 */ 103 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 104 { 105 unsigned long irqflags; 106 unsigned i, j, k; 107 int r; 108 109 spin_lock_irqsave(&adev->irq.lock, irqflags); 110 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 111 if (!adev->irq.client[i].sources) 112 continue; 113 114 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 115 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 116 117 if (!src || !src->funcs->set || !src->num_types) 118 continue; 119 120 for (k = 0; k < src->num_types; ++k) { 121 atomic_set(&src->enabled_types[k], 0); 122 r = src->funcs->set(adev, src, k, 123 AMDGPU_IRQ_STATE_DISABLE); 124 if (r) 125 DRM_ERROR("error disabling interrupt (%d)\n", 126 r); 127 } 128 } 129 } 130 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 131 } 132 133 /** 134 * amdgpu_irq_handler - IRQ handler 135 * 136 * @irq: IRQ number (unused) 137 * @arg: pointer to DRM device 138 * 139 * IRQ handler for amdgpu driver (all ASICs). 140 * 141 * Returns: 142 * result of handling the IRQ, as defined by &irqreturn_t 143 */ 144 irqreturn_t amdgpu_irq_handler(int irq, void *arg) 145 { 146 struct drm_device *dev = (struct drm_device *) arg; 147 struct amdgpu_device *adev = dev->dev_private; 148 irqreturn_t ret; 149 150 ret = amdgpu_ih_process(adev, &adev->irq.ih); 151 if (ret == IRQ_HANDLED) 152 pm_runtime_mark_last_busy(dev->dev); 153 return ret; 154 } 155 156 /** 157 * amdgpu_irq_handle_ih1 - kick of processing for IH1 158 * 159 * @work: work structure in struct amdgpu_irq 160 * 161 * Kick of processing IH ring 1. 162 */ 163 static void amdgpu_irq_handle_ih1(struct work_struct *work) 164 { 165 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 166 irq.ih1_work); 167 168 amdgpu_ih_process(adev, &adev->irq.ih1); 169 } 170 171 /** 172 * amdgpu_irq_handle_ih2 - kick of processing for IH2 173 * 174 * @work: work structure in struct amdgpu_irq 175 * 176 * Kick of processing IH ring 2. 177 */ 178 static void amdgpu_irq_handle_ih2(struct work_struct *work) 179 { 180 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 181 irq.ih2_work); 182 183 amdgpu_ih_process(adev, &adev->irq.ih2); 184 } 185 186 /** 187 * amdgpu_msi_ok - check whether MSI functionality is enabled 188 * 189 * @adev: amdgpu device pointer (unused) 190 * 191 * Checks whether MSI functionality has been disabled via module parameter 192 * (all ASICs). 193 * 194 * Returns: 195 * *true* if MSIs are allowed to be enabled or *false* otherwise 196 */ 197 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 198 { 199 if (amdgpu_msi == 1) 200 return true; 201 else if (amdgpu_msi == 0) 202 return false; 203 204 return true; 205 } 206 207 /** 208 * amdgpu_irq_init - initialize interrupt handling 209 * 210 * @adev: amdgpu device pointer 211 * 212 * Sets up work functions for hotplug and reset interrupts, enables MSI 213 * functionality, initializes vblank, hotplug and reset interrupt handling. 214 * 215 * Returns: 216 * 0 on success or error code on failure 217 */ 218 int amdgpu_irq_init(struct amdgpu_device *adev) 219 { 220 int r = 0; 221 222 spin_lock_init(&adev->irq.lock); 223 224 /* Enable MSI if not disabled by module parameter */ 225 adev->irq.msi_enabled = false; 226 227 if (amdgpu_msi_ok(adev)) { 228 int ret = pci_enable_msi(adev->pdev); 229 if (!ret) { 230 adev->irq.msi_enabled = true; 231 dev_dbg(adev->dev, "amdgpu: using MSI.\n"); 232 } 233 } 234 235 if (!amdgpu_device_has_dc_support(adev)) { 236 if (!adev->enable_virtual_display) 237 /* Disable vblank IRQs aggressively for power-saving */ 238 /* XXX: can this be enabled for DC? */ 239 adev->ddev->vblank_disable_immediate = true; 240 241 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); 242 if (r) 243 return r; 244 245 /* Pre-DCE11 */ 246 INIT_WORK(&adev->hotplug_work, 247 amdgpu_hotplug_work_func); 248 } 249 250 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 251 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 252 253 adev->irq.installed = true; 254 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); 255 if (r) { 256 adev->irq.installed = false; 257 if (!amdgpu_device_has_dc_support(adev)) 258 flush_work(&adev->hotplug_work); 259 return r; 260 } 261 adev->ddev->max_vblank_count = 0x00ffffff; 262 263 DRM_DEBUG("amdgpu: irq initialized.\n"); 264 return 0; 265 } 266 267 /** 268 * amdgpu_irq_fini - shut down interrupt handling 269 * 270 * @adev: amdgpu device pointer 271 * 272 * Tears down work functions for hotplug and reset interrupts, disables MSI 273 * functionality, shuts down vblank, hotplug and reset interrupt handling, 274 * turns off interrupts from all sources (all ASICs). 275 */ 276 void amdgpu_irq_fini(struct amdgpu_device *adev) 277 { 278 unsigned i, j; 279 280 if (adev->irq.installed) { 281 drm_irq_uninstall(adev->ddev); 282 adev->irq.installed = false; 283 if (adev->irq.msi_enabled) 284 pci_disable_msi(adev->pdev); 285 if (!amdgpu_device_has_dc_support(adev)) 286 flush_work(&adev->hotplug_work); 287 } 288 289 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 290 if (!adev->irq.client[i].sources) 291 continue; 292 293 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 294 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 295 296 if (!src) 297 continue; 298 299 kfree(src->enabled_types); 300 src->enabled_types = NULL; 301 if (src->data) { 302 kfree(src->data); 303 kfree(src); 304 adev->irq.client[i].sources[j] = NULL; 305 } 306 } 307 kfree(adev->irq.client[i].sources); 308 adev->irq.client[i].sources = NULL; 309 } 310 } 311 312 /** 313 * amdgpu_irq_add_id - register IRQ source 314 * 315 * @adev: amdgpu device pointer 316 * @client_id: client id 317 * @src_id: source id 318 * @source: IRQ source pointer 319 * 320 * Registers IRQ source on a client. 321 * 322 * Returns: 323 * 0 on success or error code otherwise 324 */ 325 int amdgpu_irq_add_id(struct amdgpu_device *adev, 326 unsigned client_id, unsigned src_id, 327 struct amdgpu_irq_src *source) 328 { 329 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 330 return -EINVAL; 331 332 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 333 return -EINVAL; 334 335 if (!source->funcs) 336 return -EINVAL; 337 338 if (!adev->irq.client[client_id].sources) { 339 adev->irq.client[client_id].sources = 340 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 341 sizeof(struct amdgpu_irq_src *), 342 GFP_KERNEL); 343 if (!adev->irq.client[client_id].sources) 344 return -ENOMEM; 345 } 346 347 if (adev->irq.client[client_id].sources[src_id] != NULL) 348 return -EINVAL; 349 350 if (source->num_types && !source->enabled_types) { 351 atomic_t *types; 352 353 types = kcalloc(source->num_types, sizeof(atomic_t), 354 GFP_KERNEL); 355 if (!types) 356 return -ENOMEM; 357 358 source->enabled_types = types; 359 } 360 361 adev->irq.client[client_id].sources[src_id] = source; 362 return 0; 363 } 364 365 /** 366 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 367 * 368 * @adev: amdgpu device pointer 369 * @entry: interrupt vector pointer 370 * 371 * Dispatches IRQ to IP blocks. 372 */ 373 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 374 struct amdgpu_ih_ring *ih) 375 { 376 u32 ring_index = ih->rptr >> 2; 377 struct amdgpu_iv_entry entry; 378 unsigned client_id, src_id; 379 struct amdgpu_irq_src *src; 380 bool handled = false; 381 int r; 382 383 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 384 amdgpu_ih_decode_iv(adev, &entry); 385 386 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 387 388 client_id = entry.client_id; 389 src_id = entry.src_id; 390 391 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 392 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 393 394 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 395 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 396 397 } else if (adev->irq.virq[src_id]) { 398 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); 399 400 } else if (!adev->irq.client[client_id].sources) { 401 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 402 client_id, src_id); 403 404 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 405 r = src->funcs->process(adev, src, &entry); 406 if (r < 0) 407 DRM_ERROR("error processing interrupt (%d)\n", r); 408 else if (r) 409 handled = true; 410 411 } else { 412 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 413 } 414 415 /* Send it to amdkfd as well if it isn't already handled */ 416 if (!handled) 417 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 418 } 419 420 /** 421 * amdgpu_irq_update - update hardware interrupt state 422 * 423 * @adev: amdgpu device pointer 424 * @src: interrupt source pointer 425 * @type: type of interrupt 426 * 427 * Updates interrupt state for the specific source (all ASICs). 428 */ 429 int amdgpu_irq_update(struct amdgpu_device *adev, 430 struct amdgpu_irq_src *src, unsigned type) 431 { 432 unsigned long irqflags; 433 enum amdgpu_interrupt_state state; 434 int r; 435 436 spin_lock_irqsave(&adev->irq.lock, irqflags); 437 438 /* We need to determine after taking the lock, otherwise 439 we might disable just enabled interrupts again */ 440 if (amdgpu_irq_enabled(adev, src, type)) 441 state = AMDGPU_IRQ_STATE_ENABLE; 442 else 443 state = AMDGPU_IRQ_STATE_DISABLE; 444 445 r = src->funcs->set(adev, src, type, state); 446 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 447 return r; 448 } 449 450 /** 451 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 452 * 453 * @adev: amdgpu device pointer 454 * 455 * Updates state of all types of interrupts on all sources on resume after 456 * reset. 457 */ 458 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 459 { 460 int i, j, k; 461 462 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 463 if (!adev->irq.client[i].sources) 464 continue; 465 466 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 467 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 468 469 if (!src) 470 continue; 471 for (k = 0; k < src->num_types; k++) 472 amdgpu_irq_update(adev, src, k); 473 } 474 } 475 } 476 477 /** 478 * amdgpu_irq_get - enable interrupt 479 * 480 * @adev: amdgpu device pointer 481 * @src: interrupt source pointer 482 * @type: type of interrupt 483 * 484 * Enables specified type of interrupt on the specified source (all ASICs). 485 * 486 * Returns: 487 * 0 on success or error code otherwise 488 */ 489 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 490 unsigned type) 491 { 492 if (!adev->ddev->irq_enabled) 493 return -ENOENT; 494 495 if (type >= src->num_types) 496 return -EINVAL; 497 498 if (!src->enabled_types || !src->funcs->set) 499 return -EINVAL; 500 501 if (atomic_inc_return(&src->enabled_types[type]) == 1) 502 return amdgpu_irq_update(adev, src, type); 503 504 return 0; 505 } 506 507 /** 508 * amdgpu_irq_put - disable interrupt 509 * 510 * @adev: amdgpu device pointer 511 * @src: interrupt source pointer 512 * @type: type of interrupt 513 * 514 * Enables specified type of interrupt on the specified source (all ASICs). 515 * 516 * Returns: 517 * 0 on success or error code otherwise 518 */ 519 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 520 unsigned type) 521 { 522 if (!adev->ddev->irq_enabled) 523 return -ENOENT; 524 525 if (type >= src->num_types) 526 return -EINVAL; 527 528 if (!src->enabled_types || !src->funcs->set) 529 return -EINVAL; 530 531 if (atomic_dec_and_test(&src->enabled_types[type])) 532 return amdgpu_irq_update(adev, src, type); 533 534 return 0; 535 } 536 537 /** 538 * amdgpu_irq_enabled - check whether interrupt is enabled or not 539 * 540 * @adev: amdgpu device pointer 541 * @src: interrupt source pointer 542 * @type: type of interrupt 543 * 544 * Checks whether the given type of interrupt is enabled on the given source. 545 * 546 * Returns: 547 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 548 * invalid parameters 549 */ 550 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 551 unsigned type) 552 { 553 if (!adev->ddev->irq_enabled) 554 return false; 555 556 if (type >= src->num_types) 557 return false; 558 559 if (!src->enabled_types || !src->funcs->set) 560 return false; 561 562 return !!atomic_read(&src->enabled_types[type]); 563 } 564 565 /* XXX: Generic IRQ handling */ 566 static void amdgpu_irq_mask(struct irq_data *irqd) 567 { 568 /* XXX */ 569 } 570 571 static void amdgpu_irq_unmask(struct irq_data *irqd) 572 { 573 /* XXX */ 574 } 575 576 /* amdgpu hardware interrupt chip descriptor */ 577 static struct irq_chip amdgpu_irq_chip = { 578 .name = "amdgpu-ih", 579 .irq_mask = amdgpu_irq_mask, 580 .irq_unmask = amdgpu_irq_unmask, 581 }; 582 583 /** 584 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 585 * 586 * @d: amdgpu IRQ domain pointer (unused) 587 * @irq: virtual IRQ number 588 * @hwirq: hardware irq number 589 * 590 * Current implementation assigns simple interrupt handler to the given virtual 591 * IRQ. 592 * 593 * Returns: 594 * 0 on success or error code otherwise 595 */ 596 static int amdgpu_irqdomain_map(struct irq_domain *d, 597 unsigned int irq, irq_hw_number_t hwirq) 598 { 599 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 600 return -EPERM; 601 602 irq_set_chip_and_handler(irq, 603 &amdgpu_irq_chip, handle_simple_irq); 604 return 0; 605 } 606 607 /* Implementation of methods for amdgpu IRQ domain */ 608 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 609 .map = amdgpu_irqdomain_map, 610 }; 611 612 /** 613 * amdgpu_irq_add_domain - create a linear IRQ domain 614 * 615 * @adev: amdgpu device pointer 616 * 617 * Creates an IRQ domain for GPU interrupt sources 618 * that may be driven by another driver (e.g., ACP). 619 * 620 * Returns: 621 * 0 on success or error code otherwise 622 */ 623 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 624 { 625 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 626 &amdgpu_hw_irqdomain_ops, adev); 627 if (!adev->irq.domain) { 628 DRM_ERROR("GPU irq add domain failed\n"); 629 return -ENODEV; 630 } 631 632 return 0; 633 } 634 635 /** 636 * amdgpu_irq_remove_domain - remove the IRQ domain 637 * 638 * @adev: amdgpu device pointer 639 * 640 * Removes the IRQ domain for GPU interrupt sources 641 * that may be driven by another driver (e.g., ACP). 642 */ 643 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 644 { 645 if (adev->irq.domain) { 646 irq_domain_remove(adev->irq.domain); 647 adev->irq.domain = NULL; 648 } 649 } 650 651 /** 652 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 653 * 654 * @adev: amdgpu device pointer 655 * @src_id: IH source id 656 * 657 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 658 * Use this for components that generate a GPU interrupt, but are driven 659 * by a different driver (e.g., ACP). 660 * 661 * Returns: 662 * Linux IRQ 663 */ 664 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) 665 { 666 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 667 668 return adev->irq.virq[src_id]; 669 } 670