1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <drm/drmP.h> 47 #include <drm/drm_crtc_helper.h> 48 #include <drm/amdgpu_drm.h> 49 #include "amdgpu.h" 50 #include "amdgpu_ih.h" 51 #include "atom.h" 52 #include "amdgpu_connectors.h" 53 #include "amdgpu_trace.h" 54 #include "amdgpu_amdkfd.h" 55 56 #include <linux/pm_runtime.h> 57 58 #ifdef CONFIG_DRM_AMD_DC 59 #include "amdgpu_dm_irq.h" 60 #endif 61 62 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 63 64 /** 65 * amdgpu_hotplug_work_func - work handler for display hotplug event 66 * 67 * @work: work struct pointer 68 * 69 * This is the hotplug event work handler (all ASICs). 70 * The work gets scheduled from the IRQ handler if there 71 * was a hotplug interrupt. It walks through the connector table 72 * and calls hotplug handler for each connector. After this, it sends 73 * a DRM hotplug event to alert userspace. 74 * 75 * This design approach is required in order to defer hotplug event handling 76 * from the IRQ handler to a work handler because hotplug handler has to use 77 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 78 * sleep). 79 */ 80 static void amdgpu_hotplug_work_func(struct work_struct *work) 81 { 82 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 83 hotplug_work); 84 struct drm_device *dev = adev->ddev; 85 struct drm_mode_config *mode_config = &dev->mode_config; 86 struct drm_connector *connector; 87 88 mutex_lock(&mode_config->mutex); 89 list_for_each_entry(connector, &mode_config->connector_list, head) 90 amdgpu_connector_hotplug(connector); 91 mutex_unlock(&mode_config->mutex); 92 /* Just fire off a uevent and let userspace tell us what to do */ 93 drm_helper_hpd_irq_event(dev); 94 } 95 96 /** 97 * amdgpu_irq_disable_all - disable *all* interrupts 98 * 99 * @adev: amdgpu device pointer 100 * 101 * Disable all types of interrupts from all sources. 102 */ 103 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 104 { 105 unsigned long irqflags; 106 unsigned i, j, k; 107 int r; 108 109 spin_lock_irqsave(&adev->irq.lock, irqflags); 110 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 111 if (!adev->irq.client[i].sources) 112 continue; 113 114 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 115 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 116 117 if (!src || !src->funcs->set || !src->num_types) 118 continue; 119 120 for (k = 0; k < src->num_types; ++k) { 121 atomic_set(&src->enabled_types[k], 0); 122 r = src->funcs->set(adev, src, k, 123 AMDGPU_IRQ_STATE_DISABLE); 124 if (r) 125 DRM_ERROR("error disabling interrupt (%d)\n", 126 r); 127 } 128 } 129 } 130 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 131 } 132 133 /** 134 * amdgpu_irq_callback - callback from the IH ring 135 * 136 * @adev: amdgpu device pointer 137 * @ih: amdgpu ih ring 138 * 139 * Callback from IH ring processing to handle the entry at the current position 140 * and advance the read pointer. 141 */ 142 static void amdgpu_irq_callback(struct amdgpu_device *adev, 143 struct amdgpu_ih_ring *ih) 144 { 145 u32 ring_index = ih->rptr >> 2; 146 struct amdgpu_iv_entry entry; 147 148 /* Prescreening of high-frequency interrupts */ 149 if (!amdgpu_ih_prescreen_iv(adev)) 150 return; 151 152 /* Before dispatching irq to IP blocks, send it to amdkfd */ 153 amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]); 154 155 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 156 amdgpu_ih_decode_iv(adev, &entry); 157 158 amdgpu_irq_dispatch(adev, &entry); 159 } 160 161 /** 162 * amdgpu_irq_handler - IRQ handler 163 * 164 * @irq: IRQ number (unused) 165 * @arg: pointer to DRM device 166 * 167 * IRQ handler for amdgpu driver (all ASICs). 168 * 169 * Returns: 170 * result of handling the IRQ, as defined by &irqreturn_t 171 */ 172 irqreturn_t amdgpu_irq_handler(int irq, void *arg) 173 { 174 struct drm_device *dev = (struct drm_device *) arg; 175 struct amdgpu_device *adev = dev->dev_private; 176 irqreturn_t ret; 177 178 ret = amdgpu_ih_process(adev, &adev->irq.ih, amdgpu_irq_callback); 179 if (ret == IRQ_HANDLED) 180 pm_runtime_mark_last_busy(dev->dev); 181 return ret; 182 } 183 184 /** 185 * amdgpu_msi_ok - check whether MSI functionality is enabled 186 * 187 * @adev: amdgpu device pointer (unused) 188 * 189 * Checks whether MSI functionality has been disabled via module parameter 190 * (all ASICs). 191 * 192 * Returns: 193 * *true* if MSIs are allowed to be enabled or *false* otherwise 194 */ 195 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 196 { 197 if (amdgpu_msi == 1) 198 return true; 199 else if (amdgpu_msi == 0) 200 return false; 201 202 return true; 203 } 204 205 /** 206 * amdgpu_irq_init - initialize interrupt handling 207 * 208 * @adev: amdgpu device pointer 209 * 210 * Sets up work functions for hotplug and reset interrupts, enables MSI 211 * functionality, initializes vblank, hotplug and reset interrupt handling. 212 * 213 * Returns: 214 * 0 on success or error code on failure 215 */ 216 int amdgpu_irq_init(struct amdgpu_device *adev) 217 { 218 int r = 0; 219 220 spin_lock_init(&adev->irq.lock); 221 222 /* Enable MSI if not disabled by module parameter */ 223 adev->irq.msi_enabled = false; 224 225 if (amdgpu_msi_ok(adev)) { 226 int ret = pci_enable_msi(adev->pdev); 227 if (!ret) { 228 adev->irq.msi_enabled = true; 229 dev_dbg(adev->dev, "amdgpu: using MSI.\n"); 230 } 231 } 232 233 if (!amdgpu_device_has_dc_support(adev)) { 234 if (!adev->enable_virtual_display) 235 /* Disable vblank IRQs aggressively for power-saving */ 236 /* XXX: can this be enabled for DC? */ 237 adev->ddev->vblank_disable_immediate = true; 238 239 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); 240 if (r) 241 return r; 242 243 /* Pre-DCE11 */ 244 INIT_WORK(&adev->hotplug_work, 245 amdgpu_hotplug_work_func); 246 } 247 248 adev->irq.installed = true; 249 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); 250 if (r) { 251 adev->irq.installed = false; 252 if (!amdgpu_device_has_dc_support(adev)) 253 flush_work(&adev->hotplug_work); 254 return r; 255 } 256 adev->ddev->max_vblank_count = 0x00ffffff; 257 258 DRM_DEBUG("amdgpu: irq initialized.\n"); 259 return 0; 260 } 261 262 /** 263 * amdgpu_irq_fini - shut down interrupt handling 264 * 265 * @adev: amdgpu device pointer 266 * 267 * Tears down work functions for hotplug and reset interrupts, disables MSI 268 * functionality, shuts down vblank, hotplug and reset interrupt handling, 269 * turns off interrupts from all sources (all ASICs). 270 */ 271 void amdgpu_irq_fini(struct amdgpu_device *adev) 272 { 273 unsigned i, j; 274 275 if (adev->irq.installed) { 276 drm_irq_uninstall(adev->ddev); 277 adev->irq.installed = false; 278 if (adev->irq.msi_enabled) 279 pci_disable_msi(adev->pdev); 280 if (!amdgpu_device_has_dc_support(adev)) 281 flush_work(&adev->hotplug_work); 282 } 283 284 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 285 if (!adev->irq.client[i].sources) 286 continue; 287 288 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 289 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 290 291 if (!src) 292 continue; 293 294 kfree(src->enabled_types); 295 src->enabled_types = NULL; 296 if (src->data) { 297 kfree(src->data); 298 kfree(src); 299 adev->irq.client[i].sources[j] = NULL; 300 } 301 } 302 kfree(adev->irq.client[i].sources); 303 adev->irq.client[i].sources = NULL; 304 } 305 } 306 307 /** 308 * amdgpu_irq_add_id - register IRQ source 309 * 310 * @adev: amdgpu device pointer 311 * @client_id: client id 312 * @src_id: source id 313 * @source: IRQ source pointer 314 * 315 * Registers IRQ source on a client. 316 * 317 * Returns: 318 * 0 on success or error code otherwise 319 */ 320 int amdgpu_irq_add_id(struct amdgpu_device *adev, 321 unsigned client_id, unsigned src_id, 322 struct amdgpu_irq_src *source) 323 { 324 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 325 return -EINVAL; 326 327 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 328 return -EINVAL; 329 330 if (!source->funcs) 331 return -EINVAL; 332 333 if (!adev->irq.client[client_id].sources) { 334 adev->irq.client[client_id].sources = 335 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 336 sizeof(struct amdgpu_irq_src *), 337 GFP_KERNEL); 338 if (!adev->irq.client[client_id].sources) 339 return -ENOMEM; 340 } 341 342 if (adev->irq.client[client_id].sources[src_id] != NULL) 343 return -EINVAL; 344 345 if (source->num_types && !source->enabled_types) { 346 atomic_t *types; 347 348 types = kcalloc(source->num_types, sizeof(atomic_t), 349 GFP_KERNEL); 350 if (!types) 351 return -ENOMEM; 352 353 source->enabled_types = types; 354 } 355 356 adev->irq.client[client_id].sources[src_id] = source; 357 return 0; 358 } 359 360 /** 361 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 362 * 363 * @adev: amdgpu device pointer 364 * @entry: interrupt vector pointer 365 * 366 * Dispatches IRQ to IP blocks. 367 */ 368 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 369 struct amdgpu_iv_entry *entry) 370 { 371 unsigned client_id = entry->client_id; 372 unsigned src_id = entry->src_id; 373 struct amdgpu_irq_src *src; 374 int r; 375 376 trace_amdgpu_iv(entry); 377 378 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 379 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 380 return; 381 } 382 383 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 384 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 385 return; 386 } 387 388 if (adev->irq.virq[src_id]) { 389 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); 390 } else { 391 if (!adev->irq.client[client_id].sources) { 392 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 393 client_id, src_id); 394 return; 395 } 396 397 src = adev->irq.client[client_id].sources[src_id]; 398 if (!src) { 399 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 400 return; 401 } 402 403 r = src->funcs->process(adev, src, entry); 404 if (r) 405 DRM_ERROR("error processing interrupt (%d)\n", r); 406 } 407 } 408 409 /** 410 * amdgpu_irq_update - update hardware interrupt state 411 * 412 * @adev: amdgpu device pointer 413 * @src: interrupt source pointer 414 * @type: type of interrupt 415 * 416 * Updates interrupt state for the specific source (all ASICs). 417 */ 418 int amdgpu_irq_update(struct amdgpu_device *adev, 419 struct amdgpu_irq_src *src, unsigned type) 420 { 421 unsigned long irqflags; 422 enum amdgpu_interrupt_state state; 423 int r; 424 425 spin_lock_irqsave(&adev->irq.lock, irqflags); 426 427 /* We need to determine after taking the lock, otherwise 428 we might disable just enabled interrupts again */ 429 if (amdgpu_irq_enabled(adev, src, type)) 430 state = AMDGPU_IRQ_STATE_ENABLE; 431 else 432 state = AMDGPU_IRQ_STATE_DISABLE; 433 434 r = src->funcs->set(adev, src, type, state); 435 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 436 return r; 437 } 438 439 /** 440 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 441 * 442 * @adev: amdgpu device pointer 443 * 444 * Updates state of all types of interrupts on all sources on resume after 445 * reset. 446 */ 447 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 448 { 449 int i, j, k; 450 451 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 452 if (!adev->irq.client[i].sources) 453 continue; 454 455 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 456 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 457 458 if (!src) 459 continue; 460 for (k = 0; k < src->num_types; k++) 461 amdgpu_irq_update(adev, src, k); 462 } 463 } 464 } 465 466 /** 467 * amdgpu_irq_get - enable interrupt 468 * 469 * @adev: amdgpu device pointer 470 * @src: interrupt source pointer 471 * @type: type of interrupt 472 * 473 * Enables specified type of interrupt on the specified source (all ASICs). 474 * 475 * Returns: 476 * 0 on success or error code otherwise 477 */ 478 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 479 unsigned type) 480 { 481 if (!adev->ddev->irq_enabled) 482 return -ENOENT; 483 484 if (type >= src->num_types) 485 return -EINVAL; 486 487 if (!src->enabled_types || !src->funcs->set) 488 return -EINVAL; 489 490 if (atomic_inc_return(&src->enabled_types[type]) == 1) 491 return amdgpu_irq_update(adev, src, type); 492 493 return 0; 494 } 495 496 /** 497 * amdgpu_irq_put - disable interrupt 498 * 499 * @adev: amdgpu device pointer 500 * @src: interrupt source pointer 501 * @type: type of interrupt 502 * 503 * Enables specified type of interrupt on the specified source (all ASICs). 504 * 505 * Returns: 506 * 0 on success or error code otherwise 507 */ 508 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 509 unsigned type) 510 { 511 if (!adev->ddev->irq_enabled) 512 return -ENOENT; 513 514 if (type >= src->num_types) 515 return -EINVAL; 516 517 if (!src->enabled_types || !src->funcs->set) 518 return -EINVAL; 519 520 if (atomic_dec_and_test(&src->enabled_types[type])) 521 return amdgpu_irq_update(adev, src, type); 522 523 return 0; 524 } 525 526 /** 527 * amdgpu_irq_enabled - check whether interrupt is enabled or not 528 * 529 * @adev: amdgpu device pointer 530 * @src: interrupt source pointer 531 * @type: type of interrupt 532 * 533 * Checks whether the given type of interrupt is enabled on the given source. 534 * 535 * Returns: 536 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 537 * invalid parameters 538 */ 539 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 540 unsigned type) 541 { 542 if (!adev->ddev->irq_enabled) 543 return false; 544 545 if (type >= src->num_types) 546 return false; 547 548 if (!src->enabled_types || !src->funcs->set) 549 return false; 550 551 return !!atomic_read(&src->enabled_types[type]); 552 } 553 554 /* XXX: Generic IRQ handling */ 555 static void amdgpu_irq_mask(struct irq_data *irqd) 556 { 557 /* XXX */ 558 } 559 560 static void amdgpu_irq_unmask(struct irq_data *irqd) 561 { 562 /* XXX */ 563 } 564 565 /* amdgpu hardware interrupt chip descriptor */ 566 static struct irq_chip amdgpu_irq_chip = { 567 .name = "amdgpu-ih", 568 .irq_mask = amdgpu_irq_mask, 569 .irq_unmask = amdgpu_irq_unmask, 570 }; 571 572 /** 573 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 574 * 575 * @d: amdgpu IRQ domain pointer (unused) 576 * @irq: virtual IRQ number 577 * @hwirq: hardware irq number 578 * 579 * Current implementation assigns simple interrupt handler to the given virtual 580 * IRQ. 581 * 582 * Returns: 583 * 0 on success or error code otherwise 584 */ 585 static int amdgpu_irqdomain_map(struct irq_domain *d, 586 unsigned int irq, irq_hw_number_t hwirq) 587 { 588 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 589 return -EPERM; 590 591 irq_set_chip_and_handler(irq, 592 &amdgpu_irq_chip, handle_simple_irq); 593 return 0; 594 } 595 596 /* Implementation of methods for amdgpu IRQ domain */ 597 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 598 .map = amdgpu_irqdomain_map, 599 }; 600 601 /** 602 * amdgpu_irq_add_domain - create a linear IRQ domain 603 * 604 * @adev: amdgpu device pointer 605 * 606 * Creates an IRQ domain for GPU interrupt sources 607 * that may be driven by another driver (e.g., ACP). 608 * 609 * Returns: 610 * 0 on success or error code otherwise 611 */ 612 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 613 { 614 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 615 &amdgpu_hw_irqdomain_ops, adev); 616 if (!adev->irq.domain) { 617 DRM_ERROR("GPU irq add domain failed\n"); 618 return -ENODEV; 619 } 620 621 return 0; 622 } 623 624 /** 625 * amdgpu_irq_remove_domain - remove the IRQ domain 626 * 627 * @adev: amdgpu device pointer 628 * 629 * Removes the IRQ domain for GPU interrupt sources 630 * that may be driven by another driver (e.g., ACP). 631 */ 632 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 633 { 634 if (adev->irq.domain) { 635 irq_domain_remove(adev->irq.domain); 636 adev->irq.domain = NULL; 637 } 638 } 639 640 /** 641 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 642 * 643 * @adev: amdgpu device pointer 644 * @src_id: IH source id 645 * 646 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 647 * Use this for components that generate a GPU interrupt, but are driven 648 * by a different driver (e.g., ACP). 649 * 650 * Returns: 651 * Linux IRQ 652 */ 653 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) 654 { 655 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 656 657 return adev->irq.virq[src_id]; 658 } 659