1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <linux/pci.h> 47 48 #include <drm/drm_crtc_helper.h> 49 #include <drm/drm_vblank.h> 50 #include <drm/amdgpu_drm.h> 51 #include <drm/drm_drv.h> 52 #include "amdgpu.h" 53 #include "amdgpu_ih.h" 54 #include "atom.h" 55 #include "amdgpu_connectors.h" 56 #include "amdgpu_trace.h" 57 #include "amdgpu_amdkfd.h" 58 #include "amdgpu_ras.h" 59 60 #include <linux/pm_runtime.h> 61 62 #ifdef CONFIG_DRM_AMD_DC 63 #include "amdgpu_dm_irq.h" 64 #endif 65 66 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 67 68 const char *soc15_ih_clientid_name[] = { 69 "IH", 70 "SDMA2 or ACP", 71 "ATHUB", 72 "BIF", 73 "SDMA3 or DCE", 74 "SDMA4 or ISP", 75 "VMC1 or PCIE0", 76 "RLC", 77 "SDMA0", 78 "SDMA1", 79 "SE0SH", 80 "SE1SH", 81 "SE2SH", 82 "SE3SH", 83 "VCN1 or UVD1", 84 "THM", 85 "VCN or UVD", 86 "SDMA5 or VCE0", 87 "VMC", 88 "SDMA6 or XDMA", 89 "GRBM_CP", 90 "ATS", 91 "ROM_SMUIO", 92 "DF", 93 "SDMA7 or VCE1", 94 "PWR", 95 "reserved", 96 "UTCL2", 97 "EA", 98 "UTCL2LOG", 99 "MP0", 100 "MP1" 101 }; 102 103 /** 104 * amdgpu_hotplug_work_func - work handler for display hotplug event 105 * 106 * @work: work struct pointer 107 * 108 * This is the hotplug event work handler (all ASICs). 109 * The work gets scheduled from the IRQ handler if there 110 * was a hotplug interrupt. It walks through the connector table 111 * and calls hotplug handler for each connector. After this, it sends 112 * a DRM hotplug event to alert userspace. 113 * 114 * This design approach is required in order to defer hotplug event handling 115 * from the IRQ handler to a work handler because hotplug handler has to use 116 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 117 * sleep). 118 */ 119 static void amdgpu_hotplug_work_func(struct work_struct *work) 120 { 121 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 122 hotplug_work); 123 struct drm_device *dev = adev_to_drm(adev); 124 struct drm_mode_config *mode_config = &dev->mode_config; 125 struct drm_connector *connector; 126 struct drm_connector_list_iter iter; 127 128 mutex_lock(&mode_config->mutex); 129 drm_connector_list_iter_begin(dev, &iter); 130 drm_for_each_connector_iter(connector, &iter) 131 amdgpu_connector_hotplug(connector); 132 drm_connector_list_iter_end(&iter); 133 mutex_unlock(&mode_config->mutex); 134 /* Just fire off a uevent and let userspace tell us what to do */ 135 drm_helper_hpd_irq_event(dev); 136 } 137 138 /** 139 * amdgpu_irq_disable_all - disable *all* interrupts 140 * 141 * @adev: amdgpu device pointer 142 * 143 * Disable all types of interrupts from all sources. 144 */ 145 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 146 { 147 unsigned long irqflags; 148 unsigned i, j, k; 149 int r; 150 151 spin_lock_irqsave(&adev->irq.lock, irqflags); 152 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 153 if (!adev->irq.client[i].sources) 154 continue; 155 156 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 157 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 158 159 if (!src || !src->funcs->set || !src->num_types) 160 continue; 161 162 for (k = 0; k < src->num_types; ++k) { 163 atomic_set(&src->enabled_types[k], 0); 164 r = src->funcs->set(adev, src, k, 165 AMDGPU_IRQ_STATE_DISABLE); 166 if (r) 167 DRM_ERROR("error disabling interrupt (%d)\n", 168 r); 169 } 170 } 171 } 172 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 173 } 174 175 /** 176 * amdgpu_irq_handler - IRQ handler 177 * 178 * @irq: IRQ number (unused) 179 * @arg: pointer to DRM device 180 * 181 * IRQ handler for amdgpu driver (all ASICs). 182 * 183 * Returns: 184 * result of handling the IRQ, as defined by &irqreturn_t 185 */ 186 static irqreturn_t amdgpu_irq_handler(int irq, void *arg) 187 { 188 struct drm_device *dev = (struct drm_device *) arg; 189 struct amdgpu_device *adev = drm_to_adev(dev); 190 irqreturn_t ret; 191 192 ret = amdgpu_ih_process(adev, &adev->irq.ih); 193 if (ret == IRQ_HANDLED) 194 pm_runtime_mark_last_busy(dev->dev); 195 196 amdgpu_ras_interrupt_fatal_error_handler(adev); 197 198 return ret; 199 } 200 201 /** 202 * amdgpu_irq_handle_ih1 - kick of processing for IH1 203 * 204 * @work: work structure in struct amdgpu_irq 205 * 206 * Kick of processing IH ring 1. 207 */ 208 static void amdgpu_irq_handle_ih1(struct work_struct *work) 209 { 210 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 211 irq.ih1_work); 212 213 amdgpu_ih_process(adev, &adev->irq.ih1); 214 } 215 216 /** 217 * amdgpu_irq_handle_ih2 - kick of processing for IH2 218 * 219 * @work: work structure in struct amdgpu_irq 220 * 221 * Kick of processing IH ring 2. 222 */ 223 static void amdgpu_irq_handle_ih2(struct work_struct *work) 224 { 225 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 226 irq.ih2_work); 227 228 amdgpu_ih_process(adev, &adev->irq.ih2); 229 } 230 231 /** 232 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft 233 * 234 * @work: work structure in struct amdgpu_irq 235 * 236 * Kick of processing IH soft ring. 237 */ 238 static void amdgpu_irq_handle_ih_soft(struct work_struct *work) 239 { 240 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 241 irq.ih_soft_work); 242 243 amdgpu_ih_process(adev, &adev->irq.ih_soft); 244 } 245 246 /** 247 * amdgpu_msi_ok - check whether MSI functionality is enabled 248 * 249 * @adev: amdgpu device pointer (unused) 250 * 251 * Checks whether MSI functionality has been disabled via module parameter 252 * (all ASICs). 253 * 254 * Returns: 255 * *true* if MSIs are allowed to be enabled or *false* otherwise 256 */ 257 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 258 { 259 if (amdgpu_msi == 1) 260 return true; 261 else if (amdgpu_msi == 0) 262 return false; 263 264 return true; 265 } 266 267 static void amdgpu_restore_msix(struct amdgpu_device *adev) 268 { 269 u16 ctrl; 270 271 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 272 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE)) 273 return; 274 275 /* VF FLR */ 276 ctrl &= ~PCI_MSIX_FLAGS_ENABLE; 277 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 278 ctrl |= PCI_MSIX_FLAGS_ENABLE; 279 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 280 } 281 282 /** 283 * amdgpu_irq_init - initialize interrupt handling 284 * 285 * @adev: amdgpu device pointer 286 * 287 * Sets up work functions for hotplug and reset interrupts, enables MSI 288 * functionality, initializes vblank, hotplug and reset interrupt handling. 289 * 290 * Returns: 291 * 0 on success or error code on failure 292 */ 293 int amdgpu_irq_init(struct amdgpu_device *adev) 294 { 295 int r = 0; 296 unsigned int irq; 297 298 spin_lock_init(&adev->irq.lock); 299 300 /* Enable MSI if not disabled by module parameter */ 301 adev->irq.msi_enabled = false; 302 303 if (amdgpu_msi_ok(adev)) { 304 int nvec = pci_msix_vec_count(adev->pdev); 305 unsigned int flags; 306 307 if (nvec <= 0) { 308 flags = PCI_IRQ_MSI; 309 } else { 310 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX; 311 } 312 /* we only need one vector */ 313 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags); 314 if (nvec > 0) { 315 adev->irq.msi_enabled = true; 316 dev_dbg(adev->dev, "using MSI/MSI-X.\n"); 317 } 318 } 319 320 if (!amdgpu_device_has_dc_support(adev)) { 321 if (!adev->enable_virtual_display) 322 /* Disable vblank IRQs aggressively for power-saving */ 323 adev_to_drm(adev)->vblank_disable_immediate = true; 324 325 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 326 if (r) 327 return r; 328 329 /* Pre-DCE11 */ 330 INIT_WORK(&adev->hotplug_work, 331 amdgpu_hotplug_work_func); 332 } 333 334 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 335 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 336 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft); 337 338 /* Use vector 0 for MSI-X. */ 339 r = pci_irq_vector(adev->pdev, 0); 340 if (r < 0) 341 return r; 342 irq = r; 343 344 /* PCI devices require shared interrupts. */ 345 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name, 346 adev_to_drm(adev)); 347 if (r) { 348 if (!amdgpu_device_has_dc_support(adev)) 349 flush_work(&adev->hotplug_work); 350 return r; 351 } 352 adev->irq.installed = true; 353 adev->irq.irq = irq; 354 adev_to_drm(adev)->max_vblank_count = 0x00ffffff; 355 356 DRM_DEBUG("amdgpu: irq initialized.\n"); 357 return 0; 358 } 359 360 361 void amdgpu_irq_fini_hw(struct amdgpu_device *adev) 362 { 363 if (adev->irq.installed) { 364 free_irq(adev->irq.irq, adev_to_drm(adev)); 365 adev->irq.installed = false; 366 if (adev->irq.msi_enabled) 367 pci_free_irq_vectors(adev->pdev); 368 369 if (!amdgpu_device_has_dc_support(adev)) 370 flush_work(&adev->hotplug_work); 371 } 372 373 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 374 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 375 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 376 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 377 } 378 379 /** 380 * amdgpu_irq_fini_sw - shut down interrupt handling 381 * 382 * @adev: amdgpu device pointer 383 * 384 * Tears down work functions for hotplug and reset interrupts, disables MSI 385 * functionality, shuts down vblank, hotplug and reset interrupt handling, 386 * turns off interrupts from all sources (all ASICs). 387 */ 388 void amdgpu_irq_fini_sw(struct amdgpu_device *adev) 389 { 390 unsigned i, j; 391 392 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 393 if (!adev->irq.client[i].sources) 394 continue; 395 396 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 397 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 398 399 if (!src) 400 continue; 401 402 kfree(src->enabled_types); 403 src->enabled_types = NULL; 404 } 405 kfree(adev->irq.client[i].sources); 406 adev->irq.client[i].sources = NULL; 407 } 408 } 409 410 /** 411 * amdgpu_irq_add_id - register IRQ source 412 * 413 * @adev: amdgpu device pointer 414 * @client_id: client id 415 * @src_id: source id 416 * @source: IRQ source pointer 417 * 418 * Registers IRQ source on a client. 419 * 420 * Returns: 421 * 0 on success or error code otherwise 422 */ 423 int amdgpu_irq_add_id(struct amdgpu_device *adev, 424 unsigned client_id, unsigned src_id, 425 struct amdgpu_irq_src *source) 426 { 427 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 428 return -EINVAL; 429 430 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 431 return -EINVAL; 432 433 if (!source->funcs) 434 return -EINVAL; 435 436 if (!adev->irq.client[client_id].sources) { 437 adev->irq.client[client_id].sources = 438 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 439 sizeof(struct amdgpu_irq_src *), 440 GFP_KERNEL); 441 if (!adev->irq.client[client_id].sources) 442 return -ENOMEM; 443 } 444 445 if (adev->irq.client[client_id].sources[src_id] != NULL) 446 return -EINVAL; 447 448 if (source->num_types && !source->enabled_types) { 449 atomic_t *types; 450 451 types = kcalloc(source->num_types, sizeof(atomic_t), 452 GFP_KERNEL); 453 if (!types) 454 return -ENOMEM; 455 456 source->enabled_types = types; 457 } 458 459 adev->irq.client[client_id].sources[src_id] = source; 460 return 0; 461 } 462 463 /** 464 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 465 * 466 * @adev: amdgpu device pointer 467 * @ih: interrupt ring instance 468 * 469 * Dispatches IRQ to IP blocks. 470 */ 471 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 472 struct amdgpu_ih_ring *ih) 473 { 474 u32 ring_index = ih->rptr >> 2; 475 struct amdgpu_iv_entry entry; 476 unsigned client_id, src_id; 477 struct amdgpu_irq_src *src; 478 bool handled = false; 479 int r; 480 481 entry.ih = ih; 482 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 483 amdgpu_ih_decode_iv(adev, &entry); 484 485 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 486 487 client_id = entry.client_id; 488 src_id = entry.src_id; 489 490 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 491 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 492 493 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 494 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 495 496 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) && 497 adev->irq.virq[src_id]) { 498 generic_handle_domain_irq(adev->irq.domain, src_id); 499 500 } else if (!adev->irq.client[client_id].sources) { 501 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 502 client_id, src_id); 503 504 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 505 r = src->funcs->process(adev, src, &entry); 506 if (r < 0) 507 DRM_ERROR("error processing interrupt (%d)\n", r); 508 else if (r) 509 handled = true; 510 511 } else { 512 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 513 } 514 515 /* Send it to amdkfd as well if it isn't already handled */ 516 if (!handled) 517 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 518 519 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp)) 520 ih->processed_timestamp = entry.timestamp; 521 } 522 523 /** 524 * amdgpu_irq_delegate - delegate IV to soft IH ring 525 * 526 * @adev: amdgpu device pointer 527 * @entry: IV entry 528 * @num_dw: size of IV 529 * 530 * Delegate the IV to the soft IH ring and schedule processing of it. Used 531 * if the hardware delegation to IH1 or IH2 doesn't work for some reason. 532 */ 533 void amdgpu_irq_delegate(struct amdgpu_device *adev, 534 struct amdgpu_iv_entry *entry, 535 unsigned int num_dw) 536 { 537 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw); 538 schedule_work(&adev->irq.ih_soft_work); 539 } 540 541 /** 542 * amdgpu_irq_update - update hardware interrupt state 543 * 544 * @adev: amdgpu device pointer 545 * @src: interrupt source pointer 546 * @type: type of interrupt 547 * 548 * Updates interrupt state for the specific source (all ASICs). 549 */ 550 int amdgpu_irq_update(struct amdgpu_device *adev, 551 struct amdgpu_irq_src *src, unsigned type) 552 { 553 unsigned long irqflags; 554 enum amdgpu_interrupt_state state; 555 int r; 556 557 spin_lock_irqsave(&adev->irq.lock, irqflags); 558 559 /* We need to determine after taking the lock, otherwise 560 we might disable just enabled interrupts again */ 561 if (amdgpu_irq_enabled(adev, src, type)) 562 state = AMDGPU_IRQ_STATE_ENABLE; 563 else 564 state = AMDGPU_IRQ_STATE_DISABLE; 565 566 r = src->funcs->set(adev, src, type, state); 567 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 568 return r; 569 } 570 571 /** 572 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 573 * 574 * @adev: amdgpu device pointer 575 * 576 * Updates state of all types of interrupts on all sources on resume after 577 * reset. 578 */ 579 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 580 { 581 int i, j, k; 582 583 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) 584 amdgpu_restore_msix(adev); 585 586 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 587 if (!adev->irq.client[i].sources) 588 continue; 589 590 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 591 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 592 593 if (!src || !src->funcs || !src->funcs->set) 594 continue; 595 for (k = 0; k < src->num_types; k++) 596 amdgpu_irq_update(adev, src, k); 597 } 598 } 599 } 600 601 /** 602 * amdgpu_irq_get - enable interrupt 603 * 604 * @adev: amdgpu device pointer 605 * @src: interrupt source pointer 606 * @type: type of interrupt 607 * 608 * Enables specified type of interrupt on the specified source (all ASICs). 609 * 610 * Returns: 611 * 0 on success or error code otherwise 612 */ 613 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 614 unsigned type) 615 { 616 if (!adev->irq.installed) 617 return -ENOENT; 618 619 if (type >= src->num_types) 620 return -EINVAL; 621 622 if (!src->enabled_types || !src->funcs->set) 623 return -EINVAL; 624 625 if (atomic_inc_return(&src->enabled_types[type]) == 1) 626 return amdgpu_irq_update(adev, src, type); 627 628 return 0; 629 } 630 631 /** 632 * amdgpu_irq_put - disable interrupt 633 * 634 * @adev: amdgpu device pointer 635 * @src: interrupt source pointer 636 * @type: type of interrupt 637 * 638 * Enables specified type of interrupt on the specified source (all ASICs). 639 * 640 * Returns: 641 * 0 on success or error code otherwise 642 */ 643 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 644 unsigned type) 645 { 646 if (!adev->irq.installed) 647 return -ENOENT; 648 649 if (type >= src->num_types) 650 return -EINVAL; 651 652 if (!src->enabled_types || !src->funcs->set) 653 return -EINVAL; 654 655 if (atomic_dec_and_test(&src->enabled_types[type])) 656 return amdgpu_irq_update(adev, src, type); 657 658 return 0; 659 } 660 661 /** 662 * amdgpu_irq_enabled - check whether interrupt is enabled or not 663 * 664 * @adev: amdgpu device pointer 665 * @src: interrupt source pointer 666 * @type: type of interrupt 667 * 668 * Checks whether the given type of interrupt is enabled on the given source. 669 * 670 * Returns: 671 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 672 * invalid parameters 673 */ 674 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 675 unsigned type) 676 { 677 if (!adev->irq.installed) 678 return false; 679 680 if (type >= src->num_types) 681 return false; 682 683 if (!src->enabled_types || !src->funcs->set) 684 return false; 685 686 return !!atomic_read(&src->enabled_types[type]); 687 } 688 689 /* XXX: Generic IRQ handling */ 690 static void amdgpu_irq_mask(struct irq_data *irqd) 691 { 692 /* XXX */ 693 } 694 695 static void amdgpu_irq_unmask(struct irq_data *irqd) 696 { 697 /* XXX */ 698 } 699 700 /* amdgpu hardware interrupt chip descriptor */ 701 static struct irq_chip amdgpu_irq_chip = { 702 .name = "amdgpu-ih", 703 .irq_mask = amdgpu_irq_mask, 704 .irq_unmask = amdgpu_irq_unmask, 705 }; 706 707 /** 708 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 709 * 710 * @d: amdgpu IRQ domain pointer (unused) 711 * @irq: virtual IRQ number 712 * @hwirq: hardware irq number 713 * 714 * Current implementation assigns simple interrupt handler to the given virtual 715 * IRQ. 716 * 717 * Returns: 718 * 0 on success or error code otherwise 719 */ 720 static int amdgpu_irqdomain_map(struct irq_domain *d, 721 unsigned int irq, irq_hw_number_t hwirq) 722 { 723 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 724 return -EPERM; 725 726 irq_set_chip_and_handler(irq, 727 &amdgpu_irq_chip, handle_simple_irq); 728 return 0; 729 } 730 731 /* Implementation of methods for amdgpu IRQ domain */ 732 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 733 .map = amdgpu_irqdomain_map, 734 }; 735 736 /** 737 * amdgpu_irq_add_domain - create a linear IRQ domain 738 * 739 * @adev: amdgpu device pointer 740 * 741 * Creates an IRQ domain for GPU interrupt sources 742 * that may be driven by another driver (e.g., ACP). 743 * 744 * Returns: 745 * 0 on success or error code otherwise 746 */ 747 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 748 { 749 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 750 &amdgpu_hw_irqdomain_ops, adev); 751 if (!adev->irq.domain) { 752 DRM_ERROR("GPU irq add domain failed\n"); 753 return -ENODEV; 754 } 755 756 return 0; 757 } 758 759 /** 760 * amdgpu_irq_remove_domain - remove the IRQ domain 761 * 762 * @adev: amdgpu device pointer 763 * 764 * Removes the IRQ domain for GPU interrupt sources 765 * that may be driven by another driver (e.g., ACP). 766 */ 767 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 768 { 769 if (adev->irq.domain) { 770 irq_domain_remove(adev->irq.domain); 771 adev->irq.domain = NULL; 772 } 773 } 774 775 /** 776 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 777 * 778 * @adev: amdgpu device pointer 779 * @src_id: IH source id 780 * 781 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 782 * Use this for components that generate a GPU interrupt, but are driven 783 * by a different driver (e.g., ACP). 784 * 785 * Returns: 786 * Linux IRQ 787 */ 788 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) 789 { 790 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 791 792 return adev->irq.virq[src_id]; 793 } 794