1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <linux/pci.h> 47 48 #include <drm/drm_crtc_helper.h> 49 #include <drm/drm_irq.h> 50 #include <drm/drm_vblank.h> 51 #include <drm/amdgpu_drm.h> 52 #include "amdgpu.h" 53 #include "amdgpu_ih.h" 54 #include "atom.h" 55 #include "amdgpu_connectors.h" 56 #include "amdgpu_trace.h" 57 #include "amdgpu_amdkfd.h" 58 #include "amdgpu_ras.h" 59 60 #include <linux/pm_runtime.h> 61 62 #ifdef CONFIG_DRM_AMD_DC 63 #include "amdgpu_dm_irq.h" 64 #endif 65 66 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 67 68 /** 69 * amdgpu_hotplug_work_func - work handler for display hotplug event 70 * 71 * @work: work struct pointer 72 * 73 * This is the hotplug event work handler (all ASICs). 74 * The work gets scheduled from the IRQ handler if there 75 * was a hotplug interrupt. It walks through the connector table 76 * and calls hotplug handler for each connector. After this, it sends 77 * a DRM hotplug event to alert userspace. 78 * 79 * This design approach is required in order to defer hotplug event handling 80 * from the IRQ handler to a work handler because hotplug handler has to use 81 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 82 * sleep). 83 */ 84 static void amdgpu_hotplug_work_func(struct work_struct *work) 85 { 86 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 87 hotplug_work); 88 struct drm_device *dev = adev_to_drm(adev); 89 struct drm_mode_config *mode_config = &dev->mode_config; 90 struct drm_connector *connector; 91 struct drm_connector_list_iter iter; 92 93 mutex_lock(&mode_config->mutex); 94 drm_connector_list_iter_begin(dev, &iter); 95 drm_for_each_connector_iter(connector, &iter) 96 amdgpu_connector_hotplug(connector); 97 drm_connector_list_iter_end(&iter); 98 mutex_unlock(&mode_config->mutex); 99 /* Just fire off a uevent and let userspace tell us what to do */ 100 drm_helper_hpd_irq_event(dev); 101 } 102 103 /** 104 * amdgpu_irq_disable_all - disable *all* interrupts 105 * 106 * @adev: amdgpu device pointer 107 * 108 * Disable all types of interrupts from all sources. 109 */ 110 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 111 { 112 unsigned long irqflags; 113 unsigned i, j, k; 114 int r; 115 116 spin_lock_irqsave(&adev->irq.lock, irqflags); 117 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 118 if (!adev->irq.client[i].sources) 119 continue; 120 121 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 122 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 123 124 if (!src || !src->funcs->set || !src->num_types) 125 continue; 126 127 for (k = 0; k < src->num_types; ++k) { 128 atomic_set(&src->enabled_types[k], 0); 129 r = src->funcs->set(adev, src, k, 130 AMDGPU_IRQ_STATE_DISABLE); 131 if (r) 132 DRM_ERROR("error disabling interrupt (%d)\n", 133 r); 134 } 135 } 136 } 137 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 138 } 139 140 /** 141 * amdgpu_irq_handler - IRQ handler 142 * 143 * @irq: IRQ number (unused) 144 * @arg: pointer to DRM device 145 * 146 * IRQ handler for amdgpu driver (all ASICs). 147 * 148 * Returns: 149 * result of handling the IRQ, as defined by &irqreturn_t 150 */ 151 irqreturn_t amdgpu_irq_handler(int irq, void *arg) 152 { 153 struct drm_device *dev = (struct drm_device *) arg; 154 struct amdgpu_device *adev = drm_to_adev(dev); 155 irqreturn_t ret; 156 157 ret = amdgpu_ih_process(adev, &adev->irq.ih); 158 if (ret == IRQ_HANDLED) 159 pm_runtime_mark_last_busy(dev->dev); 160 161 /* For the hardware that cannot enable bif ring for both ras_controller_irq 162 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status 163 * register to check whether the interrupt is triggered or not, and properly 164 * ack the interrupt if it is there 165 */ 166 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) { 167 if (adev->nbio.funcs && 168 adev->nbio.funcs->handle_ras_controller_intr_no_bifring) 169 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev); 170 171 if (adev->nbio.funcs && 172 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring) 173 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev); 174 } 175 176 return ret; 177 } 178 179 /** 180 * amdgpu_irq_handle_ih1 - kick of processing for IH1 181 * 182 * @work: work structure in struct amdgpu_irq 183 * 184 * Kick of processing IH ring 1. 185 */ 186 static void amdgpu_irq_handle_ih1(struct work_struct *work) 187 { 188 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 189 irq.ih1_work); 190 191 amdgpu_ih_process(adev, &adev->irq.ih1); 192 } 193 194 /** 195 * amdgpu_irq_handle_ih2 - kick of processing for IH2 196 * 197 * @work: work structure in struct amdgpu_irq 198 * 199 * Kick of processing IH ring 2. 200 */ 201 static void amdgpu_irq_handle_ih2(struct work_struct *work) 202 { 203 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 204 irq.ih2_work); 205 206 amdgpu_ih_process(adev, &adev->irq.ih2); 207 } 208 209 /** 210 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft 211 * 212 * @work: work structure in struct amdgpu_irq 213 * 214 * Kick of processing IH soft ring. 215 */ 216 static void amdgpu_irq_handle_ih_soft(struct work_struct *work) 217 { 218 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 219 irq.ih_soft_work); 220 221 amdgpu_ih_process(adev, &adev->irq.ih_soft); 222 } 223 224 /** 225 * amdgpu_msi_ok - check whether MSI functionality is enabled 226 * 227 * @adev: amdgpu device pointer (unused) 228 * 229 * Checks whether MSI functionality has been disabled via module parameter 230 * (all ASICs). 231 * 232 * Returns: 233 * *true* if MSIs are allowed to be enabled or *false* otherwise 234 */ 235 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 236 { 237 if (amdgpu_msi == 1) 238 return true; 239 else if (amdgpu_msi == 0) 240 return false; 241 242 return true; 243 } 244 245 /** 246 * amdgpu_irq_init - initialize interrupt handling 247 * 248 * @adev: amdgpu device pointer 249 * 250 * Sets up work functions for hotplug and reset interrupts, enables MSI 251 * functionality, initializes vblank, hotplug and reset interrupt handling. 252 * 253 * Returns: 254 * 0 on success or error code on failure 255 */ 256 int amdgpu_irq_init(struct amdgpu_device *adev) 257 { 258 int r = 0; 259 260 spin_lock_init(&adev->irq.lock); 261 262 /* Enable MSI if not disabled by module parameter */ 263 adev->irq.msi_enabled = false; 264 265 if (amdgpu_msi_ok(adev)) { 266 int nvec = pci_msix_vec_count(adev->pdev); 267 unsigned int flags; 268 269 if (nvec <= 0) { 270 flags = PCI_IRQ_MSI; 271 } else { 272 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX; 273 } 274 /* we only need one vector */ 275 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags); 276 if (nvec > 0) { 277 adev->irq.msi_enabled = true; 278 dev_dbg(adev->dev, "using MSI/MSI-X.\n"); 279 } 280 } 281 282 if (!amdgpu_device_has_dc_support(adev)) { 283 if (!adev->enable_virtual_display) 284 /* Disable vblank IRQs aggressively for power-saving */ 285 /* XXX: can this be enabled for DC? */ 286 adev_to_drm(adev)->vblank_disable_immediate = true; 287 288 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 289 if (r) 290 return r; 291 292 /* Pre-DCE11 */ 293 INIT_WORK(&adev->hotplug_work, 294 amdgpu_hotplug_work_func); 295 } 296 297 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 298 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 299 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft); 300 301 adev->irq.installed = true; 302 /* Use vector 0 for MSI-X */ 303 r = drm_irq_install(adev_to_drm(adev), pci_irq_vector(adev->pdev, 0)); 304 if (r) { 305 adev->irq.installed = false; 306 if (!amdgpu_device_has_dc_support(adev)) 307 flush_work(&adev->hotplug_work); 308 return r; 309 } 310 adev_to_drm(adev)->max_vblank_count = 0x00ffffff; 311 312 DRM_DEBUG("amdgpu: irq initialized.\n"); 313 return 0; 314 } 315 316 /** 317 * amdgpu_irq_fini - shut down interrupt handling 318 * 319 * @adev: amdgpu device pointer 320 * 321 * Tears down work functions for hotplug and reset interrupts, disables MSI 322 * functionality, shuts down vblank, hotplug and reset interrupt handling, 323 * turns off interrupts from all sources (all ASICs). 324 */ 325 void amdgpu_irq_fini(struct amdgpu_device *adev) 326 { 327 unsigned i, j; 328 329 if (adev->irq.installed) { 330 drm_irq_uninstall(adev_to_drm(adev)); 331 adev->irq.installed = false; 332 if (adev->irq.msi_enabled) 333 pci_free_irq_vectors(adev->pdev); 334 if (!amdgpu_device_has_dc_support(adev)) 335 flush_work(&adev->hotplug_work); 336 } 337 338 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 339 if (!adev->irq.client[i].sources) 340 continue; 341 342 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 343 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 344 345 if (!src) 346 continue; 347 348 kfree(src->enabled_types); 349 src->enabled_types = NULL; 350 if (src->data) { 351 kfree(src->data); 352 kfree(src); 353 adev->irq.client[i].sources[j] = NULL; 354 } 355 } 356 kfree(adev->irq.client[i].sources); 357 adev->irq.client[i].sources = NULL; 358 } 359 } 360 361 /** 362 * amdgpu_irq_add_id - register IRQ source 363 * 364 * @adev: amdgpu device pointer 365 * @client_id: client id 366 * @src_id: source id 367 * @source: IRQ source pointer 368 * 369 * Registers IRQ source on a client. 370 * 371 * Returns: 372 * 0 on success or error code otherwise 373 */ 374 int amdgpu_irq_add_id(struct amdgpu_device *adev, 375 unsigned client_id, unsigned src_id, 376 struct amdgpu_irq_src *source) 377 { 378 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 379 return -EINVAL; 380 381 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 382 return -EINVAL; 383 384 if (!source->funcs) 385 return -EINVAL; 386 387 if (!adev->irq.client[client_id].sources) { 388 adev->irq.client[client_id].sources = 389 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 390 sizeof(struct amdgpu_irq_src *), 391 GFP_KERNEL); 392 if (!adev->irq.client[client_id].sources) 393 return -ENOMEM; 394 } 395 396 if (adev->irq.client[client_id].sources[src_id] != NULL) 397 return -EINVAL; 398 399 if (source->num_types && !source->enabled_types) { 400 atomic_t *types; 401 402 types = kcalloc(source->num_types, sizeof(atomic_t), 403 GFP_KERNEL); 404 if (!types) 405 return -ENOMEM; 406 407 source->enabled_types = types; 408 } 409 410 adev->irq.client[client_id].sources[src_id] = source; 411 return 0; 412 } 413 414 /** 415 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 416 * 417 * @adev: amdgpu device pointer 418 * @ih: interrupt ring instance 419 * 420 * Dispatches IRQ to IP blocks. 421 */ 422 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 423 struct amdgpu_ih_ring *ih) 424 { 425 u32 ring_index = ih->rptr >> 2; 426 struct amdgpu_iv_entry entry; 427 unsigned client_id, src_id; 428 struct amdgpu_irq_src *src; 429 bool handled = false; 430 int r; 431 432 entry.ih = ih; 433 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 434 amdgpu_ih_decode_iv(adev, &entry); 435 436 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 437 438 client_id = entry.client_id; 439 src_id = entry.src_id; 440 441 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 442 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 443 444 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 445 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 446 447 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) && 448 adev->irq.virq[src_id]) { 449 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); 450 451 } else if (!adev->irq.client[client_id].sources) { 452 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 453 client_id, src_id); 454 455 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 456 r = src->funcs->process(adev, src, &entry); 457 if (r < 0) 458 DRM_ERROR("error processing interrupt (%d)\n", r); 459 else if (r) 460 handled = true; 461 462 } else { 463 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 464 } 465 466 /* Send it to amdkfd as well if it isn't already handled */ 467 if (!handled) 468 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 469 } 470 471 /** 472 * amdgpu_irq_delegate - delegate IV to soft IH ring 473 * 474 * @adev: amdgpu device pointer 475 * @entry: IV entry 476 * @num_dw: size of IV 477 * 478 * Delegate the IV to the soft IH ring and schedule processing of it. Used 479 * if the hardware delegation to IH1 or IH2 doesn't work for some reason. 480 */ 481 void amdgpu_irq_delegate(struct amdgpu_device *adev, 482 struct amdgpu_iv_entry *entry, 483 unsigned int num_dw) 484 { 485 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw); 486 schedule_work(&adev->irq.ih_soft_work); 487 } 488 489 /** 490 * amdgpu_irq_update - update hardware interrupt state 491 * 492 * @adev: amdgpu device pointer 493 * @src: interrupt source pointer 494 * @type: type of interrupt 495 * 496 * Updates interrupt state for the specific source (all ASICs). 497 */ 498 int amdgpu_irq_update(struct amdgpu_device *adev, 499 struct amdgpu_irq_src *src, unsigned type) 500 { 501 unsigned long irqflags; 502 enum amdgpu_interrupt_state state; 503 int r; 504 505 spin_lock_irqsave(&adev->irq.lock, irqflags); 506 507 /* We need to determine after taking the lock, otherwise 508 we might disable just enabled interrupts again */ 509 if (amdgpu_irq_enabled(adev, src, type)) 510 state = AMDGPU_IRQ_STATE_ENABLE; 511 else 512 state = AMDGPU_IRQ_STATE_DISABLE; 513 514 r = src->funcs->set(adev, src, type, state); 515 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 516 return r; 517 } 518 519 /** 520 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 521 * 522 * @adev: amdgpu device pointer 523 * 524 * Updates state of all types of interrupts on all sources on resume after 525 * reset. 526 */ 527 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 528 { 529 int i, j, k; 530 531 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 532 if (!adev->irq.client[i].sources) 533 continue; 534 535 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 536 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 537 538 if (!src) 539 continue; 540 for (k = 0; k < src->num_types; k++) 541 amdgpu_irq_update(adev, src, k); 542 } 543 } 544 } 545 546 /** 547 * amdgpu_irq_get - enable interrupt 548 * 549 * @adev: amdgpu device pointer 550 * @src: interrupt source pointer 551 * @type: type of interrupt 552 * 553 * Enables specified type of interrupt on the specified source (all ASICs). 554 * 555 * Returns: 556 * 0 on success or error code otherwise 557 */ 558 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 559 unsigned type) 560 { 561 if (!adev_to_drm(adev)->irq_enabled) 562 return -ENOENT; 563 564 if (type >= src->num_types) 565 return -EINVAL; 566 567 if (!src->enabled_types || !src->funcs->set) 568 return -EINVAL; 569 570 if (atomic_inc_return(&src->enabled_types[type]) == 1) 571 return amdgpu_irq_update(adev, src, type); 572 573 return 0; 574 } 575 576 /** 577 * amdgpu_irq_put - disable interrupt 578 * 579 * @adev: amdgpu device pointer 580 * @src: interrupt source pointer 581 * @type: type of interrupt 582 * 583 * Enables specified type of interrupt on the specified source (all ASICs). 584 * 585 * Returns: 586 * 0 on success or error code otherwise 587 */ 588 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 589 unsigned type) 590 { 591 if (!adev_to_drm(adev)->irq_enabled) 592 return -ENOENT; 593 594 if (type >= src->num_types) 595 return -EINVAL; 596 597 if (!src->enabled_types || !src->funcs->set) 598 return -EINVAL; 599 600 if (atomic_dec_and_test(&src->enabled_types[type])) 601 return amdgpu_irq_update(adev, src, type); 602 603 return 0; 604 } 605 606 /** 607 * amdgpu_irq_enabled - check whether interrupt is enabled or not 608 * 609 * @adev: amdgpu device pointer 610 * @src: interrupt source pointer 611 * @type: type of interrupt 612 * 613 * Checks whether the given type of interrupt is enabled on the given source. 614 * 615 * Returns: 616 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 617 * invalid parameters 618 */ 619 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 620 unsigned type) 621 { 622 if (!adev_to_drm(adev)->irq_enabled) 623 return false; 624 625 if (type >= src->num_types) 626 return false; 627 628 if (!src->enabled_types || !src->funcs->set) 629 return false; 630 631 return !!atomic_read(&src->enabled_types[type]); 632 } 633 634 /* XXX: Generic IRQ handling */ 635 static void amdgpu_irq_mask(struct irq_data *irqd) 636 { 637 /* XXX */ 638 } 639 640 static void amdgpu_irq_unmask(struct irq_data *irqd) 641 { 642 /* XXX */ 643 } 644 645 /* amdgpu hardware interrupt chip descriptor */ 646 static struct irq_chip amdgpu_irq_chip = { 647 .name = "amdgpu-ih", 648 .irq_mask = amdgpu_irq_mask, 649 .irq_unmask = amdgpu_irq_unmask, 650 }; 651 652 /** 653 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 654 * 655 * @d: amdgpu IRQ domain pointer (unused) 656 * @irq: virtual IRQ number 657 * @hwirq: hardware irq number 658 * 659 * Current implementation assigns simple interrupt handler to the given virtual 660 * IRQ. 661 * 662 * Returns: 663 * 0 on success or error code otherwise 664 */ 665 static int amdgpu_irqdomain_map(struct irq_domain *d, 666 unsigned int irq, irq_hw_number_t hwirq) 667 { 668 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 669 return -EPERM; 670 671 irq_set_chip_and_handler(irq, 672 &amdgpu_irq_chip, handle_simple_irq); 673 return 0; 674 } 675 676 /* Implementation of methods for amdgpu IRQ domain */ 677 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 678 .map = amdgpu_irqdomain_map, 679 }; 680 681 /** 682 * amdgpu_irq_add_domain - create a linear IRQ domain 683 * 684 * @adev: amdgpu device pointer 685 * 686 * Creates an IRQ domain for GPU interrupt sources 687 * that may be driven by another driver (e.g., ACP). 688 * 689 * Returns: 690 * 0 on success or error code otherwise 691 */ 692 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 693 { 694 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 695 &amdgpu_hw_irqdomain_ops, adev); 696 if (!adev->irq.domain) { 697 DRM_ERROR("GPU irq add domain failed\n"); 698 return -ENODEV; 699 } 700 701 return 0; 702 } 703 704 /** 705 * amdgpu_irq_remove_domain - remove the IRQ domain 706 * 707 * @adev: amdgpu device pointer 708 * 709 * Removes the IRQ domain for GPU interrupt sources 710 * that may be driven by another driver (e.g., ACP). 711 */ 712 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 713 { 714 if (adev->irq.domain) { 715 irq_domain_remove(adev->irq.domain); 716 adev->irq.domain = NULL; 717 } 718 } 719 720 /** 721 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 722 * 723 * @adev: amdgpu device pointer 724 * @src_id: IH source id 725 * 726 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 727 * Use this for components that generate a GPU interrupt, but are driven 728 * by a different driver (e.g., ACP). 729 * 730 * Returns: 731 * Linux IRQ 732 */ 733 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) 734 { 735 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 736 737 return adev->irq.virq[src_id]; 738 } 739