1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <drm/drmP.h> 47 #include <drm/drm_crtc_helper.h> 48 #include <drm/amdgpu_drm.h> 49 #include "amdgpu.h" 50 #include "amdgpu_ih.h" 51 #include "atom.h" 52 #include "amdgpu_connectors.h" 53 #include "amdgpu_trace.h" 54 #include "amdgpu_amdkfd.h" 55 56 #include <linux/pm_runtime.h> 57 58 #ifdef CONFIG_DRM_AMD_DC 59 #include "amdgpu_dm_irq.h" 60 #endif 61 62 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 63 64 /** 65 * amdgpu_hotplug_work_func - work handler for display hotplug event 66 * 67 * @work: work struct pointer 68 * 69 * This is the hotplug event work handler (all ASICs). 70 * The work gets scheduled from the IRQ handler if there 71 * was a hotplug interrupt. It walks through the connector table 72 * and calls hotplug handler for each connector. After this, it sends 73 * a DRM hotplug event to alert userspace. 74 * 75 * This design approach is required in order to defer hotplug event handling 76 * from the IRQ handler to a work handler because hotplug handler has to use 77 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may 78 * sleep). 79 */ 80 static void amdgpu_hotplug_work_func(struct work_struct *work) 81 { 82 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 83 hotplug_work); 84 struct drm_device *dev = adev->ddev; 85 struct drm_mode_config *mode_config = &dev->mode_config; 86 struct drm_connector *connector; 87 88 mutex_lock(&mode_config->mutex); 89 list_for_each_entry(connector, &mode_config->connector_list, head) 90 amdgpu_connector_hotplug(connector); 91 mutex_unlock(&mode_config->mutex); 92 /* Just fire off a uevent and let userspace tell us what to do */ 93 drm_helper_hpd_irq_event(dev); 94 } 95 96 /** 97 * amdgpu_irq_disable_all - disable *all* interrupts 98 * 99 * @adev: amdgpu device pointer 100 * 101 * Disable all types of interrupts from all sources. 102 */ 103 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 104 { 105 unsigned long irqflags; 106 unsigned i, j, k; 107 int r; 108 109 spin_lock_irqsave(&adev->irq.lock, irqflags); 110 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 111 if (!adev->irq.client[i].sources) 112 continue; 113 114 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 115 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 116 117 if (!src || !src->funcs->set || !src->num_types) 118 continue; 119 120 for (k = 0; k < src->num_types; ++k) { 121 atomic_set(&src->enabled_types[k], 0); 122 r = src->funcs->set(adev, src, k, 123 AMDGPU_IRQ_STATE_DISABLE); 124 if (r) 125 DRM_ERROR("error disabling interrupt (%d)\n", 126 r); 127 } 128 } 129 } 130 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 131 } 132 133 /** 134 * amdgpu_irq_callback - callback from the IH ring 135 * 136 * @adev: amdgpu device pointer 137 * @ih: amdgpu ih ring 138 * 139 * Callback from IH ring processing to handle the entry at the current position 140 * and advance the read pointer. 141 */ 142 static void amdgpu_irq_callback(struct amdgpu_device *adev, 143 struct amdgpu_ih_ring *ih) 144 { 145 u32 ring_index = ih->rptr >> 2; 146 struct amdgpu_iv_entry entry; 147 148 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 149 amdgpu_ih_decode_iv(adev, &entry); 150 151 amdgpu_irq_dispatch(adev, &entry); 152 } 153 154 /** 155 * amdgpu_irq_handler - IRQ handler 156 * 157 * @irq: IRQ number (unused) 158 * @arg: pointer to DRM device 159 * 160 * IRQ handler for amdgpu driver (all ASICs). 161 * 162 * Returns: 163 * result of handling the IRQ, as defined by &irqreturn_t 164 */ 165 irqreturn_t amdgpu_irq_handler(int irq, void *arg) 166 { 167 struct drm_device *dev = (struct drm_device *) arg; 168 struct amdgpu_device *adev = dev->dev_private; 169 irqreturn_t ret; 170 171 ret = amdgpu_ih_process(adev, &adev->irq.ih, amdgpu_irq_callback); 172 if (ret == IRQ_HANDLED) 173 pm_runtime_mark_last_busy(dev->dev); 174 return ret; 175 } 176 177 /** 178 * amdgpu_msi_ok - check whether MSI functionality is enabled 179 * 180 * @adev: amdgpu device pointer (unused) 181 * 182 * Checks whether MSI functionality has been disabled via module parameter 183 * (all ASICs). 184 * 185 * Returns: 186 * *true* if MSIs are allowed to be enabled or *false* otherwise 187 */ 188 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 189 { 190 if (amdgpu_msi == 1) 191 return true; 192 else if (amdgpu_msi == 0) 193 return false; 194 195 return true; 196 } 197 198 /** 199 * amdgpu_irq_init - initialize interrupt handling 200 * 201 * @adev: amdgpu device pointer 202 * 203 * Sets up work functions for hotplug and reset interrupts, enables MSI 204 * functionality, initializes vblank, hotplug and reset interrupt handling. 205 * 206 * Returns: 207 * 0 on success or error code on failure 208 */ 209 int amdgpu_irq_init(struct amdgpu_device *adev) 210 { 211 int r = 0; 212 213 spin_lock_init(&adev->irq.lock); 214 215 /* Enable MSI if not disabled by module parameter */ 216 adev->irq.msi_enabled = false; 217 218 if (amdgpu_msi_ok(adev)) { 219 int ret = pci_enable_msi(adev->pdev); 220 if (!ret) { 221 adev->irq.msi_enabled = true; 222 dev_dbg(adev->dev, "amdgpu: using MSI.\n"); 223 } 224 } 225 226 if (!amdgpu_device_has_dc_support(adev)) { 227 if (!adev->enable_virtual_display) 228 /* Disable vblank IRQs aggressively for power-saving */ 229 /* XXX: can this be enabled for DC? */ 230 adev->ddev->vblank_disable_immediate = true; 231 232 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); 233 if (r) 234 return r; 235 236 /* Pre-DCE11 */ 237 INIT_WORK(&adev->hotplug_work, 238 amdgpu_hotplug_work_func); 239 } 240 241 adev->irq.installed = true; 242 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); 243 if (r) { 244 adev->irq.installed = false; 245 if (!amdgpu_device_has_dc_support(adev)) 246 flush_work(&adev->hotplug_work); 247 return r; 248 } 249 adev->ddev->max_vblank_count = 0x00ffffff; 250 251 DRM_DEBUG("amdgpu: irq initialized.\n"); 252 return 0; 253 } 254 255 /** 256 * amdgpu_irq_fini - shut down interrupt handling 257 * 258 * @adev: amdgpu device pointer 259 * 260 * Tears down work functions for hotplug and reset interrupts, disables MSI 261 * functionality, shuts down vblank, hotplug and reset interrupt handling, 262 * turns off interrupts from all sources (all ASICs). 263 */ 264 void amdgpu_irq_fini(struct amdgpu_device *adev) 265 { 266 unsigned i, j; 267 268 if (adev->irq.installed) { 269 drm_irq_uninstall(adev->ddev); 270 adev->irq.installed = false; 271 if (adev->irq.msi_enabled) 272 pci_disable_msi(adev->pdev); 273 if (!amdgpu_device_has_dc_support(adev)) 274 flush_work(&adev->hotplug_work); 275 } 276 277 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 278 if (!adev->irq.client[i].sources) 279 continue; 280 281 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 282 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 283 284 if (!src) 285 continue; 286 287 kfree(src->enabled_types); 288 src->enabled_types = NULL; 289 if (src->data) { 290 kfree(src->data); 291 kfree(src); 292 adev->irq.client[i].sources[j] = NULL; 293 } 294 } 295 kfree(adev->irq.client[i].sources); 296 adev->irq.client[i].sources = NULL; 297 } 298 } 299 300 /** 301 * amdgpu_irq_add_id - register IRQ source 302 * 303 * @adev: amdgpu device pointer 304 * @client_id: client id 305 * @src_id: source id 306 * @source: IRQ source pointer 307 * 308 * Registers IRQ source on a client. 309 * 310 * Returns: 311 * 0 on success or error code otherwise 312 */ 313 int amdgpu_irq_add_id(struct amdgpu_device *adev, 314 unsigned client_id, unsigned src_id, 315 struct amdgpu_irq_src *source) 316 { 317 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 318 return -EINVAL; 319 320 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 321 return -EINVAL; 322 323 if (!source->funcs) 324 return -EINVAL; 325 326 if (!adev->irq.client[client_id].sources) { 327 adev->irq.client[client_id].sources = 328 kcalloc(AMDGPU_MAX_IRQ_SRC_ID, 329 sizeof(struct amdgpu_irq_src *), 330 GFP_KERNEL); 331 if (!adev->irq.client[client_id].sources) 332 return -ENOMEM; 333 } 334 335 if (adev->irq.client[client_id].sources[src_id] != NULL) 336 return -EINVAL; 337 338 if (source->num_types && !source->enabled_types) { 339 atomic_t *types; 340 341 types = kcalloc(source->num_types, sizeof(atomic_t), 342 GFP_KERNEL); 343 if (!types) 344 return -ENOMEM; 345 346 source->enabled_types = types; 347 } 348 349 adev->irq.client[client_id].sources[src_id] = source; 350 return 0; 351 } 352 353 /** 354 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 355 * 356 * @adev: amdgpu device pointer 357 * @entry: interrupt vector pointer 358 * 359 * Dispatches IRQ to IP blocks. 360 */ 361 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 362 struct amdgpu_iv_entry *entry) 363 { 364 unsigned client_id = entry->client_id; 365 unsigned src_id = entry->src_id; 366 struct amdgpu_irq_src *src; 367 bool handled = false; 368 int r; 369 370 trace_amdgpu_iv(entry); 371 372 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 373 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); 374 375 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 376 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); 377 378 } else if (adev->irq.virq[src_id]) { 379 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); 380 381 } else if (!adev->irq.client[client_id].sources) { 382 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", 383 client_id, src_id); 384 385 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 386 r = src->funcs->process(adev, src, entry); 387 if (r < 0) 388 DRM_ERROR("error processing interrupt (%d)\n", r); 389 else if (r) 390 handled = true; 391 392 } else { 393 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); 394 } 395 396 /* Send it to amdkfd as well if it isn't already handled */ 397 if (!handled) 398 amdgpu_amdkfd_interrupt(adev, entry->iv_entry); 399 } 400 401 /** 402 * amdgpu_irq_update - update hardware interrupt state 403 * 404 * @adev: amdgpu device pointer 405 * @src: interrupt source pointer 406 * @type: type of interrupt 407 * 408 * Updates interrupt state for the specific source (all ASICs). 409 */ 410 int amdgpu_irq_update(struct amdgpu_device *adev, 411 struct amdgpu_irq_src *src, unsigned type) 412 { 413 unsigned long irqflags; 414 enum amdgpu_interrupt_state state; 415 int r; 416 417 spin_lock_irqsave(&adev->irq.lock, irqflags); 418 419 /* We need to determine after taking the lock, otherwise 420 we might disable just enabled interrupts again */ 421 if (amdgpu_irq_enabled(adev, src, type)) 422 state = AMDGPU_IRQ_STATE_ENABLE; 423 else 424 state = AMDGPU_IRQ_STATE_DISABLE; 425 426 r = src->funcs->set(adev, src, type, state); 427 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 428 return r; 429 } 430 431 /** 432 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 433 * 434 * @adev: amdgpu device pointer 435 * 436 * Updates state of all types of interrupts on all sources on resume after 437 * reset. 438 */ 439 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 440 { 441 int i, j, k; 442 443 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 444 if (!adev->irq.client[i].sources) 445 continue; 446 447 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 448 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 449 450 if (!src) 451 continue; 452 for (k = 0; k < src->num_types; k++) 453 amdgpu_irq_update(adev, src, k); 454 } 455 } 456 } 457 458 /** 459 * amdgpu_irq_get - enable interrupt 460 * 461 * @adev: amdgpu device pointer 462 * @src: interrupt source pointer 463 * @type: type of interrupt 464 * 465 * Enables specified type of interrupt on the specified source (all ASICs). 466 * 467 * Returns: 468 * 0 on success or error code otherwise 469 */ 470 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 471 unsigned type) 472 { 473 if (!adev->ddev->irq_enabled) 474 return -ENOENT; 475 476 if (type >= src->num_types) 477 return -EINVAL; 478 479 if (!src->enabled_types || !src->funcs->set) 480 return -EINVAL; 481 482 if (atomic_inc_return(&src->enabled_types[type]) == 1) 483 return amdgpu_irq_update(adev, src, type); 484 485 return 0; 486 } 487 488 /** 489 * amdgpu_irq_put - disable interrupt 490 * 491 * @adev: amdgpu device pointer 492 * @src: interrupt source pointer 493 * @type: type of interrupt 494 * 495 * Enables specified type of interrupt on the specified source (all ASICs). 496 * 497 * Returns: 498 * 0 on success or error code otherwise 499 */ 500 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 501 unsigned type) 502 { 503 if (!adev->ddev->irq_enabled) 504 return -ENOENT; 505 506 if (type >= src->num_types) 507 return -EINVAL; 508 509 if (!src->enabled_types || !src->funcs->set) 510 return -EINVAL; 511 512 if (atomic_dec_and_test(&src->enabled_types[type])) 513 return amdgpu_irq_update(adev, src, type); 514 515 return 0; 516 } 517 518 /** 519 * amdgpu_irq_enabled - check whether interrupt is enabled or not 520 * 521 * @adev: amdgpu device pointer 522 * @src: interrupt source pointer 523 * @type: type of interrupt 524 * 525 * Checks whether the given type of interrupt is enabled on the given source. 526 * 527 * Returns: 528 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 529 * invalid parameters 530 */ 531 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 532 unsigned type) 533 { 534 if (!adev->ddev->irq_enabled) 535 return false; 536 537 if (type >= src->num_types) 538 return false; 539 540 if (!src->enabled_types || !src->funcs->set) 541 return false; 542 543 return !!atomic_read(&src->enabled_types[type]); 544 } 545 546 /* XXX: Generic IRQ handling */ 547 static void amdgpu_irq_mask(struct irq_data *irqd) 548 { 549 /* XXX */ 550 } 551 552 static void amdgpu_irq_unmask(struct irq_data *irqd) 553 { 554 /* XXX */ 555 } 556 557 /* amdgpu hardware interrupt chip descriptor */ 558 static struct irq_chip amdgpu_irq_chip = { 559 .name = "amdgpu-ih", 560 .irq_mask = amdgpu_irq_mask, 561 .irq_unmask = amdgpu_irq_unmask, 562 }; 563 564 /** 565 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 566 * 567 * @d: amdgpu IRQ domain pointer (unused) 568 * @irq: virtual IRQ number 569 * @hwirq: hardware irq number 570 * 571 * Current implementation assigns simple interrupt handler to the given virtual 572 * IRQ. 573 * 574 * Returns: 575 * 0 on success or error code otherwise 576 */ 577 static int amdgpu_irqdomain_map(struct irq_domain *d, 578 unsigned int irq, irq_hw_number_t hwirq) 579 { 580 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 581 return -EPERM; 582 583 irq_set_chip_and_handler(irq, 584 &amdgpu_irq_chip, handle_simple_irq); 585 return 0; 586 } 587 588 /* Implementation of methods for amdgpu IRQ domain */ 589 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 590 .map = amdgpu_irqdomain_map, 591 }; 592 593 /** 594 * amdgpu_irq_add_domain - create a linear IRQ domain 595 * 596 * @adev: amdgpu device pointer 597 * 598 * Creates an IRQ domain for GPU interrupt sources 599 * that may be driven by another driver (e.g., ACP). 600 * 601 * Returns: 602 * 0 on success or error code otherwise 603 */ 604 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 605 { 606 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 607 &amdgpu_hw_irqdomain_ops, adev); 608 if (!adev->irq.domain) { 609 DRM_ERROR("GPU irq add domain failed\n"); 610 return -ENODEV; 611 } 612 613 return 0; 614 } 615 616 /** 617 * amdgpu_irq_remove_domain - remove the IRQ domain 618 * 619 * @adev: amdgpu device pointer 620 * 621 * Removes the IRQ domain for GPU interrupt sources 622 * that may be driven by another driver (e.g., ACP). 623 */ 624 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 625 { 626 if (adev->irq.domain) { 627 irq_domain_remove(adev->irq.domain); 628 adev->irq.domain = NULL; 629 } 630 } 631 632 /** 633 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 634 * 635 * @adev: amdgpu device pointer 636 * @src_id: IH source id 637 * 638 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 639 * Use this for components that generate a GPU interrupt, but are driven 640 * by a different driver (e.g., ACP). 641 * 642 * Returns: 643 * Linux IRQ 644 */ 645 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) 646 { 647 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 648 649 return adev->irq.virq[src_id]; 650 } 651