1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_IH_H__ 25 #define __AMDGPU_IH_H__ 26 27 #include "soc15_ih_clientid.h" 28 29 struct amdgpu_device; 30 31 #define AMDGPU_IH_CLIENTID_LEGACY 0 32 #define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX 33 34 /* 35 * R6xx+ IH ring 36 */ 37 struct amdgpu_ih_ring { 38 struct amdgpu_bo *ring_obj; 39 volatile uint32_t *ring; 40 unsigned rptr; 41 unsigned ring_size; 42 uint64_t gpu_addr; 43 uint32_t ptr_mask; 44 atomic_t lock; 45 bool enabled; 46 unsigned wptr_offs; 47 unsigned rptr_offs; 48 u32 doorbell_index; 49 bool use_doorbell; 50 bool use_bus_addr; 51 dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ 52 }; 53 54 #define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4 55 56 struct amdgpu_iv_entry { 57 unsigned client_id; 58 unsigned src_id; 59 unsigned ring_id; 60 unsigned vmid; 61 unsigned vmid_src; 62 uint64_t timestamp; 63 unsigned timestamp_src; 64 unsigned pasid; 65 unsigned pasid_src; 66 unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW]; 67 const uint32_t *iv_entry; 68 }; 69 70 /* provided by the ih block */ 71 struct amdgpu_ih_funcs { 72 /* ring read/write ptr handling, called from interrupt context */ 73 u32 (*get_wptr)(struct amdgpu_device *adev); 74 bool (*prescreen_iv)(struct amdgpu_device *adev); 75 void (*decode_iv)(struct amdgpu_device *adev, 76 struct amdgpu_iv_entry *entry); 77 void (*set_rptr)(struct amdgpu_device *adev); 78 }; 79 80 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 81 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 82 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 83 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 84 85 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, 86 bool use_bus_addr); 87 void amdgpu_ih_ring_fini(struct amdgpu_device *adev); 88 int amdgpu_ih_process(struct amdgpu_device *adev); 89 90 #endif 91