1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/dma-mapping.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 /** 30 * amdgpu_ih_ring_init - initialize the IH state 31 * 32 * @adev: amdgpu_device pointer 33 * @ih: ih ring to initialize 34 * @ring_size: ring size to allocate 35 * @use_bus_addr: true when we can use dma_alloc_coherent 36 * 37 * Initializes the IH state and allocates a buffer 38 * for the IH ring buffer. 39 * Returns 0 for success, errors for failure. 40 */ 41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 42 unsigned ring_size, bool use_bus_addr) 43 { 44 u32 rb_bufsz; 45 int r; 46 47 /* Align ring size */ 48 rb_bufsz = order_base_2(ring_size / 4); 49 ring_size = (1 << rb_bufsz) * 4; 50 ih->ring_size = ring_size; 51 ih->ptr_mask = ih->ring_size - 1; 52 ih->rptr = 0; 53 ih->use_bus_addr = use_bus_addr; 54 55 if (use_bus_addr) { 56 dma_addr_t dma_addr; 57 58 if (ih->ring) 59 return 0; 60 61 /* add 8 bytes for the rptr/wptr shadows and 62 * add them to the end of the ring allocation. 63 */ 64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, 65 &dma_addr, GFP_KERNEL); 66 if (ih->ring == NULL) 67 return -ENOMEM; 68 69 ih->gpu_addr = dma_addr; 70 ih->wptr_addr = dma_addr + ih->ring_size; 71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; 72 ih->rptr_addr = dma_addr + ih->ring_size + 4; 73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; 74 } else { 75 unsigned wptr_offs, rptr_offs; 76 77 r = amdgpu_device_wb_get(adev, &wptr_offs); 78 if (r) 79 return r; 80 81 r = amdgpu_device_wb_get(adev, &rptr_offs); 82 if (r) { 83 amdgpu_device_wb_free(adev, wptr_offs); 84 return r; 85 } 86 87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, 88 AMDGPU_GEM_DOMAIN_GTT, 89 &ih->ring_obj, &ih->gpu_addr, 90 (void **)&ih->ring); 91 if (r) { 92 amdgpu_device_wb_free(adev, rptr_offs); 93 amdgpu_device_wb_free(adev, wptr_offs); 94 return r; 95 } 96 97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; 98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; 99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; 100 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; 101 } 102 103 init_waitqueue_head(&ih->wait_process); 104 return 0; 105 } 106 107 /** 108 * amdgpu_ih_ring_fini - tear down the IH state 109 * 110 * @adev: amdgpu_device pointer 111 * @ih: ih ring to tear down 112 * 113 * Tears down the IH state and frees buffer 114 * used for the IH ring buffer. 115 */ 116 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 117 { 118 if (ih->use_bus_addr) { 119 if (!ih->ring) 120 return; 121 122 /* add 8 bytes for the rptr/wptr shadows and 123 * add them to the end of the ring allocation. 124 */ 125 dma_free_coherent(adev->dev, ih->ring_size + 8, 126 (void *)ih->ring, ih->gpu_addr); 127 ih->ring = NULL; 128 } else { 129 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, 130 (void **)&ih->ring); 131 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); 132 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); 133 } 134 } 135 136 /** 137 * amdgpu_ih_ring_write - write IV to the ring buffer 138 * 139 * @ih: ih ring to write to 140 * @iv: the iv to write 141 * @num_dw: size of the iv in dw 142 * 143 * Writes an IV to the ring buffer using the CPU and increment the wptr. 144 * Used for testing and delegating IVs to a software ring. 145 */ 146 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, 147 unsigned int num_dw) 148 { 149 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; 150 unsigned int i; 151 152 for (i = 0; i < num_dw; ++i) 153 ih->ring[wptr++] = cpu_to_le32(iv[i]); 154 155 wptr <<= 2; 156 wptr &= ih->ptr_mask; 157 158 /* Only commit the new wptr if we don't overflow */ 159 if (wptr != READ_ONCE(ih->rptr)) { 160 wmb(); 161 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); 162 } 163 } 164 165 /* Waiter helper that checks current rptr matches or passes checkpoint wptr */ 166 static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev, 167 struct amdgpu_ih_ring *ih, 168 uint32_t checkpoint_wptr, 169 uint32_t *prev_rptr) 170 { 171 uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask); 172 173 /* rptr has wrapped. */ 174 if (cur_rptr < *prev_rptr) 175 cur_rptr += ih->ptr_mask + 1; 176 *prev_rptr = cur_rptr; 177 178 return cur_rptr >= checkpoint_wptr; 179 } 180 181 /** 182 * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint 183 * 184 * @adev: amdgpu_device pointer 185 * @ih: ih ring to process 186 * 187 * Used to ensure ring has processed IVs up to the checkpoint write pointer. 188 */ 189 int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, 190 struct amdgpu_ih_ring *ih) 191 { 192 uint32_t checkpoint_wptr, rptr; 193 194 if (!ih->enabled || adev->shutdown) 195 return -ENODEV; 196 197 checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); 198 /* Order wptr with rptr. */ 199 rmb(); 200 rptr = READ_ONCE(ih->rptr); 201 202 /* wptr has wrapped. */ 203 if (rptr > checkpoint_wptr) 204 checkpoint_wptr += ih->ptr_mask + 1; 205 206 return wait_event_interruptible(ih->wait_process, 207 amdgpu_ih_has_checkpoint_processed(adev, ih, 208 checkpoint_wptr, &rptr)); 209 } 210 211 /** 212 * amdgpu_ih_process - interrupt handler 213 * 214 * @adev: amdgpu_device pointer 215 * @ih: ih ring to process 216 * 217 * Interrupt hander (VI), walk the IH ring. 218 * Returns irq process return code. 219 */ 220 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 221 { 222 unsigned int count = AMDGPU_IH_MAX_NUM_IVS; 223 u32 wptr; 224 225 if (!ih->enabled || adev->shutdown) 226 return IRQ_NONE; 227 228 wptr = amdgpu_ih_get_wptr(adev, ih); 229 230 restart_ih: 231 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); 232 233 /* Order reading of wptr vs. reading of IH ring data */ 234 rmb(); 235 236 while (ih->rptr != wptr && --count) { 237 amdgpu_irq_dispatch(adev, ih); 238 ih->rptr &= ih->ptr_mask; 239 } 240 241 amdgpu_ih_set_rptr(adev, ih); 242 wake_up_all(&ih->wait_process); 243 244 /* make sure wptr hasn't changed while processing */ 245 wptr = amdgpu_ih_get_wptr(adev, ih); 246 if (wptr != ih->rptr) 247 goto restart_ih; 248 249 return IRQ_HANDLED; 250 } 251 252 /** 253 * amdgpu_ih_decode_iv_helper - decode an interrupt vector 254 * 255 * @adev: amdgpu_device pointer 256 * @ih: ih ring to process 257 * @entry: IV entry 258 * 259 * Decodes the interrupt vector at the current rptr 260 * position and also advance the position for for Vega10 261 * and later GPUs. 262 */ 263 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, 264 struct amdgpu_ih_ring *ih, 265 struct amdgpu_iv_entry *entry) 266 { 267 /* wptr/rptr are in bytes! */ 268 u32 ring_index = ih->rptr >> 2; 269 uint32_t dw[8]; 270 271 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 272 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 273 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 274 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 275 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 276 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 277 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 278 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 279 280 entry->client_id = dw[0] & 0xff; 281 entry->src_id = (dw[0] >> 8) & 0xff; 282 entry->ring_id = (dw[0] >> 16) & 0xff; 283 entry->vmid = (dw[0] >> 24) & 0xf; 284 entry->vmid_src = (dw[0] >> 31); 285 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 286 entry->timestamp_src = dw[2] >> 31; 287 entry->pasid = dw[3] & 0xffff; 288 entry->pasid_src = dw[3] >> 31; 289 entry->src_data[0] = dw[4]; 290 entry->src_data[1] = dw[5]; 291 entry->src_data[2] = dw[6]; 292 entry->src_data[3] = dw[7]; 293 294 /* wptr/rptr are in bytes! */ 295 ih->rptr += 32; 296 } 297