1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/dma-mapping.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 /** 30 * amdgpu_ih_ring_init - initialize the IH state 31 * 32 * @adev: amdgpu_device pointer 33 * @ih: ih ring to initialize 34 * @ring_size: ring size to allocate 35 * @use_bus_addr: true when we can use dma_alloc_coherent 36 * 37 * Initializes the IH state and allocates a buffer 38 * for the IH ring buffer. 39 * Returns 0 for success, errors for failure. 40 */ 41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 42 unsigned ring_size, bool use_bus_addr) 43 { 44 u32 rb_bufsz; 45 int r; 46 47 /* Align ring size */ 48 rb_bufsz = order_base_2(ring_size / 4); 49 ring_size = (1 << rb_bufsz) * 4; 50 ih->ring_size = ring_size; 51 ih->ptr_mask = ih->ring_size - 1; 52 ih->rptr = 0; 53 ih->use_bus_addr = use_bus_addr; 54 55 if (use_bus_addr) { 56 dma_addr_t dma_addr; 57 58 if (ih->ring) 59 return 0; 60 61 /* add 8 bytes for the rptr/wptr shadows and 62 * add them to the end of the ring allocation. 63 */ 64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, 65 &dma_addr, GFP_KERNEL); 66 if (ih->ring == NULL) 67 return -ENOMEM; 68 69 ih->gpu_addr = dma_addr; 70 ih->wptr_addr = dma_addr + ih->ring_size; 71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; 72 ih->rptr_addr = dma_addr + ih->ring_size + 4; 73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; 74 } else { 75 unsigned wptr_offs, rptr_offs; 76 77 r = amdgpu_device_wb_get(adev, &wptr_offs); 78 if (r) 79 return r; 80 81 r = amdgpu_device_wb_get(adev, &rptr_offs); 82 if (r) { 83 amdgpu_device_wb_free(adev, wptr_offs); 84 return r; 85 } 86 87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, 88 AMDGPU_GEM_DOMAIN_GTT, 89 &ih->ring_obj, &ih->gpu_addr, 90 (void **)&ih->ring); 91 if (r) { 92 amdgpu_device_wb_free(adev, rptr_offs); 93 amdgpu_device_wb_free(adev, wptr_offs); 94 return r; 95 } 96 97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; 98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; 99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; 100 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; 101 } 102 103 init_waitqueue_head(&ih->wait_process); 104 return 0; 105 } 106 107 /** 108 * amdgpu_ih_ring_fini - tear down the IH state 109 * 110 * @adev: amdgpu_device pointer 111 * @ih: ih ring to tear down 112 * 113 * Tears down the IH state and frees buffer 114 * used for the IH ring buffer. 115 */ 116 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 117 { 118 119 if (!ih->ring) 120 return; 121 122 if (ih->use_bus_addr) { 123 124 /* add 8 bytes for the rptr/wptr shadows and 125 * add them to the end of the ring allocation. 126 */ 127 dma_free_coherent(adev->dev, ih->ring_size + 8, 128 (void *)ih->ring, ih->gpu_addr); 129 ih->ring = NULL; 130 } else { 131 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, 132 (void **)&ih->ring); 133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); 134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); 135 } 136 } 137 138 /** 139 * amdgpu_ih_ring_write - write IV to the ring buffer 140 * 141 * @ih: ih ring to write to 142 * @iv: the iv to write 143 * @num_dw: size of the iv in dw 144 * 145 * Writes an IV to the ring buffer using the CPU and increment the wptr. 146 * Used for testing and delegating IVs to a software ring. 147 */ 148 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, 149 unsigned int num_dw) 150 { 151 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; 152 unsigned int i; 153 154 for (i = 0; i < num_dw; ++i) 155 ih->ring[wptr++] = cpu_to_le32(iv[i]); 156 157 wptr <<= 2; 158 wptr &= ih->ptr_mask; 159 160 /* Only commit the new wptr if we don't overflow */ 161 if (wptr != READ_ONCE(ih->rptr)) { 162 wmb(); 163 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); 164 } 165 } 166 167 /* Waiter helper that checks current rptr matches or passes checkpoint wptr */ 168 static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev, 169 struct amdgpu_ih_ring *ih, 170 uint32_t checkpoint_wptr, 171 uint32_t *prev_rptr) 172 { 173 uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask); 174 175 /* rptr has wrapped. */ 176 if (cur_rptr < *prev_rptr) 177 cur_rptr += ih->ptr_mask + 1; 178 *prev_rptr = cur_rptr; 179 180 return cur_rptr >= checkpoint_wptr; 181 } 182 183 /** 184 * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint 185 * 186 * @adev: amdgpu_device pointer 187 * @ih: ih ring to process 188 * 189 * Used to ensure ring has processed IVs up to the checkpoint write pointer. 190 */ 191 int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, 192 struct amdgpu_ih_ring *ih) 193 { 194 uint32_t checkpoint_wptr, rptr; 195 196 if (!ih->enabled || adev->shutdown) 197 return -ENODEV; 198 199 checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); 200 /* Order wptr with rptr. */ 201 rmb(); 202 rptr = READ_ONCE(ih->rptr); 203 204 /* wptr has wrapped. */ 205 if (rptr > checkpoint_wptr) 206 checkpoint_wptr += ih->ptr_mask + 1; 207 208 return wait_event_interruptible(ih->wait_process, 209 amdgpu_ih_has_checkpoint_processed(adev, ih, 210 checkpoint_wptr, &rptr)); 211 } 212 213 /** 214 * amdgpu_ih_process - interrupt handler 215 * 216 * @adev: amdgpu_device pointer 217 * @ih: ih ring to process 218 * 219 * Interrupt hander (VI), walk the IH ring. 220 * Returns irq process return code. 221 */ 222 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 223 { 224 unsigned int count = AMDGPU_IH_MAX_NUM_IVS; 225 u32 wptr; 226 227 if (!ih->enabled || adev->shutdown) 228 return IRQ_NONE; 229 230 wptr = amdgpu_ih_get_wptr(adev, ih); 231 232 restart_ih: 233 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); 234 235 /* Order reading of wptr vs. reading of IH ring data */ 236 rmb(); 237 238 while (ih->rptr != wptr && --count) { 239 amdgpu_irq_dispatch(adev, ih); 240 ih->rptr &= ih->ptr_mask; 241 } 242 243 amdgpu_ih_set_rptr(adev, ih); 244 wake_up_all(&ih->wait_process); 245 246 /* make sure wptr hasn't changed while processing */ 247 wptr = amdgpu_ih_get_wptr(adev, ih); 248 if (wptr != ih->rptr) 249 goto restart_ih; 250 251 return IRQ_HANDLED; 252 } 253 254 /** 255 * amdgpu_ih_decode_iv_helper - decode an interrupt vector 256 * 257 * @adev: amdgpu_device pointer 258 * @ih: ih ring to process 259 * @entry: IV entry 260 * 261 * Decodes the interrupt vector at the current rptr 262 * position and also advance the position for for Vega10 263 * and later GPUs. 264 */ 265 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, 266 struct amdgpu_ih_ring *ih, 267 struct amdgpu_iv_entry *entry) 268 { 269 /* wptr/rptr are in bytes! */ 270 u32 ring_index = ih->rptr >> 2; 271 uint32_t dw[8]; 272 273 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 274 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 275 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 276 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 277 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 278 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 279 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 280 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 281 282 entry->client_id = dw[0] & 0xff; 283 entry->src_id = (dw[0] >> 8) & 0xff; 284 entry->ring_id = (dw[0] >> 16) & 0xff; 285 entry->vmid = (dw[0] >> 24) & 0xf; 286 entry->vmid_src = (dw[0] >> 31); 287 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 288 entry->timestamp_src = dw[2] >> 31; 289 entry->pasid = dw[3] & 0xffff; 290 entry->pasid_src = dw[3] >> 31; 291 entry->src_data[0] = dw[4]; 292 entry->src_data[1] = dw[5]; 293 entry->src_data[2] = dw[6]; 294 entry->src_data[3] = dw[7]; 295 296 /* wptr/rptr are in bytes! */ 297 ih->rptr += 32; 298 } 299