1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/dma-mapping.h>
25 
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 
29 /**
30  * amdgpu_ih_ring_init - initialize the IH state
31  *
32  * @adev: amdgpu_device pointer
33  * @ih: ih ring to initialize
34  * @ring_size: ring size to allocate
35  * @use_bus_addr: true when we can use dma_alloc_coherent
36  *
37  * Initializes the IH state and allocates a buffer
38  * for the IH ring buffer.
39  * Returns 0 for success, errors for failure.
40  */
41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
42 			unsigned ring_size, bool use_bus_addr)
43 {
44 	u32 rb_bufsz;
45 	int r;
46 
47 	/* Align ring size */
48 	rb_bufsz = order_base_2(ring_size / 4);
49 	ring_size = (1 << rb_bufsz) * 4;
50 	ih->ring_size = ring_size;
51 	ih->ptr_mask = ih->ring_size - 1;
52 	ih->rptr = 0;
53 	ih->use_bus_addr = use_bus_addr;
54 
55 	if (use_bus_addr) {
56 		dma_addr_t dma_addr;
57 
58 		if (ih->ring)
59 			return 0;
60 
61 		/* add 8 bytes for the rptr/wptr shadows and
62 		 * add them to the end of the ring allocation.
63 		 */
64 		ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
65 					      &dma_addr, GFP_KERNEL);
66 		if (ih->ring == NULL)
67 			return -ENOMEM;
68 
69 		ih->gpu_addr = dma_addr;
70 		ih->wptr_addr = dma_addr + ih->ring_size;
71 		ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
72 		ih->rptr_addr = dma_addr + ih->ring_size + 4;
73 		ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
74 	} else {
75 		unsigned wptr_offs, rptr_offs;
76 
77 		r = amdgpu_device_wb_get(adev, &wptr_offs);
78 		if (r)
79 			return r;
80 
81 		r = amdgpu_device_wb_get(adev, &rptr_offs);
82 		if (r) {
83 			amdgpu_device_wb_free(adev, wptr_offs);
84 			return r;
85 		}
86 
87 		r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
88 					    AMDGPU_GEM_DOMAIN_GTT,
89 					    &ih->ring_obj, &ih->gpu_addr,
90 					    (void **)&ih->ring);
91 		if (r) {
92 			amdgpu_device_wb_free(adev, rptr_offs);
93 			amdgpu_device_wb_free(adev, wptr_offs);
94 			return r;
95 		}
96 
97 		ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
98 		ih->wptr_cpu = &adev->wb.wb[wptr_offs];
99 		ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
100 		ih->rptr_cpu = &adev->wb.wb[rptr_offs];
101 	}
102 	return 0;
103 }
104 
105 /**
106  * amdgpu_ih_ring_fini - tear down the IH state
107  *
108  * @adev: amdgpu_device pointer
109  * @ih: ih ring to tear down
110  *
111  * Tears down the IH state and frees buffer
112  * used for the IH ring buffer.
113  */
114 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
115 {
116 	if (ih->use_bus_addr) {
117 		if (!ih->ring)
118 			return;
119 
120 		/* add 8 bytes for the rptr/wptr shadows and
121 		 * add them to the end of the ring allocation.
122 		 */
123 		dma_free_coherent(adev->dev, ih->ring_size + 8,
124 				  (void *)ih->ring, ih->gpu_addr);
125 		ih->ring = NULL;
126 	} else {
127 		amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
128 				      (void **)&ih->ring);
129 		amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
130 		amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
131 	}
132 }
133 
134 /**
135  * amdgpu_ih_ring_write - write IV to the ring buffer
136  *
137  * @ih: ih ring to write to
138  * @iv: the iv to write
139  * @num_dw: size of the iv in dw
140  *
141  * Writes an IV to the ring buffer using the CPU and increment the wptr.
142  * Used for testing and delegating IVs to a software ring.
143  */
144 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
145 			  unsigned int num_dw)
146 {
147 	uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
148 	unsigned int i;
149 
150 	for (i = 0; i < num_dw; ++i)
151 	        ih->ring[wptr++] = cpu_to_le32(iv[i]);
152 
153 	wptr <<= 2;
154 	wptr &= ih->ptr_mask;
155 
156 	/* Only commit the new wptr if we don't overflow */
157 	if (wptr != READ_ONCE(ih->rptr)) {
158 		wmb();
159 		WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
160 	}
161 }
162 
163 /**
164  * amdgpu_ih_process - interrupt handler
165  *
166  * @adev: amdgpu_device pointer
167  * @ih: ih ring to process
168  *
169  * Interrupt hander (VI), walk the IH ring.
170  * Returns irq process return code.
171  */
172 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
173 {
174 	unsigned int count = AMDGPU_IH_MAX_NUM_IVS;
175 	u32 wptr;
176 
177 	if (!ih->enabled || adev->shutdown)
178 		return IRQ_NONE;
179 
180 	wptr = amdgpu_ih_get_wptr(adev, ih);
181 
182 restart_ih:
183 	/* is somebody else already processing irqs? */
184 	if (atomic_xchg(&ih->lock, 1))
185 		return IRQ_NONE;
186 
187 	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
188 
189 	/* Order reading of wptr vs. reading of IH ring data */
190 	rmb();
191 
192 	while (ih->rptr != wptr && --count) {
193 		amdgpu_irq_dispatch(adev, ih);
194 		ih->rptr &= ih->ptr_mask;
195 	}
196 
197 	amdgpu_ih_set_rptr(adev, ih);
198 	atomic_set(&ih->lock, 0);
199 
200 	/* make sure wptr hasn't changed while processing */
201 	wptr = amdgpu_ih_get_wptr(adev, ih);
202 	if (wptr != ih->rptr)
203 		goto restart_ih;
204 
205 	return IRQ_HANDLED;
206 }
207 
208