1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/dma-mapping.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 /** 30 * amdgpu_ih_ring_init - initialize the IH state 31 * 32 * @adev: amdgpu_device pointer 33 * @ih: ih ring to initialize 34 * @ring_size: ring size to allocate 35 * @use_bus_addr: true when we can use dma_alloc_coherent 36 * 37 * Initializes the IH state and allocates a buffer 38 * for the IH ring buffer. 39 * Returns 0 for success, errors for failure. 40 */ 41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 42 unsigned ring_size, bool use_bus_addr) 43 { 44 u32 rb_bufsz; 45 int r; 46 47 /* Align ring size */ 48 rb_bufsz = order_base_2(ring_size / 4); 49 ring_size = (1 << rb_bufsz) * 4; 50 ih->ring_size = ring_size; 51 ih->ptr_mask = ih->ring_size - 1; 52 ih->rptr = 0; 53 ih->use_bus_addr = use_bus_addr; 54 55 if (use_bus_addr) { 56 dma_addr_t dma_addr; 57 58 if (ih->ring) 59 return 0; 60 61 /* add 8 bytes for the rptr/wptr shadows and 62 * add them to the end of the ring allocation. 63 */ 64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, 65 &dma_addr, GFP_KERNEL); 66 if (ih->ring == NULL) 67 return -ENOMEM; 68 69 memset((void *)ih->ring, 0, ih->ring_size + 8); 70 ih->gpu_addr = dma_addr; 71 ih->wptr_addr = dma_addr + ih->ring_size; 72 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; 73 ih->rptr_addr = dma_addr + ih->ring_size + 4; 74 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; 75 } else { 76 unsigned wptr_offs, rptr_offs; 77 78 r = amdgpu_device_wb_get(adev, &wptr_offs); 79 if (r) 80 return r; 81 82 r = amdgpu_device_wb_get(adev, &rptr_offs); 83 if (r) { 84 amdgpu_device_wb_free(adev, wptr_offs); 85 return r; 86 } 87 88 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, 89 AMDGPU_GEM_DOMAIN_GTT, 90 &ih->ring_obj, &ih->gpu_addr, 91 (void **)&ih->ring); 92 if (r) { 93 amdgpu_device_wb_free(adev, rptr_offs); 94 amdgpu_device_wb_free(adev, wptr_offs); 95 return r; 96 } 97 98 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; 99 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; 100 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; 101 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; 102 } 103 return 0; 104 } 105 106 /** 107 * amdgpu_ih_ring_fini - tear down the IH state 108 * 109 * @adev: amdgpu_device pointer 110 * @ih: ih ring to tear down 111 * 112 * Tears down the IH state and frees buffer 113 * used for the IH ring buffer. 114 */ 115 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 116 { 117 if (ih->use_bus_addr) { 118 if (!ih->ring) 119 return; 120 121 /* add 8 bytes for the rptr/wptr shadows and 122 * add them to the end of the ring allocation. 123 */ 124 dma_free_coherent(adev->dev, ih->ring_size + 8, 125 (void *)ih->ring, ih->gpu_addr); 126 ih->ring = NULL; 127 } else { 128 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, 129 (void **)&ih->ring); 130 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); 131 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); 132 } 133 } 134 135 /** 136 * amdgpu_ih_process - interrupt handler 137 * 138 * @adev: amdgpu_device pointer 139 * @ih: ih ring to process 140 * 141 * Interrupt hander (VI), walk the IH ring. 142 * Returns irq process return code. 143 */ 144 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 145 { 146 unsigned int count = AMDGPU_IH_MAX_NUM_IVS; 147 u32 wptr; 148 149 if (!ih->enabled || adev->shutdown) 150 return IRQ_NONE; 151 152 wptr = amdgpu_ih_get_wptr(adev, ih); 153 154 restart_ih: 155 /* is somebody else already processing irqs? */ 156 if (atomic_xchg(&ih->lock, 1)) 157 return IRQ_NONE; 158 159 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); 160 161 /* Order reading of wptr vs. reading of IH ring data */ 162 rmb(); 163 164 while (ih->rptr != wptr && --count) { 165 amdgpu_irq_dispatch(adev, ih); 166 ih->rptr &= ih->ptr_mask; 167 } 168 169 amdgpu_ih_set_rptr(adev, ih); 170 atomic_set(&ih->lock, 0); 171 172 /* make sure wptr hasn't changed while processing */ 173 wptr = amdgpu_ih_get_wptr(adev, ih); 174 if (wptr != ih->rptr) 175 goto restart_ih; 176 177 return IRQ_HANDLED; 178 } 179 180