1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_debugfs.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_trace.h" 38 39 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 40 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 41 42 /* 43 * IB 44 * IBs (Indirect Buffers) and areas of GPU accessible memory where 45 * commands are stored. You can put a pointer to the IB in the 46 * command ring and the hw will fetch the commands from the IB 47 * and execute them. Generally userspace acceleration drivers 48 * produce command buffers which are send to the kernel and 49 * put in IBs for execution by the requested ring. 50 */ 51 52 /** 53 * amdgpu_ib_get - request an IB (Indirect Buffer) 54 * 55 * @adev: amdgpu_device pointer 56 * @vm: amdgpu_vm pointer 57 * @size: requested IB size 58 * @pool_type: IB pool type (delayed, immediate, direct) 59 * @ib: IB object returned 60 * 61 * Request an IB (all asics). IBs are allocated using the 62 * suballocator. 63 * Returns 0 on success, error on failure. 64 */ 65 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 66 unsigned size, enum amdgpu_ib_pool_type pool_type, 67 struct amdgpu_ib *ib) 68 { 69 int r; 70 71 if (size) { 72 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], 73 &ib->sa_bo, size, 256); 74 if (r) { 75 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 76 return r; 77 } 78 79 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 80 81 if (!vm) 82 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 83 } 84 85 return 0; 86 } 87 88 /** 89 * amdgpu_ib_free - free an IB (Indirect Buffer) 90 * 91 * @adev: amdgpu_device pointer 92 * @ib: IB object to free 93 * @f: the fence SA bo need wait on for the ib alloation 94 * 95 * Free an IB (all asics). 96 */ 97 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 98 struct dma_fence *f) 99 { 100 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 101 } 102 103 /** 104 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 105 * 106 * @ring: ring index the IB is associated with 107 * @num_ibs: number of IBs to schedule 108 * @ibs: IB objects to schedule 109 * @job: job to schedule 110 * @f: fence created during this submission 111 * 112 * Schedule an IB on the associated ring (all asics). 113 * Returns 0 on success, error on failure. 114 * 115 * On SI, there are two parallel engines fed from the primary ring, 116 * the CE (Constant Engine) and the DE (Drawing Engine). Since 117 * resource descriptors have moved to memory, the CE allows you to 118 * prime the caches while the DE is updating register state so that 119 * the resource descriptors will be already in cache when the draw is 120 * processed. To accomplish this, the userspace driver submits two 121 * IBs, one for the CE and one for the DE. If there is a CE IB (called 122 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 123 * to SI there was just a DE IB. 124 */ 125 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 126 struct amdgpu_ib *ibs, struct amdgpu_job *job, 127 struct dma_fence **f) 128 { 129 struct amdgpu_device *adev = ring->adev; 130 struct amdgpu_ib *ib = &ibs[0]; 131 struct dma_fence *tmp = NULL; 132 bool skip_preamble, need_ctx_switch; 133 unsigned patch_offset = ~0; 134 struct amdgpu_vm *vm; 135 uint64_t fence_ctx; 136 uint32_t status = 0, alloc_size; 137 unsigned fence_flags = 0; 138 bool secure; 139 140 unsigned i; 141 int r = 0; 142 bool need_pipe_sync = false; 143 144 if (num_ibs == 0) 145 return -EINVAL; 146 147 /* ring tests don't use a job */ 148 if (job) { 149 vm = job->vm; 150 fence_ctx = job->base.s_fence ? 151 job->base.s_fence->scheduled.context : 0; 152 } else { 153 vm = NULL; 154 fence_ctx = 0; 155 } 156 157 if (!ring->sched.ready) { 158 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 159 return -EINVAL; 160 } 161 162 if (vm && !job->vmid) { 163 dev_err(adev->dev, "VM IB without ID\n"); 164 return -EINVAL; 165 } 166 167 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 168 (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) { 169 dev_err(adev->dev, "secure submissions not supported on compute rings\n"); 170 return -EINVAL; 171 } 172 173 alloc_size = ring->funcs->emit_frame_size + num_ibs * 174 ring->funcs->emit_ib_size; 175 176 r = amdgpu_ring_alloc(ring, alloc_size); 177 if (r) { 178 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 179 return r; 180 } 181 182 need_ctx_switch = ring->current_ctx != fence_ctx; 183 if (ring->funcs->emit_pipeline_sync && job && 184 ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) || 185 (amdgpu_sriov_vf(adev) && need_ctx_switch) || 186 amdgpu_vm_need_pipeline_sync(ring, job))) { 187 need_pipe_sync = true; 188 189 if (tmp) 190 trace_amdgpu_ib_pipe_sync(job, tmp); 191 192 dma_fence_put(tmp); 193 } 194 195 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) 196 ring->funcs->emit_mem_sync(ring); 197 198 if (ring->funcs->emit_wave_limit && 199 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 200 ring->funcs->emit_wave_limit(ring, true); 201 202 if (ring->funcs->insert_start) 203 ring->funcs->insert_start(ring); 204 205 if (job) { 206 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 207 if (r) { 208 amdgpu_ring_undo(ring); 209 return r; 210 } 211 } 212 213 if (job && ring->funcs->init_cond_exec) 214 patch_offset = amdgpu_ring_init_cond_exec(ring); 215 216 #ifdef CONFIG_X86_64 217 if (!(adev->flags & AMD_IS_APU)) 218 #endif 219 { 220 if (ring->funcs->emit_hdp_flush) 221 amdgpu_ring_emit_hdp_flush(ring); 222 else 223 amdgpu_asic_flush_hdp(adev, ring); 224 } 225 226 if (need_ctx_switch) 227 status |= AMDGPU_HAVE_CTX_SWITCH; 228 229 skip_preamble = ring->current_ctx == fence_ctx; 230 if (job && ring->funcs->emit_cntxcntl) { 231 status |= job->preamble_status; 232 status |= job->preemption_status; 233 amdgpu_ring_emit_cntxcntl(ring, status); 234 } 235 236 /* Setup initial TMZiness and send it off. 237 */ 238 secure = false; 239 if (job && ring->funcs->emit_frame_cntl) { 240 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; 241 amdgpu_ring_emit_frame_cntl(ring, true, secure); 242 } 243 244 for (i = 0; i < num_ibs; ++i) { 245 ib = &ibs[i]; 246 247 /* drop preamble IBs if we don't have a context switch */ 248 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 249 skip_preamble && 250 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 251 !amdgpu_mcbp && 252 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 253 continue; 254 255 if (job && ring->funcs->emit_frame_cntl) { 256 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { 257 amdgpu_ring_emit_frame_cntl(ring, false, secure); 258 secure = !secure; 259 amdgpu_ring_emit_frame_cntl(ring, true, secure); 260 } 261 } 262 263 amdgpu_ring_emit_ib(ring, job, ib, status); 264 status &= ~AMDGPU_HAVE_CTX_SWITCH; 265 } 266 267 if (job && ring->funcs->emit_frame_cntl) 268 amdgpu_ring_emit_frame_cntl(ring, false, secure); 269 270 #ifdef CONFIG_X86_64 271 if (!(adev->flags & AMD_IS_APU)) 272 #endif 273 amdgpu_asic_invalidate_hdp(adev, ring); 274 275 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 276 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 277 278 /* wrap the last IB with fence */ 279 if (job && job->uf_addr) { 280 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 281 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 282 } 283 284 r = amdgpu_fence_emit(ring, f, fence_flags); 285 if (r) { 286 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 287 if (job && job->vmid) 288 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 289 amdgpu_ring_undo(ring); 290 return r; 291 } 292 293 if (ring->funcs->insert_end) 294 ring->funcs->insert_end(ring); 295 296 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 297 amdgpu_ring_patch_cond_exec(ring, patch_offset); 298 299 ring->current_ctx = fence_ctx; 300 if (vm && ring->funcs->emit_switch_buffer) 301 amdgpu_ring_emit_switch_buffer(ring); 302 303 if (ring->funcs->emit_wave_limit && 304 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 305 ring->funcs->emit_wave_limit(ring, false); 306 307 amdgpu_ring_commit(ring); 308 return 0; 309 } 310 311 /** 312 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 313 * 314 * @adev: amdgpu_device pointer 315 * 316 * Initialize the suballocator to manage a pool of memory 317 * for use as IBs (all asics). 318 * Returns 0 on success, error on failure. 319 */ 320 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 321 { 322 unsigned size; 323 int r, i; 324 325 if (adev->ib_pool_ready) 326 return 0; 327 328 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 329 if (i == AMDGPU_IB_POOL_DIRECT) 330 size = PAGE_SIZE * 2; 331 else 332 size = AMDGPU_IB_POOL_SIZE; 333 334 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], 335 size, AMDGPU_GPU_PAGE_SIZE, 336 AMDGPU_GEM_DOMAIN_GTT); 337 if (r) 338 goto error; 339 } 340 adev->ib_pool_ready = true; 341 342 return 0; 343 344 error: 345 while (i--) 346 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 347 return r; 348 } 349 350 /** 351 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 352 * 353 * @adev: amdgpu_device pointer 354 * 355 * Tear down the suballocator managing the pool of memory 356 * for use as IBs (all asics). 357 */ 358 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 359 { 360 int i; 361 362 if (!adev->ib_pool_ready) 363 return; 364 365 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 366 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 367 adev->ib_pool_ready = false; 368 } 369 370 /** 371 * amdgpu_ib_ring_tests - test IBs on the rings 372 * 373 * @adev: amdgpu_device pointer 374 * 375 * Test an IB (Indirect Buffer) on each ring. 376 * If the test fails, disable the ring. 377 * Returns 0 on success, error if the primary GFX ring 378 * IB test fails. 379 */ 380 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 381 { 382 long tmo_gfx, tmo_mm; 383 int r, ret = 0; 384 unsigned i; 385 386 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 387 if (amdgpu_sriov_vf(adev)) { 388 /* for MM engines in hypervisor side they are not scheduled together 389 * with CP and SDMA engines, so even in exclusive mode MM engine could 390 * still running on other VF thus the IB TEST TIMEOUT for MM engines 391 * under SR-IOV should be set to a long time. 8 sec should be enough 392 * for the MM comes back to this VF. 393 */ 394 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 395 } 396 397 if (amdgpu_sriov_runtime(adev)) { 398 /* for CP & SDMA engines since they are scheduled together so 399 * need to make the timeout width enough to cover the time 400 * cost waiting for it coming back under RUNTIME only 401 */ 402 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 403 } else if (adev->gmc.xgmi.hive_id) { 404 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 405 } 406 407 for (i = 0; i < adev->num_rings; ++i) { 408 struct amdgpu_ring *ring = adev->rings[i]; 409 long tmo; 410 411 /* KIQ rings don't have an IB test because we never submit IBs 412 * to them and they have no interrupt support. 413 */ 414 if (!ring->sched.ready || !ring->funcs->test_ib) 415 continue; 416 417 /* MM engine need more time */ 418 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 419 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 420 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 421 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 422 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 423 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 424 tmo = tmo_mm; 425 else 426 tmo = tmo_gfx; 427 428 r = amdgpu_ring_test_ib(ring, tmo); 429 if (!r) { 430 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 431 ring->name); 432 continue; 433 } 434 435 ring->sched.ready = false; 436 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 437 ring->name, r); 438 439 if (ring == &adev->gfx.gfx_ring[0]) { 440 /* oh, oh, that's really bad */ 441 adev->accel_working = false; 442 return r; 443 444 } else { 445 ret = r; 446 } 447 } 448 return ret; 449 } 450 451 /* 452 * Debugfs info 453 */ 454 #if defined(CONFIG_DEBUG_FS) 455 456 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 457 { 458 struct drm_info_node *node = (struct drm_info_node *) m->private; 459 struct drm_device *dev = node->minor->dev; 460 struct amdgpu_device *adev = drm_to_adev(dev); 461 462 seq_printf(m, "--------------------- DELAYED --------------------- \n"); 463 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], 464 m); 465 seq_printf(m, "-------------------- IMMEDIATE -------------------- \n"); 466 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE], 467 m); 468 seq_printf(m, "--------------------- DIRECT ---------------------- \n"); 469 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m); 470 471 return 0; 472 } 473 474 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 475 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 476 }; 477 478 #endif 479 480 int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 481 { 482 #if defined(CONFIG_DEBUG_FS) 483 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 484 ARRAY_SIZE(amdgpu_debugfs_sa_list)); 485 #else 486 return 0; 487 #endif 488 } 489