1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *          Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <drm/drmP.h>
32 #include <drm/amdgpu_drm.h>
33 #include "amdgpu.h"
34 #include "atom.h"
35 
36 #define AMDGPU_IB_TEST_TIMEOUT	msecs_to_jiffies(1000)
37 
38 /*
39  * IB
40  * IBs (Indirect Buffers) and areas of GPU accessible memory where
41  * commands are stored.  You can put a pointer to the IB in the
42  * command ring and the hw will fetch the commands from the IB
43  * and execute them.  Generally userspace acceleration drivers
44  * produce command buffers which are send to the kernel and
45  * put in IBs for execution by the requested ring.
46  */
47 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
48 
49 /**
50  * amdgpu_ib_get - request an IB (Indirect Buffer)
51  *
52  * @ring: ring index the IB is associated with
53  * @size: requested IB size
54  * @ib: IB object returned
55  *
56  * Request an IB (all asics).  IBs are allocated using the
57  * suballocator.
58  * Returns 0 on success, error on failure.
59  */
60 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
61 		  unsigned size, struct amdgpu_ib *ib)
62 {
63 	int r;
64 
65 	if (size) {
66 		r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
67 				      &ib->sa_bo, size, 256);
68 		if (r) {
69 			dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
70 			return r;
71 		}
72 
73 		ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
74 
75 		if (!vm)
76 			ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
77 	}
78 
79 	return 0;
80 }
81 
82 /**
83  * amdgpu_ib_free - free an IB (Indirect Buffer)
84  *
85  * @adev: amdgpu_device pointer
86  * @ib: IB object to free
87  * @f: the fence SA bo need wait on for the ib alloation
88  *
89  * Free an IB (all asics).
90  */
91 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
92 		    struct dma_fence *f)
93 {
94 	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
95 }
96 
97 /**
98  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
99  *
100  * @adev: amdgpu_device pointer
101  * @num_ibs: number of IBs to schedule
102  * @ibs: IB objects to schedule
103  * @f: fence created during this submission
104  *
105  * Schedule an IB on the associated ring (all asics).
106  * Returns 0 on success, error on failure.
107  *
108  * On SI, there are two parallel engines fed from the primary ring,
109  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
110  * resource descriptors have moved to memory, the CE allows you to
111  * prime the caches while the DE is updating register state so that
112  * the resource descriptors will be already in cache when the draw is
113  * processed.  To accomplish this, the userspace driver submits two
114  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
115  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
116  * to SI there was just a DE IB.
117  */
118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
119 		       struct amdgpu_ib *ibs, struct amdgpu_job *job,
120 		       struct dma_fence **f)
121 {
122 	struct amdgpu_device *adev = ring->adev;
123 	struct amdgpu_ib *ib = &ibs[0];
124 	struct dma_fence *tmp = NULL;
125 	bool skip_preamble, need_ctx_switch;
126 	unsigned patch_offset = ~0;
127 	struct amdgpu_vm *vm;
128 	uint64_t fence_ctx;
129 	uint32_t status = 0, alloc_size;
130 
131 	unsigned i;
132 	int r = 0;
133 	bool need_pipe_sync = false;
134 
135 	if (num_ibs == 0)
136 		return -EINVAL;
137 
138 	/* ring tests don't use a job */
139 	if (job) {
140 		vm = job->vm;
141 		fence_ctx = job->fence_ctx;
142 	} else {
143 		vm = NULL;
144 		fence_ctx = 0;
145 	}
146 
147 	if (!ring->ready) {
148 		dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
149 		return -EINVAL;
150 	}
151 
152 	if (vm && !job->vm_id) {
153 		dev_err(adev->dev, "VM IB without ID\n");
154 		return -EINVAL;
155 	}
156 
157 	alloc_size = ring->funcs->emit_frame_size + num_ibs *
158 		ring->funcs->emit_ib_size;
159 
160 	r = amdgpu_ring_alloc(ring, alloc_size);
161 	if (r) {
162 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
163 		return r;
164 	}
165 
166 	if (ring->funcs->emit_pipeline_sync && job &&
167 	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
168 	     amdgpu_vm_need_pipeline_sync(ring, job))) {
169 		need_pipe_sync = true;
170 		dma_fence_put(tmp);
171 	}
172 
173 	if (ring->funcs->insert_start)
174 		ring->funcs->insert_start(ring);
175 
176 	if (job) {
177 		r = amdgpu_vm_flush(ring, job, need_pipe_sync);
178 		if (r) {
179 			amdgpu_ring_undo(ring);
180 			return r;
181 		}
182 	}
183 
184 	if (ring->funcs->init_cond_exec)
185 		patch_offset = amdgpu_ring_init_cond_exec(ring);
186 
187 	if (ring->funcs->emit_hdp_flush
188 #ifdef CONFIG_X86_64
189 	    && !(adev->flags & AMD_IS_APU)
190 #endif
191 	   )
192 		amdgpu_ring_emit_hdp_flush(ring);
193 
194 	skip_preamble = ring->current_ctx == fence_ctx;
195 	need_ctx_switch = ring->current_ctx != fence_ctx;
196 	if (job && ring->funcs->emit_cntxcntl) {
197 		if (need_ctx_switch)
198 			status |= AMDGPU_HAVE_CTX_SWITCH;
199 		status |= job->preamble_status;
200 
201 		amdgpu_ring_emit_cntxcntl(ring, status);
202 	}
203 
204 	for (i = 0; i < num_ibs; ++i) {
205 		ib = &ibs[i];
206 
207 		/* drop preamble IBs if we don't have a context switch */
208 		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
209 			skip_preamble &&
210 			!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
211 			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
212 			continue;
213 
214 		amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
215 				    need_ctx_switch);
216 		need_ctx_switch = false;
217 	}
218 
219 	if (ring->funcs->emit_tmz)
220 		amdgpu_ring_emit_tmz(ring, false);
221 
222 	if (ring->funcs->emit_hdp_invalidate
223 #ifdef CONFIG_X86_64
224 	    && !(adev->flags & AMD_IS_APU)
225 #endif
226 	   )
227 		amdgpu_ring_emit_hdp_invalidate(ring);
228 
229 	r = amdgpu_fence_emit(ring, f);
230 	if (r) {
231 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
232 		if (job && job->vm_id)
233 			amdgpu_vm_reset_id(adev, ring->funcs->vmhub,
234 					   job->vm_id);
235 		amdgpu_ring_undo(ring);
236 		return r;
237 	}
238 
239 	if (ring->funcs->insert_end)
240 		ring->funcs->insert_end(ring);
241 
242 	/* wrap the last IB with fence */
243 	if (job && job->uf_addr) {
244 		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
245 				       AMDGPU_FENCE_FLAG_64BIT);
246 	}
247 
248 	if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
249 		amdgpu_ring_patch_cond_exec(ring, patch_offset);
250 
251 	ring->current_ctx = fence_ctx;
252 	if (vm && ring->funcs->emit_switch_buffer)
253 		amdgpu_ring_emit_switch_buffer(ring);
254 	amdgpu_ring_commit(ring);
255 	return 0;
256 }
257 
258 /**
259  * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
260  *
261  * @adev: amdgpu_device pointer
262  *
263  * Initialize the suballocator to manage a pool of memory
264  * for use as IBs (all asics).
265  * Returns 0 on success, error on failure.
266  */
267 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
268 {
269 	int r;
270 
271 	if (adev->ib_pool_ready) {
272 		return 0;
273 	}
274 	r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
275 				      AMDGPU_IB_POOL_SIZE*64*1024,
276 				      AMDGPU_GPU_PAGE_SIZE,
277 				      AMDGPU_GEM_DOMAIN_GTT);
278 	if (r) {
279 		return r;
280 	}
281 
282 	r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
283 	if (r) {
284 		return r;
285 	}
286 
287 	adev->ib_pool_ready = true;
288 	if (amdgpu_debugfs_sa_init(adev)) {
289 		dev_err(adev->dev, "failed to register debugfs file for SA\n");
290 	}
291 	return 0;
292 }
293 
294 /**
295  * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
296  *
297  * @adev: amdgpu_device pointer
298  *
299  * Tear down the suballocator managing the pool of memory
300  * for use as IBs (all asics).
301  */
302 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
303 {
304 	if (adev->ib_pool_ready) {
305 		amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
306 		amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
307 		adev->ib_pool_ready = false;
308 	}
309 }
310 
311 /**
312  * amdgpu_ib_ring_tests - test IBs on the rings
313  *
314  * @adev: amdgpu_device pointer
315  *
316  * Test an IB (Indirect Buffer) on each ring.
317  * If the test fails, disable the ring.
318  * Returns 0 on success, error if the primary GFX ring
319  * IB test fails.
320  */
321 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
322 {
323 	unsigned i;
324 	int r, ret = 0;
325 
326 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
327 		struct amdgpu_ring *ring = adev->rings[i];
328 
329 		if (!ring || !ring->ready)
330 			continue;
331 
332 		r = amdgpu_ring_test_ib(ring, AMDGPU_IB_TEST_TIMEOUT);
333 		if (r) {
334 			ring->ready = false;
335 
336 			if (ring == &adev->gfx.gfx_ring[0]) {
337 				/* oh, oh, that's really bad */
338 				DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
339 				adev->accel_working = false;
340 				return r;
341 
342 			} else {
343 				/* still not good, but we can live with it */
344 				DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
345 				ret = r;
346 			}
347 		}
348 	}
349 	return ret;
350 }
351 
352 /*
353  * Debugfs info
354  */
355 #if defined(CONFIG_DEBUG_FS)
356 
357 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
358 {
359 	struct drm_info_node *node = (struct drm_info_node *) m->private;
360 	struct drm_device *dev = node->minor->dev;
361 	struct amdgpu_device *adev = dev->dev_private;
362 
363 	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
364 
365 	return 0;
366 
367 }
368 
369 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
370 	{"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
371 };
372 
373 #endif
374 
375 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
376 {
377 #if defined(CONFIG_DEBUG_FS)
378 	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
379 #else
380 	return 0;
381 #endif
382 }
383