1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 36 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 37 38 /* 39 * IB 40 * IBs (Indirect Buffers) and areas of GPU accessible memory where 41 * commands are stored. You can put a pointer to the IB in the 42 * command ring and the hw will fetch the commands from the IB 43 * and execute them. Generally userspace acceleration drivers 44 * produce command buffers which are send to the kernel and 45 * put in IBs for execution by the requested ring. 46 */ 47 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 48 49 /** 50 * amdgpu_ib_get - request an IB (Indirect Buffer) 51 * 52 * @ring: ring index the IB is associated with 53 * @size: requested IB size 54 * @ib: IB object returned 55 * 56 * Request an IB (all asics). IBs are allocated using the 57 * suballocator. 58 * Returns 0 on success, error on failure. 59 */ 60 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 61 unsigned size, struct amdgpu_ib *ib) 62 { 63 int r; 64 65 if (size) { 66 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 67 &ib->sa_bo, size, 256); 68 if (r) { 69 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 70 return r; 71 } 72 73 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 74 75 if (!vm) 76 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 77 } 78 79 return 0; 80 } 81 82 /** 83 * amdgpu_ib_free - free an IB (Indirect Buffer) 84 * 85 * @adev: amdgpu_device pointer 86 * @ib: IB object to free 87 * @f: the fence SA bo need wait on for the ib alloation 88 * 89 * Free an IB (all asics). 90 */ 91 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 92 struct dma_fence *f) 93 { 94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95 } 96 97 /** 98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99 * 100 * @adev: amdgpu_device pointer 101 * @num_ibs: number of IBs to schedule 102 * @ibs: IB objects to schedule 103 * @f: fence created during this submission 104 * 105 * Schedule an IB on the associated ring (all asics). 106 * Returns 0 on success, error on failure. 107 * 108 * On SI, there are two parallel engines fed from the primary ring, 109 * the CE (Constant Engine) and the DE (Drawing Engine). Since 110 * resource descriptors have moved to memory, the CE allows you to 111 * prime the caches while the DE is updating register state so that 112 * the resource descriptors will be already in cache when the draw is 113 * processed. To accomplish this, the userspace driver submits two 114 * IBs, one for the CE and one for the DE. If there is a CE IB (called 115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116 * to SI there was just a DE IB. 117 */ 118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 119 struct amdgpu_ib *ibs, struct amdgpu_job *job, 120 struct dma_fence **f) 121 { 122 struct amdgpu_device *adev = ring->adev; 123 struct amdgpu_ib *ib = &ibs[0]; 124 struct dma_fence *tmp = NULL; 125 bool skip_preamble, need_ctx_switch; 126 unsigned patch_offset = ~0; 127 struct amdgpu_vm *vm; 128 uint64_t fence_ctx; 129 uint32_t status = 0, alloc_size; 130 unsigned fence_flags = 0; 131 132 unsigned i; 133 int r = 0; 134 bool need_pipe_sync = false; 135 136 if (num_ibs == 0) 137 return -EINVAL; 138 139 /* ring tests don't use a job */ 140 if (job) { 141 vm = job->vm; 142 fence_ctx = job->fence_ctx; 143 } else { 144 vm = NULL; 145 fence_ctx = 0; 146 } 147 148 if (!ring->ready) { 149 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 150 return -EINVAL; 151 } 152 153 if (vm && !job->vmid) { 154 dev_err(adev->dev, "VM IB without ID\n"); 155 return -EINVAL; 156 } 157 158 alloc_size = ring->funcs->emit_frame_size + num_ibs * 159 ring->funcs->emit_ib_size; 160 161 r = amdgpu_ring_alloc(ring, alloc_size); 162 if (r) { 163 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 164 return r; 165 } 166 167 if (ring->funcs->emit_pipeline_sync && job && 168 ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 169 amdgpu_vm_need_pipeline_sync(ring, job))) { 170 need_pipe_sync = true; 171 dma_fence_put(tmp); 172 } 173 174 if (ring->funcs->insert_start) 175 ring->funcs->insert_start(ring); 176 177 if (job) { 178 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 179 if (r) { 180 amdgpu_ring_undo(ring); 181 return r; 182 } 183 } 184 185 if (job && ring->funcs->init_cond_exec) 186 patch_offset = amdgpu_ring_init_cond_exec(ring); 187 188 #ifdef CONFIG_X86_64 189 if (!(adev->flags & AMD_IS_APU)) 190 #endif 191 { 192 if (ring->funcs->emit_hdp_flush) 193 amdgpu_ring_emit_hdp_flush(ring); 194 else 195 amdgpu_asic_flush_hdp(adev, ring); 196 } 197 198 skip_preamble = ring->current_ctx == fence_ctx; 199 need_ctx_switch = ring->current_ctx != fence_ctx; 200 if (job && ring->funcs->emit_cntxcntl) { 201 if (need_ctx_switch) 202 status |= AMDGPU_HAVE_CTX_SWITCH; 203 status |= job->preamble_status; 204 205 amdgpu_ring_emit_cntxcntl(ring, status); 206 } 207 208 for (i = 0; i < num_ibs; ++i) { 209 ib = &ibs[i]; 210 211 /* drop preamble IBs if we don't have a context switch */ 212 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 213 skip_preamble && 214 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 215 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 216 continue; 217 218 amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0, 219 need_ctx_switch); 220 need_ctx_switch = false; 221 } 222 223 if (ring->funcs->emit_tmz) 224 amdgpu_ring_emit_tmz(ring, false); 225 226 #ifdef CONFIG_X86_64 227 if (!(adev->flags & AMD_IS_APU)) 228 #endif 229 amdgpu_asic_invalidate_hdp(adev, ring); 230 231 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 232 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 233 234 /* wrap the last IB with fence */ 235 if (job && job->uf_addr) { 236 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 237 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 238 } 239 240 r = amdgpu_fence_emit(ring, f, fence_flags); 241 if (r) { 242 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 243 if (job && job->vmid) 244 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 245 amdgpu_ring_undo(ring); 246 return r; 247 } 248 249 if (ring->funcs->insert_end) 250 ring->funcs->insert_end(ring); 251 252 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 253 amdgpu_ring_patch_cond_exec(ring, patch_offset); 254 255 ring->current_ctx = fence_ctx; 256 if (vm && ring->funcs->emit_switch_buffer) 257 amdgpu_ring_emit_switch_buffer(ring); 258 amdgpu_ring_commit(ring); 259 return 0; 260 } 261 262 /** 263 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 264 * 265 * @adev: amdgpu_device pointer 266 * 267 * Initialize the suballocator to manage a pool of memory 268 * for use as IBs (all asics). 269 * Returns 0 on success, error on failure. 270 */ 271 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 272 { 273 int r; 274 275 if (adev->ib_pool_ready) { 276 return 0; 277 } 278 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 279 AMDGPU_IB_POOL_SIZE*64*1024, 280 AMDGPU_GPU_PAGE_SIZE, 281 AMDGPU_GEM_DOMAIN_GTT); 282 if (r) { 283 return r; 284 } 285 286 adev->ib_pool_ready = true; 287 if (amdgpu_debugfs_sa_init(adev)) { 288 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 289 } 290 return 0; 291 } 292 293 /** 294 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 295 * 296 * @adev: amdgpu_device pointer 297 * 298 * Tear down the suballocator managing the pool of memory 299 * for use as IBs (all asics). 300 */ 301 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 302 { 303 if (adev->ib_pool_ready) { 304 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 305 adev->ib_pool_ready = false; 306 } 307 } 308 309 /** 310 * amdgpu_ib_ring_tests - test IBs on the rings 311 * 312 * @adev: amdgpu_device pointer 313 * 314 * Test an IB (Indirect Buffer) on each ring. 315 * If the test fails, disable the ring. 316 * Returns 0 on success, error if the primary GFX ring 317 * IB test fails. 318 */ 319 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 320 { 321 unsigned i; 322 int r, ret = 0; 323 long tmo_gfx, tmo_mm; 324 325 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 326 if (amdgpu_sriov_vf(adev)) { 327 /* for MM engines in hypervisor side they are not scheduled together 328 * with CP and SDMA engines, so even in exclusive mode MM engine could 329 * still running on other VF thus the IB TEST TIMEOUT for MM engines 330 * under SR-IOV should be set to a long time. 8 sec should be enough 331 * for the MM comes back to this VF. 332 */ 333 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 334 } 335 336 if (amdgpu_sriov_runtime(adev)) { 337 /* for CP & SDMA engines since they are scheduled together so 338 * need to make the timeout width enough to cover the time 339 * cost waiting for it coming back under RUNTIME only 340 */ 341 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 342 } 343 344 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 345 struct amdgpu_ring *ring = adev->rings[i]; 346 long tmo; 347 348 if (!ring || !ring->ready) 349 continue; 350 351 /* MM engine need more time */ 352 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 353 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 354 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 355 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 356 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 357 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 358 tmo = tmo_mm; 359 else 360 tmo = tmo_gfx; 361 362 r = amdgpu_ring_test_ib(ring, tmo); 363 if (r) { 364 ring->ready = false; 365 366 if (ring == &adev->gfx.gfx_ring[0]) { 367 /* oh, oh, that's really bad */ 368 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 369 adev->accel_working = false; 370 return r; 371 372 } else { 373 /* still not good, but we can live with it */ 374 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 375 ret = r; 376 } 377 } 378 } 379 return ret; 380 } 381 382 /* 383 * Debugfs info 384 */ 385 #if defined(CONFIG_DEBUG_FS) 386 387 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 388 { 389 struct drm_info_node *node = (struct drm_info_node *) m->private; 390 struct drm_device *dev = node->minor->dev; 391 struct amdgpu_device *adev = dev->dev_private; 392 393 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 394 395 return 0; 396 397 } 398 399 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 400 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 401 }; 402 403 #endif 404 405 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 406 { 407 #if defined(CONFIG_DEBUG_FS) 408 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 409 #else 410 return 0; 411 #endif 412 } 413