1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_debugfs.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_trace.h" 38 39 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 40 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 41 42 /* 43 * IB 44 * IBs (Indirect Buffers) and areas of GPU accessible memory where 45 * commands are stored. You can put a pointer to the IB in the 46 * command ring and the hw will fetch the commands from the IB 47 * and execute them. Generally userspace acceleration drivers 48 * produce command buffers which are send to the kernel and 49 * put in IBs for execution by the requested ring. 50 */ 51 52 /** 53 * amdgpu_ib_get - request an IB (Indirect Buffer) 54 * 55 * @adev: amdgpu_device pointer 56 * @vm: amdgpu_vm pointer 57 * @size: requested IB size 58 * @pool_type: IB pool type (delayed, immediate, direct) 59 * @ib: IB object returned 60 * 61 * Request an IB (all asics). IBs are allocated using the 62 * suballocator. 63 * Returns 0 on success, error on failure. 64 */ 65 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 66 unsigned size, enum amdgpu_ib_pool_type pool_type, 67 struct amdgpu_ib *ib) 68 { 69 int r; 70 71 if (size) { 72 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], 73 &ib->sa_bo, size, 256); 74 if (r) { 75 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 76 return r; 77 } 78 79 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 80 81 if (!vm) 82 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 83 } 84 85 return 0; 86 } 87 88 /** 89 * amdgpu_ib_free - free an IB (Indirect Buffer) 90 * 91 * @adev: amdgpu_device pointer 92 * @ib: IB object to free 93 * @f: the fence SA bo need wait on for the ib alloation 94 * 95 * Free an IB (all asics). 96 */ 97 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 98 struct dma_fence *f) 99 { 100 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 101 } 102 103 /** 104 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 105 * 106 * @ring: ring index the IB is associated with 107 * @num_ibs: number of IBs to schedule 108 * @ibs: IB objects to schedule 109 * @job: job to schedule 110 * @f: fence created during this submission 111 * 112 * Schedule an IB on the associated ring (all asics). 113 * Returns 0 on success, error on failure. 114 * 115 * On SI, there are two parallel engines fed from the primary ring, 116 * the CE (Constant Engine) and the DE (Drawing Engine). Since 117 * resource descriptors have moved to memory, the CE allows you to 118 * prime the caches while the DE is updating register state so that 119 * the resource descriptors will be already in cache when the draw is 120 * processed. To accomplish this, the userspace driver submits two 121 * IBs, one for the CE and one for the DE. If there is a CE IB (called 122 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 123 * to SI there was just a DE IB. 124 */ 125 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 126 struct amdgpu_ib *ibs, struct amdgpu_job *job, 127 struct dma_fence **f) 128 { 129 struct amdgpu_device *adev = ring->adev; 130 struct amdgpu_ib *ib = &ibs[0]; 131 struct dma_fence *tmp = NULL; 132 bool skip_preamble, need_ctx_switch; 133 unsigned patch_offset = ~0; 134 struct amdgpu_vm *vm; 135 uint64_t fence_ctx; 136 uint32_t status = 0, alloc_size; 137 unsigned fence_flags = 0; 138 bool secure; 139 140 unsigned i; 141 int r = 0; 142 bool need_pipe_sync = false; 143 144 if (num_ibs == 0) 145 return -EINVAL; 146 147 /* ring tests don't use a job */ 148 if (job) { 149 vm = job->vm; 150 fence_ctx = job->base.s_fence ? 151 job->base.s_fence->scheduled.context : 0; 152 } else { 153 vm = NULL; 154 fence_ctx = 0; 155 } 156 157 if (!ring->sched.ready) { 158 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 159 return -EINVAL; 160 } 161 162 if (vm && !job->vmid) { 163 dev_err(adev->dev, "VM IB without ID\n"); 164 return -EINVAL; 165 } 166 167 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 168 (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) { 169 dev_err(adev->dev, "secure submissions not supported on compute rings\n"); 170 return -EINVAL; 171 } 172 173 alloc_size = ring->funcs->emit_frame_size + num_ibs * 174 ring->funcs->emit_ib_size; 175 176 r = amdgpu_ring_alloc(ring, alloc_size); 177 if (r) { 178 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 179 return r; 180 } 181 182 need_ctx_switch = ring->current_ctx != fence_ctx; 183 if (ring->funcs->emit_pipeline_sync && job && 184 ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) || 185 (amdgpu_sriov_vf(adev) && need_ctx_switch) || 186 amdgpu_vm_need_pipeline_sync(ring, job))) { 187 need_pipe_sync = true; 188 189 if (tmp) 190 trace_amdgpu_ib_pipe_sync(job, tmp); 191 192 dma_fence_put(tmp); 193 } 194 195 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) 196 ring->funcs->emit_mem_sync(ring); 197 198 if (ring->funcs->insert_start) 199 ring->funcs->insert_start(ring); 200 201 if (job) { 202 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 203 if (r) { 204 amdgpu_ring_undo(ring); 205 return r; 206 } 207 } 208 209 if (job && ring->funcs->init_cond_exec) 210 patch_offset = amdgpu_ring_init_cond_exec(ring); 211 212 #ifdef CONFIG_X86_64 213 if (!(adev->flags & AMD_IS_APU)) 214 #endif 215 { 216 if (ring->funcs->emit_hdp_flush) 217 amdgpu_ring_emit_hdp_flush(ring); 218 else 219 amdgpu_asic_flush_hdp(adev, ring); 220 } 221 222 if (need_ctx_switch) 223 status |= AMDGPU_HAVE_CTX_SWITCH; 224 225 skip_preamble = ring->current_ctx == fence_ctx; 226 if (job && ring->funcs->emit_cntxcntl) { 227 status |= job->preamble_status; 228 status |= job->preemption_status; 229 amdgpu_ring_emit_cntxcntl(ring, status); 230 } 231 232 /* Setup initial TMZiness and send it off. 233 */ 234 secure = false; 235 if (job && ring->funcs->emit_frame_cntl) { 236 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; 237 amdgpu_ring_emit_frame_cntl(ring, true, secure); 238 } 239 240 for (i = 0; i < num_ibs; ++i) { 241 ib = &ibs[i]; 242 243 /* drop preamble IBs if we don't have a context switch */ 244 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 245 skip_preamble && 246 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 247 !amdgpu_mcbp && 248 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 249 continue; 250 251 if (job && ring->funcs->emit_frame_cntl) { 252 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { 253 amdgpu_ring_emit_frame_cntl(ring, false, secure); 254 secure = !secure; 255 amdgpu_ring_emit_frame_cntl(ring, true, secure); 256 } 257 } 258 259 amdgpu_ring_emit_ib(ring, job, ib, status); 260 status &= ~AMDGPU_HAVE_CTX_SWITCH; 261 } 262 263 if (job && ring->funcs->emit_frame_cntl) 264 amdgpu_ring_emit_frame_cntl(ring, false, secure); 265 266 #ifdef CONFIG_X86_64 267 if (!(adev->flags & AMD_IS_APU)) 268 #endif 269 amdgpu_asic_invalidate_hdp(adev, ring); 270 271 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 272 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 273 274 /* wrap the last IB with fence */ 275 if (job && job->uf_addr) { 276 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 277 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 278 } 279 280 r = amdgpu_fence_emit(ring, f, fence_flags); 281 if (r) { 282 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 283 if (job && job->vmid) 284 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 285 amdgpu_ring_undo(ring); 286 return r; 287 } 288 289 if (ring->funcs->insert_end) 290 ring->funcs->insert_end(ring); 291 292 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 293 amdgpu_ring_patch_cond_exec(ring, patch_offset); 294 295 ring->current_ctx = fence_ctx; 296 if (vm && ring->funcs->emit_switch_buffer) 297 amdgpu_ring_emit_switch_buffer(ring); 298 amdgpu_ring_commit(ring); 299 return 0; 300 } 301 302 /** 303 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 304 * 305 * @adev: amdgpu_device pointer 306 * 307 * Initialize the suballocator to manage a pool of memory 308 * for use as IBs (all asics). 309 * Returns 0 on success, error on failure. 310 */ 311 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 312 { 313 unsigned size; 314 int r, i; 315 316 if (adev->ib_pool_ready) 317 return 0; 318 319 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 320 if (i == AMDGPU_IB_POOL_DIRECT) 321 size = PAGE_SIZE * 2; 322 else 323 size = AMDGPU_IB_POOL_SIZE; 324 325 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], 326 size, AMDGPU_GPU_PAGE_SIZE, 327 AMDGPU_GEM_DOMAIN_GTT); 328 if (r) 329 goto error; 330 } 331 adev->ib_pool_ready = true; 332 333 return 0; 334 335 error: 336 while (i--) 337 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 338 return r; 339 } 340 341 /** 342 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 343 * 344 * @adev: amdgpu_device pointer 345 * 346 * Tear down the suballocator managing the pool of memory 347 * for use as IBs (all asics). 348 */ 349 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 350 { 351 int i; 352 353 if (!adev->ib_pool_ready) 354 return; 355 356 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 357 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 358 adev->ib_pool_ready = false; 359 } 360 361 /** 362 * amdgpu_ib_ring_tests - test IBs on the rings 363 * 364 * @adev: amdgpu_device pointer 365 * 366 * Test an IB (Indirect Buffer) on each ring. 367 * If the test fails, disable the ring. 368 * Returns 0 on success, error if the primary GFX ring 369 * IB test fails. 370 */ 371 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 372 { 373 long tmo_gfx, tmo_mm; 374 int r, ret = 0; 375 unsigned i; 376 377 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 378 if (amdgpu_sriov_vf(adev)) { 379 /* for MM engines in hypervisor side they are not scheduled together 380 * with CP and SDMA engines, so even in exclusive mode MM engine could 381 * still running on other VF thus the IB TEST TIMEOUT for MM engines 382 * under SR-IOV should be set to a long time. 8 sec should be enough 383 * for the MM comes back to this VF. 384 */ 385 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 386 } 387 388 if (amdgpu_sriov_runtime(adev)) { 389 /* for CP & SDMA engines since they are scheduled together so 390 * need to make the timeout width enough to cover the time 391 * cost waiting for it coming back under RUNTIME only 392 */ 393 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 394 } else if (adev->gmc.xgmi.hive_id) { 395 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 396 } 397 398 for (i = 0; i < adev->num_rings; ++i) { 399 struct amdgpu_ring *ring = adev->rings[i]; 400 long tmo; 401 402 /* KIQ rings don't have an IB test because we never submit IBs 403 * to them and they have no interrupt support. 404 */ 405 if (!ring->sched.ready || !ring->funcs->test_ib) 406 continue; 407 408 /* MM engine need more time */ 409 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 410 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 411 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 412 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 413 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 414 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 415 tmo = tmo_mm; 416 else 417 tmo = tmo_gfx; 418 419 r = amdgpu_ring_test_ib(ring, tmo); 420 if (!r) { 421 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 422 ring->name); 423 continue; 424 } 425 426 ring->sched.ready = false; 427 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 428 ring->name, r); 429 430 if (ring == &adev->gfx.gfx_ring[0]) { 431 /* oh, oh, that's really bad */ 432 adev->accel_working = false; 433 return r; 434 435 } else { 436 ret = r; 437 } 438 } 439 return ret; 440 } 441 442 /* 443 * Debugfs info 444 */ 445 #if defined(CONFIG_DEBUG_FS) 446 447 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 448 { 449 struct drm_info_node *node = (struct drm_info_node *) m->private; 450 struct drm_device *dev = node->minor->dev; 451 struct amdgpu_device *adev = drm_to_adev(dev); 452 453 seq_printf(m, "--------------------- DELAYED --------------------- \n"); 454 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], 455 m); 456 seq_printf(m, "-------------------- IMMEDIATE -------------------- \n"); 457 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE], 458 m); 459 seq_printf(m, "--------------------- DIRECT ---------------------- \n"); 460 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m); 461 462 return 0; 463 } 464 465 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 466 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 467 }; 468 469 #endif 470 471 int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 472 { 473 #if defined(CONFIG_DEBUG_FS) 474 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 475 ARRAY_SIZE(amdgpu_debugfs_sa_list)); 476 #else 477 return 0; 478 #endif 479 } 480