1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 36 /* 37 * IB 38 * IBs (Indirect Buffers) and areas of GPU accessible memory where 39 * commands are stored. You can put a pointer to the IB in the 40 * command ring and the hw will fetch the commands from the IB 41 * and execute them. Generally userspace acceleration drivers 42 * produce command buffers which are send to the kernel and 43 * put in IBs for execution by the requested ring. 44 */ 45 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 46 47 /** 48 * amdgpu_ib_get - request an IB (Indirect Buffer) 49 * 50 * @ring: ring index the IB is associated with 51 * @size: requested IB size 52 * @ib: IB object returned 53 * 54 * Request an IB (all asics). IBs are allocated using the 55 * suballocator. 56 * Returns 0 on success, error on failure. 57 */ 58 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 59 unsigned size, struct amdgpu_ib *ib) 60 { 61 int r; 62 63 if (size) { 64 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 65 &ib->sa_bo, size, 256); 66 if (r) { 67 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 68 return r; 69 } 70 71 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 72 73 if (!vm) 74 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 75 } 76 77 ib->vm = vm; 78 79 return 0; 80 } 81 82 /** 83 * amdgpu_ib_free - free an IB (Indirect Buffer) 84 * 85 * @adev: amdgpu_device pointer 86 * @ib: IB object to free 87 * 88 * Free an IB (all asics). 89 */ 90 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) 91 { 92 amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base); 93 if (ib->fence) 94 fence_put(&ib->fence->base); 95 } 96 97 /** 98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99 * 100 * @adev: amdgpu_device pointer 101 * @num_ibs: number of IBs to schedule 102 * @ibs: IB objects to schedule 103 * @owner: owner for creating the fences 104 * @f: fence created during this submission 105 * 106 * Schedule an IB on the associated ring (all asics). 107 * Returns 0 on success, error on failure. 108 * 109 * On SI, there are two parallel engines fed from the primary ring, 110 * the CE (Constant Engine) and the DE (Drawing Engine). Since 111 * resource descriptors have moved to memory, the CE allows you to 112 * prime the caches while the DE is updating register state so that 113 * the resource descriptors will be already in cache when the draw is 114 * processed. To accomplish this, the userspace driver submits two 115 * IBs, one for the CE and one for the DE. If there is a CE IB (called 116 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 117 * to SI there was just a DE IB. 118 */ 119 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 120 struct amdgpu_ib *ibs, void *owner, 121 struct fence *last_vm_update, 122 struct fence **f) 123 { 124 struct amdgpu_device *adev = ring->adev; 125 struct amdgpu_ib *ib = &ibs[0]; 126 struct amdgpu_ctx *ctx, *old_ctx; 127 struct amdgpu_vm *vm; 128 unsigned i; 129 int r = 0; 130 131 if (num_ibs == 0) 132 return -EINVAL; 133 134 ctx = ibs->ctx; 135 vm = ibs->vm; 136 137 if (!ring->ready) { 138 dev_err(adev->dev, "couldn't schedule ib\n"); 139 return -EINVAL; 140 } 141 142 if (vm && !ibs->grabbed_vmid) { 143 dev_err(adev->dev, "VM IB without ID\n"); 144 return -EINVAL; 145 } 146 147 r = amdgpu_ring_alloc(ring, 256 * num_ibs); 148 if (r) { 149 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 150 return r; 151 } 152 153 if (vm) { 154 /* do context switch */ 155 amdgpu_vm_flush(ring, vm, last_vm_update); 156 157 if (ring->funcs->emit_gds_switch) 158 amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, 159 ib->gds_base, ib->gds_size, 160 ib->gws_base, ib->gws_size, 161 ib->oa_base, ib->oa_size); 162 163 if (ring->funcs->emit_hdp_flush) 164 amdgpu_ring_emit_hdp_flush(ring); 165 } 166 167 old_ctx = ring->current_ctx; 168 for (i = 0; i < num_ibs; ++i) { 169 ib = &ibs[i]; 170 171 if (ib->ctx != ctx || ib->vm != vm) { 172 ring->current_ctx = old_ctx; 173 amdgpu_ring_undo(ring); 174 return -EINVAL; 175 } 176 amdgpu_ring_emit_ib(ring, ib); 177 ring->current_ctx = ctx; 178 } 179 180 r = amdgpu_fence_emit(ring, owner, &ib->fence); 181 if (r) { 182 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 183 ring->current_ctx = old_ctx; 184 amdgpu_ring_undo(ring); 185 return r; 186 } 187 188 /* wrap the last IB with fence */ 189 if (ib->user) { 190 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 191 addr += ib->user->offset; 192 amdgpu_ring_emit_fence(ring, addr, ib->sequence, 193 AMDGPU_FENCE_FLAG_64BIT); 194 } 195 196 if (f) 197 *f = fence_get(&ib->fence->base); 198 199 amdgpu_ring_commit(ring); 200 return 0; 201 } 202 203 /** 204 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 205 * 206 * @adev: amdgpu_device pointer 207 * 208 * Initialize the suballocator to manage a pool of memory 209 * for use as IBs (all asics). 210 * Returns 0 on success, error on failure. 211 */ 212 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 213 { 214 int r; 215 216 if (adev->ib_pool_ready) { 217 return 0; 218 } 219 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 220 AMDGPU_IB_POOL_SIZE*64*1024, 221 AMDGPU_GPU_PAGE_SIZE, 222 AMDGPU_GEM_DOMAIN_GTT); 223 if (r) { 224 return r; 225 } 226 227 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 228 if (r) { 229 return r; 230 } 231 232 adev->ib_pool_ready = true; 233 if (amdgpu_debugfs_sa_init(adev)) { 234 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 235 } 236 return 0; 237 } 238 239 /** 240 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 241 * 242 * @adev: amdgpu_device pointer 243 * 244 * Tear down the suballocator managing the pool of memory 245 * for use as IBs (all asics). 246 */ 247 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 248 { 249 if (adev->ib_pool_ready) { 250 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 251 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 252 adev->ib_pool_ready = false; 253 } 254 } 255 256 /** 257 * amdgpu_ib_ring_tests - test IBs on the rings 258 * 259 * @adev: amdgpu_device pointer 260 * 261 * Test an IB (Indirect Buffer) on each ring. 262 * If the test fails, disable the ring. 263 * Returns 0 on success, error if the primary GFX ring 264 * IB test fails. 265 */ 266 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 267 { 268 unsigned i; 269 int r; 270 271 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 272 struct amdgpu_ring *ring = adev->rings[i]; 273 274 if (!ring || !ring->ready) 275 continue; 276 277 r = amdgpu_ring_test_ib(ring); 278 if (r) { 279 ring->ready = false; 280 281 if (ring == &adev->gfx.gfx_ring[0]) { 282 /* oh, oh, that's really bad */ 283 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 284 adev->accel_working = false; 285 return r; 286 287 } else { 288 /* still not good, but we can live with it */ 289 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 290 } 291 } 292 } 293 return 0; 294 } 295 296 /* 297 * Debugfs info 298 */ 299 #if defined(CONFIG_DEBUG_FS) 300 301 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 302 { 303 struct drm_info_node *node = (struct drm_info_node *) m->private; 304 struct drm_device *dev = node->minor->dev; 305 struct amdgpu_device *adev = dev->dev_private; 306 307 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 308 309 return 0; 310 311 } 312 313 static struct drm_info_list amdgpu_debugfs_sa_list[] = { 314 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 315 }; 316 317 #endif 318 319 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 320 { 321 #if defined(CONFIG_DEBUG_FS) 322 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 323 #else 324 return 0; 325 #endif 326 } 327