1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 34 #include "amdgpu.h" 35 #include "atom.h" 36 #include "amdgpu_trace.h" 37 38 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 39 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 40 41 /* 42 * IB 43 * IBs (Indirect Buffers) and areas of GPU accessible memory where 44 * commands are stored. You can put a pointer to the IB in the 45 * command ring and the hw will fetch the commands from the IB 46 * and execute them. Generally userspace acceleration drivers 47 * produce command buffers which are send to the kernel and 48 * put in IBs for execution by the requested ring. 49 */ 50 51 /** 52 * amdgpu_ib_get - request an IB (Indirect Buffer) 53 * 54 * @adev: amdgpu_device pointer 55 * @vm: amdgpu_vm pointer 56 * @size: requested IB size 57 * @pool_type: IB pool type (delayed, immediate, direct) 58 * @ib: IB object returned 59 * 60 * Request an IB (all asics). IBs are allocated using the 61 * suballocator. 62 * Returns 0 on success, error on failure. 63 */ 64 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 65 unsigned int size, enum amdgpu_ib_pool_type pool_type, 66 struct amdgpu_ib *ib) 67 { 68 int r; 69 70 if (size) { 71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], 72 &ib->sa_bo, size); 73 if (r) { 74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 75 return r; 76 } 77 78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 79 /* flush the cache before commit the IB */ 80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; 81 82 if (!vm) 83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 84 } 85 86 return 0; 87 } 88 89 /** 90 * amdgpu_ib_free - free an IB (Indirect Buffer) 91 * 92 * @adev: amdgpu_device pointer 93 * @ib: IB object to free 94 * @f: the fence SA bo need wait on for the ib alloation 95 * 96 * Free an IB (all asics). 97 */ 98 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 99 struct dma_fence *f) 100 { 101 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 102 } 103 104 /** 105 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 106 * 107 * @ring: ring index the IB is associated with 108 * @num_ibs: number of IBs to schedule 109 * @ibs: IB objects to schedule 110 * @job: job to schedule 111 * @f: fence created during this submission 112 * 113 * Schedule an IB on the associated ring (all asics). 114 * Returns 0 on success, error on failure. 115 * 116 * On SI, there are two parallel engines fed from the primary ring, 117 * the CE (Constant Engine) and the DE (Drawing Engine). Since 118 * resource descriptors have moved to memory, the CE allows you to 119 * prime the caches while the DE is updating register state so that 120 * the resource descriptors will be already in cache when the draw is 121 * processed. To accomplish this, the userspace driver submits two 122 * IBs, one for the CE and one for the DE. If there is a CE IB (called 123 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 124 * to SI there was just a DE IB. 125 */ 126 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 127 struct amdgpu_ib *ibs, struct amdgpu_job *job, 128 struct dma_fence **f) 129 { 130 struct amdgpu_device *adev = ring->adev; 131 struct amdgpu_ib *ib = &ibs[0]; 132 struct dma_fence *tmp = NULL; 133 bool need_ctx_switch; 134 unsigned int patch_offset = ~0; 135 struct amdgpu_vm *vm; 136 uint64_t fence_ctx; 137 uint32_t status = 0, alloc_size; 138 unsigned int fence_flags = 0; 139 bool secure, init_shadow; 140 u64 shadow_va, csa_va, gds_va; 141 int vmid = AMDGPU_JOB_GET_VMID(job); 142 143 unsigned int i; 144 int r = 0; 145 bool need_pipe_sync = false; 146 147 if (num_ibs == 0) 148 return -EINVAL; 149 150 /* ring tests don't use a job */ 151 if (job) { 152 vm = job->vm; 153 fence_ctx = job->base.s_fence ? 154 job->base.s_fence->scheduled.context : 0; 155 shadow_va = job->shadow_va; 156 csa_va = job->csa_va; 157 gds_va = job->gds_va; 158 init_shadow = job->init_shadow; 159 } else { 160 vm = NULL; 161 fence_ctx = 0; 162 shadow_va = 0; 163 csa_va = 0; 164 gds_va = 0; 165 init_shadow = false; 166 } 167 168 if (!ring->sched.ready && !ring->is_mes_queue) { 169 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 170 return -EINVAL; 171 } 172 173 if (vm && !job->vmid && !ring->is_mes_queue) { 174 dev_err(adev->dev, "VM IB without ID\n"); 175 return -EINVAL; 176 } 177 178 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 179 (!ring->funcs->secure_submission_supported)) { 180 dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name); 181 return -EINVAL; 182 } 183 184 alloc_size = ring->funcs->emit_frame_size + num_ibs * 185 ring->funcs->emit_ib_size; 186 187 r = amdgpu_ring_alloc(ring, alloc_size); 188 if (r) { 189 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 190 return r; 191 } 192 193 need_ctx_switch = ring->current_ctx != fence_ctx; 194 if (ring->funcs->emit_pipeline_sync && job && 195 ((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) || 196 (amdgpu_sriov_vf(adev) && need_ctx_switch) || 197 amdgpu_vm_need_pipeline_sync(ring, job))) { 198 need_pipe_sync = true; 199 200 if (tmp) 201 trace_amdgpu_ib_pipe_sync(job, tmp); 202 203 dma_fence_put(tmp); 204 } 205 206 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) 207 ring->funcs->emit_mem_sync(ring); 208 209 if (ring->funcs->emit_wave_limit && 210 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 211 ring->funcs->emit_wave_limit(ring, true); 212 213 if (ring->funcs->insert_start) 214 ring->funcs->insert_start(ring); 215 216 if (job) { 217 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 218 if (r) { 219 amdgpu_ring_undo(ring); 220 return r; 221 } 222 } 223 224 amdgpu_ring_ib_begin(ring); 225 226 if (ring->funcs->emit_gfx_shadow) 227 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, 228 init_shadow, vmid); 229 230 if (ring->funcs->init_cond_exec) 231 patch_offset = amdgpu_ring_init_cond_exec(ring); 232 233 amdgpu_device_flush_hdp(adev, ring); 234 235 if (need_ctx_switch) 236 status |= AMDGPU_HAVE_CTX_SWITCH; 237 238 if (job && ring->funcs->emit_cntxcntl) { 239 status |= job->preamble_status; 240 status |= job->preemption_status; 241 amdgpu_ring_emit_cntxcntl(ring, status); 242 } 243 244 /* Setup initial TMZiness and send it off. 245 */ 246 secure = false; 247 if (job && ring->funcs->emit_frame_cntl) { 248 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; 249 amdgpu_ring_emit_frame_cntl(ring, true, secure); 250 } 251 252 for (i = 0; i < num_ibs; ++i) { 253 ib = &ibs[i]; 254 255 if (job && ring->funcs->emit_frame_cntl) { 256 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { 257 amdgpu_ring_emit_frame_cntl(ring, false, secure); 258 secure = !secure; 259 amdgpu_ring_emit_frame_cntl(ring, true, secure); 260 } 261 } 262 263 amdgpu_ring_emit_ib(ring, job, ib, status); 264 status &= ~AMDGPU_HAVE_CTX_SWITCH; 265 } 266 267 if (job && ring->funcs->emit_frame_cntl) 268 amdgpu_ring_emit_frame_cntl(ring, false, secure); 269 270 amdgpu_device_invalidate_hdp(adev, ring); 271 272 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 273 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 274 275 /* wrap the last IB with fence */ 276 if (job && job->uf_addr) { 277 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 278 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 279 } 280 281 if (ring->funcs->emit_gfx_shadow) { 282 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0); 283 284 if (ring->funcs->init_cond_exec) { 285 unsigned int ce_offset = ~0; 286 287 ce_offset = amdgpu_ring_init_cond_exec(ring); 288 if (ce_offset != ~0 && ring->funcs->patch_cond_exec) 289 amdgpu_ring_patch_cond_exec(ring, ce_offset); 290 } 291 } 292 293 r = amdgpu_fence_emit(ring, f, job, fence_flags); 294 if (r) { 295 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 296 if (job && job->vmid) 297 amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid); 298 amdgpu_ring_undo(ring); 299 return r; 300 } 301 302 if (ring->funcs->insert_end) 303 ring->funcs->insert_end(ring); 304 305 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 306 amdgpu_ring_patch_cond_exec(ring, patch_offset); 307 308 ring->current_ctx = fence_ctx; 309 if (vm && ring->funcs->emit_switch_buffer) 310 amdgpu_ring_emit_switch_buffer(ring); 311 312 if (ring->funcs->emit_wave_limit && 313 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) 314 ring->funcs->emit_wave_limit(ring, false); 315 316 amdgpu_ring_ib_end(ring); 317 amdgpu_ring_commit(ring); 318 return 0; 319 } 320 321 /** 322 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 323 * 324 * @adev: amdgpu_device pointer 325 * 326 * Initialize the suballocator to manage a pool of memory 327 * for use as IBs (all asics). 328 * Returns 0 on success, error on failure. 329 */ 330 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 331 { 332 int r, i; 333 334 if (adev->ib_pool_ready) 335 return 0; 336 337 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 338 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], 339 AMDGPU_IB_POOL_SIZE, 256, 340 AMDGPU_GEM_DOMAIN_GTT); 341 if (r) 342 goto error; 343 } 344 adev->ib_pool_ready = true; 345 346 return 0; 347 348 error: 349 while (i--) 350 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 351 return r; 352 } 353 354 /** 355 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 356 * 357 * @adev: amdgpu_device pointer 358 * 359 * Tear down the suballocator managing the pool of memory 360 * for use as IBs (all asics). 361 */ 362 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 363 { 364 int i; 365 366 if (!adev->ib_pool_ready) 367 return; 368 369 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 370 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 371 adev->ib_pool_ready = false; 372 } 373 374 /** 375 * amdgpu_ib_ring_tests - test IBs on the rings 376 * 377 * @adev: amdgpu_device pointer 378 * 379 * Test an IB (Indirect Buffer) on each ring. 380 * If the test fails, disable the ring. 381 * Returns 0 on success, error if the primary GFX ring 382 * IB test fails. 383 */ 384 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 385 { 386 long tmo_gfx, tmo_mm; 387 int r, ret = 0; 388 unsigned int i; 389 390 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 391 if (amdgpu_sriov_vf(adev)) { 392 /* for MM engines in hypervisor side they are not scheduled together 393 * with CP and SDMA engines, so even in exclusive mode MM engine could 394 * still running on other VF thus the IB TEST TIMEOUT for MM engines 395 * under SR-IOV should be set to a long time. 8 sec should be enough 396 * for the MM comes back to this VF. 397 */ 398 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 399 } 400 401 if (amdgpu_sriov_runtime(adev)) { 402 /* for CP & SDMA engines since they are scheduled together so 403 * need to make the timeout width enough to cover the time 404 * cost waiting for it coming back under RUNTIME only 405 */ 406 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 407 } else if (adev->gmc.xgmi.hive_id) { 408 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 409 } 410 411 for (i = 0; i < adev->num_rings; ++i) { 412 struct amdgpu_ring *ring = adev->rings[i]; 413 long tmo; 414 415 /* KIQ rings don't have an IB test because we never submit IBs 416 * to them and they have no interrupt support. 417 */ 418 if (!ring->sched.ready || !ring->funcs->test_ib) 419 continue; 420 421 if (adev->enable_mes && 422 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 423 continue; 424 425 /* MM engine need more time */ 426 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 427 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 428 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 429 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 430 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 431 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 432 tmo = tmo_mm; 433 else 434 tmo = tmo_gfx; 435 436 r = amdgpu_ring_test_ib(ring, tmo); 437 if (!r) { 438 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 439 ring->name); 440 continue; 441 } 442 443 ring->sched.ready = false; 444 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 445 ring->name, r); 446 447 if (ring == &adev->gfx.gfx_ring[0]) { 448 /* oh, oh, that's really bad */ 449 adev->accel_working = false; 450 return r; 451 452 } else { 453 ret = r; 454 } 455 } 456 return ret; 457 } 458 459 /* 460 * Debugfs info 461 */ 462 #if defined(CONFIG_DEBUG_FS) 463 464 static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused) 465 { 466 struct amdgpu_device *adev = m->private; 467 468 seq_puts(m, "--------------------- DELAYED ---------------------\n"); 469 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], 470 m); 471 seq_puts(m, "-------------------- IMMEDIATE --------------------\n"); 472 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE], 473 m); 474 seq_puts(m, "--------------------- DIRECT ----------------------\n"); 475 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m); 476 477 return 0; 478 } 479 480 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info); 481 482 #endif 483 484 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 485 { 486 #if defined(CONFIG_DEBUG_FS) 487 struct drm_minor *minor = adev_to_drm(adev)->primary; 488 struct dentry *root = minor->debugfs_root; 489 490 debugfs_create_file("amdgpu_sa_info", 0444, root, adev, 491 &amdgpu_debugfs_sa_info_fops); 492 493 #endif 494 } 495