1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_debugfs.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_trace.h" 38 39 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 40 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 41 42 /* 43 * IB 44 * IBs (Indirect Buffers) and areas of GPU accessible memory where 45 * commands are stored. You can put a pointer to the IB in the 46 * command ring and the hw will fetch the commands from the IB 47 * and execute them. Generally userspace acceleration drivers 48 * produce command buffers which are send to the kernel and 49 * put in IBs for execution by the requested ring. 50 */ 51 52 /** 53 * amdgpu_ib_get - request an IB (Indirect Buffer) 54 * 55 * @ring: ring index the IB is associated with 56 * @size: requested IB size 57 * @ib: IB object returned 58 * 59 * Request an IB (all asics). IBs are allocated using the 60 * suballocator. 61 * Returns 0 on success, error on failure. 62 */ 63 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 64 unsigned size, 65 enum amdgpu_ib_pool_type pool_type, 66 struct amdgpu_ib *ib) 67 { 68 int r; 69 70 if (size) { 71 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo[pool_type], 72 &ib->sa_bo, size, 256); 73 if (r) { 74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 75 return r; 76 } 77 78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 79 80 if (!vm) 81 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 82 } 83 84 return 0; 85 } 86 87 /** 88 * amdgpu_ib_free - free an IB (Indirect Buffer) 89 * 90 * @adev: amdgpu_device pointer 91 * @ib: IB object to free 92 * @f: the fence SA bo need wait on for the ib alloation 93 * 94 * Free an IB (all asics). 95 */ 96 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 97 struct dma_fence *f) 98 { 99 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 100 } 101 102 /** 103 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 104 * 105 * @adev: amdgpu_device pointer 106 * @num_ibs: number of IBs to schedule 107 * @ibs: IB objects to schedule 108 * @f: fence created during this submission 109 * 110 * Schedule an IB on the associated ring (all asics). 111 * Returns 0 on success, error on failure. 112 * 113 * On SI, there are two parallel engines fed from the primary ring, 114 * the CE (Constant Engine) and the DE (Drawing Engine). Since 115 * resource descriptors have moved to memory, the CE allows you to 116 * prime the caches while the DE is updating register state so that 117 * the resource descriptors will be already in cache when the draw is 118 * processed. To accomplish this, the userspace driver submits two 119 * IBs, one for the CE and one for the DE. If there is a CE IB (called 120 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 121 * to SI there was just a DE IB. 122 */ 123 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 124 struct amdgpu_ib *ibs, struct amdgpu_job *job, 125 struct dma_fence **f) 126 { 127 struct amdgpu_device *adev = ring->adev; 128 struct amdgpu_ib *ib = &ibs[0]; 129 struct dma_fence *tmp = NULL; 130 bool skip_preamble, need_ctx_switch; 131 unsigned patch_offset = ~0; 132 struct amdgpu_vm *vm; 133 uint64_t fence_ctx; 134 uint32_t status = 0, alloc_size; 135 unsigned fence_flags = 0; 136 137 unsigned i; 138 int r = 0; 139 bool need_pipe_sync = false; 140 141 if (num_ibs == 0) 142 return -EINVAL; 143 144 /* ring tests don't use a job */ 145 if (job) { 146 vm = job->vm; 147 fence_ctx = job->base.s_fence ? 148 job->base.s_fence->scheduled.context : 0; 149 } else { 150 vm = NULL; 151 fence_ctx = 0; 152 } 153 154 if (!ring->sched.ready) { 155 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 156 return -EINVAL; 157 } 158 159 if (vm && !job->vmid) { 160 dev_err(adev->dev, "VM IB without ID\n"); 161 return -EINVAL; 162 } 163 164 alloc_size = ring->funcs->emit_frame_size + num_ibs * 165 ring->funcs->emit_ib_size; 166 167 r = amdgpu_ring_alloc(ring, alloc_size); 168 if (r) { 169 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 170 return r; 171 } 172 173 need_ctx_switch = ring->current_ctx != fence_ctx; 174 if (ring->funcs->emit_pipeline_sync && job && 175 ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 176 (amdgpu_sriov_vf(adev) && need_ctx_switch) || 177 amdgpu_vm_need_pipeline_sync(ring, job))) { 178 need_pipe_sync = true; 179 180 if (tmp) 181 trace_amdgpu_ib_pipe_sync(job, tmp); 182 183 dma_fence_put(tmp); 184 } 185 186 if (ring->funcs->insert_start) 187 ring->funcs->insert_start(ring); 188 189 if (job) { 190 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 191 if (r) { 192 amdgpu_ring_undo(ring); 193 return r; 194 } 195 } 196 197 if (job && ring->funcs->init_cond_exec) 198 patch_offset = amdgpu_ring_init_cond_exec(ring); 199 200 #ifdef CONFIG_X86_64 201 if (!(adev->flags & AMD_IS_APU)) 202 #endif 203 { 204 if (ring->funcs->emit_hdp_flush) 205 amdgpu_ring_emit_hdp_flush(ring); 206 else 207 amdgpu_asic_flush_hdp(adev, ring); 208 } 209 210 if (need_ctx_switch) 211 status |= AMDGPU_HAVE_CTX_SWITCH; 212 213 skip_preamble = ring->current_ctx == fence_ctx; 214 if (job && ring->funcs->emit_cntxcntl) { 215 status |= job->preamble_status; 216 status |= job->preemption_status; 217 amdgpu_ring_emit_cntxcntl(ring, status); 218 } 219 220 for (i = 0; i < num_ibs; ++i) { 221 ib = &ibs[i]; 222 223 /* drop preamble IBs if we don't have a context switch */ 224 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 225 skip_preamble && 226 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 227 !amdgpu_mcbp && 228 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 229 continue; 230 231 amdgpu_ring_emit_ib(ring, job, ib, status); 232 status &= ~AMDGPU_HAVE_CTX_SWITCH; 233 } 234 235 if (ring->funcs->emit_tmz) 236 amdgpu_ring_emit_tmz(ring, false); 237 238 #ifdef CONFIG_X86_64 239 if (!(adev->flags & AMD_IS_APU)) 240 #endif 241 amdgpu_asic_invalidate_hdp(adev, ring); 242 243 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 244 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 245 246 /* wrap the last IB with fence */ 247 if (job && job->uf_addr) { 248 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 249 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 250 } 251 252 r = amdgpu_fence_emit(ring, f, fence_flags); 253 if (r) { 254 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 255 if (job && job->vmid) 256 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 257 amdgpu_ring_undo(ring); 258 return r; 259 } 260 261 if (ring->funcs->insert_end) 262 ring->funcs->insert_end(ring); 263 264 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 265 amdgpu_ring_patch_cond_exec(ring, patch_offset); 266 267 ring->current_ctx = fence_ctx; 268 if (vm && ring->funcs->emit_switch_buffer) 269 amdgpu_ring_emit_switch_buffer(ring); 270 amdgpu_ring_commit(ring); 271 return 0; 272 } 273 274 /** 275 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 276 * 277 * @adev: amdgpu_device pointer 278 * 279 * Initialize the suballocator to manage a pool of memory 280 * for use as IBs (all asics). 281 * Returns 0 on success, error on failure. 282 */ 283 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 284 { 285 int r, i; 286 unsigned size; 287 288 if (adev->ib_pool_ready) { 289 return 0; 290 } 291 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 292 if (i == AMDGPU_IB_POOL_DIRECT) 293 size = PAGE_SIZE * 2; 294 else 295 size = AMDGPU_IB_POOL_SIZE*64*1024; 296 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo[i], 297 size, 298 AMDGPU_GPU_PAGE_SIZE, 299 AMDGPU_GEM_DOMAIN_GTT); 300 if (r) { 301 for (i--; i >= 0; i--) 302 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo[i]); 303 return r; 304 } 305 } 306 adev->ib_pool_ready = true; 307 308 return 0; 309 } 310 311 /** 312 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 313 * 314 * @adev: amdgpu_device pointer 315 * 316 * Tear down the suballocator managing the pool of memory 317 * for use as IBs (all asics). 318 */ 319 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 320 { 321 int i; 322 323 if (adev->ib_pool_ready) { 324 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 325 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo[i]); 326 adev->ib_pool_ready = false; 327 } 328 } 329 330 /** 331 * amdgpu_ib_ring_tests - test IBs on the rings 332 * 333 * @adev: amdgpu_device pointer 334 * 335 * Test an IB (Indirect Buffer) on each ring. 336 * If the test fails, disable the ring. 337 * Returns 0 on success, error if the primary GFX ring 338 * IB test fails. 339 */ 340 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 341 { 342 unsigned i; 343 int r, ret = 0; 344 long tmo_gfx, tmo_mm; 345 346 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 347 if (amdgpu_sriov_vf(adev)) { 348 /* for MM engines in hypervisor side they are not scheduled together 349 * with CP and SDMA engines, so even in exclusive mode MM engine could 350 * still running on other VF thus the IB TEST TIMEOUT for MM engines 351 * under SR-IOV should be set to a long time. 8 sec should be enough 352 * for the MM comes back to this VF. 353 */ 354 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 355 } 356 357 if (amdgpu_sriov_runtime(adev)) { 358 /* for CP & SDMA engines since they are scheduled together so 359 * need to make the timeout width enough to cover the time 360 * cost waiting for it coming back under RUNTIME only 361 */ 362 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 363 } else if (adev->gmc.xgmi.hive_id) { 364 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 365 } 366 367 for (i = 0; i < adev->num_rings; ++i) { 368 struct amdgpu_ring *ring = adev->rings[i]; 369 long tmo; 370 371 /* KIQ rings don't have an IB test because we never submit IBs 372 * to them and they have no interrupt support. 373 */ 374 if (!ring->sched.ready || !ring->funcs->test_ib) 375 continue; 376 377 /* MM engine need more time */ 378 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 379 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 380 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 381 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 382 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 383 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 384 tmo = tmo_mm; 385 else 386 tmo = tmo_gfx; 387 388 r = amdgpu_ring_test_ib(ring, tmo); 389 if (!r) { 390 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 391 ring->name); 392 continue; 393 } 394 395 ring->sched.ready = false; 396 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 397 ring->name, r); 398 399 if (ring == &adev->gfx.gfx_ring[0]) { 400 /* oh, oh, that's really bad */ 401 adev->accel_working = false; 402 return r; 403 404 } else { 405 ret = r; 406 } 407 } 408 return ret; 409 } 410 411 /* 412 * Debugfs info 413 */ 414 #if defined(CONFIG_DEBUG_FS) 415 416 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 417 { 418 struct drm_info_node *node = (struct drm_info_node *) m->private; 419 struct drm_device *dev = node->minor->dev; 420 struct amdgpu_device *adev = dev->dev_private; 421 422 seq_printf(m, "-------------------- NORMAL -------------------- \n"); 423 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo[AMDGPU_IB_POOL_NORMAL], m); 424 seq_printf(m, "---------------------- VM ---------------------- \n"); 425 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo[AMDGPU_IB_POOL_VM], m); 426 seq_printf(m, "-------------------- DIRECT--------------------- \n"); 427 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo[AMDGPU_IB_POOL_DIRECT], m); 428 429 return 0; 430 431 } 432 433 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 434 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 435 }; 436 437 #endif 438 439 int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 440 { 441 #if defined(CONFIG_DEBUG_FS) 442 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 443 #else 444 return 0; 445 #endif 446 } 447