1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_debugfs.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_trace.h" 38 39 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 40 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 41 42 /* 43 * IB 44 * IBs (Indirect Buffers) and areas of GPU accessible memory where 45 * commands are stored. You can put a pointer to the IB in the 46 * command ring and the hw will fetch the commands from the IB 47 * and execute them. Generally userspace acceleration drivers 48 * produce command buffers which are send to the kernel and 49 * put in IBs for execution by the requested ring. 50 */ 51 52 /** 53 * amdgpu_ib_get - request an IB (Indirect Buffer) 54 * 55 * @adev: amdgpu_device pointer 56 * @vm: amdgpu_vm pointer 57 * @size: requested IB size 58 * @pool_type: IB pool type (delayed, immediate, direct) 59 * @ib: IB object returned 60 * 61 * Request an IB (all asics). IBs are allocated using the 62 * suballocator. 63 * Returns 0 on success, error on failure. 64 */ 65 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 66 unsigned size, enum amdgpu_ib_pool_type pool_type, 67 struct amdgpu_ib *ib) 68 { 69 int r; 70 71 if (size) { 72 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], 73 &ib->sa_bo, size, 256); 74 if (r) { 75 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 76 return r; 77 } 78 79 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 80 81 if (!vm) 82 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 83 } 84 85 return 0; 86 } 87 88 /** 89 * amdgpu_ib_free - free an IB (Indirect Buffer) 90 * 91 * @adev: amdgpu_device pointer 92 * @ib: IB object to free 93 * @f: the fence SA bo need wait on for the ib alloation 94 * 95 * Free an IB (all asics). 96 */ 97 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 98 struct dma_fence *f) 99 { 100 amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 101 } 102 103 /** 104 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 105 * 106 * @ring: ring index the IB is associated with 107 * @num_ibs: number of IBs to schedule 108 * @ibs: IB objects to schedule 109 * @f: fence created during this submission 110 * 111 * Schedule an IB on the associated ring (all asics). 112 * Returns 0 on success, error on failure. 113 * 114 * On SI, there are two parallel engines fed from the primary ring, 115 * the CE (Constant Engine) and the DE (Drawing Engine). Since 116 * resource descriptors have moved to memory, the CE allows you to 117 * prime the caches while the DE is updating register state so that 118 * the resource descriptors will be already in cache when the draw is 119 * processed. To accomplish this, the userspace driver submits two 120 * IBs, one for the CE and one for the DE. If there is a CE IB (called 121 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 122 * to SI there was just a DE IB. 123 */ 124 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 125 struct amdgpu_ib *ibs, struct amdgpu_job *job, 126 struct dma_fence **f) 127 { 128 struct amdgpu_device *adev = ring->adev; 129 struct amdgpu_ib *ib = &ibs[0]; 130 struct dma_fence *tmp = NULL; 131 bool skip_preamble, need_ctx_switch; 132 unsigned patch_offset = ~0; 133 struct amdgpu_vm *vm; 134 uint64_t fence_ctx; 135 uint32_t status = 0, alloc_size; 136 unsigned fence_flags = 0; 137 bool secure; 138 139 unsigned i; 140 int r = 0; 141 bool need_pipe_sync = false; 142 143 if (num_ibs == 0) 144 return -EINVAL; 145 146 /* ring tests don't use a job */ 147 if (job) { 148 vm = job->vm; 149 fence_ctx = job->base.s_fence ? 150 job->base.s_fence->scheduled.context : 0; 151 } else { 152 vm = NULL; 153 fence_ctx = 0; 154 } 155 156 if (!ring->sched.ready) { 157 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 158 return -EINVAL; 159 } 160 161 if (vm && !job->vmid) { 162 dev_err(adev->dev, "VM IB without ID\n"); 163 return -EINVAL; 164 } 165 166 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 167 (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) { 168 dev_err(adev->dev, "secure submissions not supported on compute rings\n"); 169 return -EINVAL; 170 } 171 172 alloc_size = ring->funcs->emit_frame_size + num_ibs * 173 ring->funcs->emit_ib_size; 174 175 r = amdgpu_ring_alloc(ring, alloc_size); 176 if (r) { 177 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 178 return r; 179 } 180 181 need_ctx_switch = ring->current_ctx != fence_ctx; 182 if (ring->funcs->emit_pipeline_sync && job && 183 ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) || 184 (amdgpu_sriov_vf(adev) && need_ctx_switch) || 185 amdgpu_vm_need_pipeline_sync(ring, job))) { 186 need_pipe_sync = true; 187 188 if (tmp) 189 trace_amdgpu_ib_pipe_sync(job, tmp); 190 191 dma_fence_put(tmp); 192 } 193 194 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) 195 ring->funcs->emit_mem_sync(ring); 196 197 if (ring->funcs->insert_start) 198 ring->funcs->insert_start(ring); 199 200 if (job) { 201 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 202 if (r) { 203 amdgpu_ring_undo(ring); 204 return r; 205 } 206 } 207 208 if (job && ring->funcs->init_cond_exec) 209 patch_offset = amdgpu_ring_init_cond_exec(ring); 210 211 #ifdef CONFIG_X86_64 212 if (!(adev->flags & AMD_IS_APU)) 213 #endif 214 { 215 if (ring->funcs->emit_hdp_flush) 216 amdgpu_ring_emit_hdp_flush(ring); 217 else 218 amdgpu_asic_flush_hdp(adev, ring); 219 } 220 221 if (need_ctx_switch) 222 status |= AMDGPU_HAVE_CTX_SWITCH; 223 224 skip_preamble = ring->current_ctx == fence_ctx; 225 if (job && ring->funcs->emit_cntxcntl) { 226 status |= job->preamble_status; 227 status |= job->preemption_status; 228 amdgpu_ring_emit_cntxcntl(ring, status); 229 } 230 231 /* Setup initial TMZiness and send it off. 232 */ 233 secure = false; 234 if (job && ring->funcs->emit_frame_cntl) { 235 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE; 236 amdgpu_ring_emit_frame_cntl(ring, true, secure); 237 } 238 239 for (i = 0; i < num_ibs; ++i) { 240 ib = &ibs[i]; 241 242 /* drop preamble IBs if we don't have a context switch */ 243 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 244 skip_preamble && 245 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 246 !amdgpu_mcbp && 247 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 248 continue; 249 250 if (job && ring->funcs->emit_frame_cntl) { 251 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) { 252 amdgpu_ring_emit_frame_cntl(ring, false, secure); 253 secure = !secure; 254 amdgpu_ring_emit_frame_cntl(ring, true, secure); 255 } 256 } 257 258 amdgpu_ring_emit_ib(ring, job, ib, status); 259 status &= ~AMDGPU_HAVE_CTX_SWITCH; 260 } 261 262 if (job && ring->funcs->emit_frame_cntl) 263 amdgpu_ring_emit_frame_cntl(ring, false, secure); 264 265 #ifdef CONFIG_X86_64 266 if (!(adev->flags & AMD_IS_APU)) 267 #endif 268 amdgpu_asic_invalidate_hdp(adev, ring); 269 270 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 271 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 272 273 /* wrap the last IB with fence */ 274 if (job && job->uf_addr) { 275 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 276 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 277 } 278 279 r = amdgpu_fence_emit(ring, f, fence_flags); 280 if (r) { 281 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 282 if (job && job->vmid) 283 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 284 amdgpu_ring_undo(ring); 285 return r; 286 } 287 288 if (ring->funcs->insert_end) 289 ring->funcs->insert_end(ring); 290 291 if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 292 amdgpu_ring_patch_cond_exec(ring, patch_offset); 293 294 ring->current_ctx = fence_ctx; 295 if (vm && ring->funcs->emit_switch_buffer) 296 amdgpu_ring_emit_switch_buffer(ring); 297 amdgpu_ring_commit(ring); 298 return 0; 299 } 300 301 /** 302 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 303 * 304 * @adev: amdgpu_device pointer 305 * 306 * Initialize the suballocator to manage a pool of memory 307 * for use as IBs (all asics). 308 * Returns 0 on success, error on failure. 309 */ 310 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 311 { 312 unsigned size; 313 int r, i; 314 315 if (adev->ib_pool_ready) 316 return 0; 317 318 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) { 319 if (i == AMDGPU_IB_POOL_DIRECT) 320 size = PAGE_SIZE * 2; 321 else 322 size = AMDGPU_IB_POOL_SIZE; 323 324 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], 325 size, AMDGPU_GPU_PAGE_SIZE, 326 AMDGPU_GEM_DOMAIN_GTT); 327 if (r) 328 goto error; 329 } 330 adev->ib_pool_ready = true; 331 332 return 0; 333 334 error: 335 while (i--) 336 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 337 return r; 338 } 339 340 /** 341 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 342 * 343 * @adev: amdgpu_device pointer 344 * 345 * Tear down the suballocator managing the pool of memory 346 * for use as IBs (all asics). 347 */ 348 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 349 { 350 int i; 351 352 if (!adev->ib_pool_ready) 353 return; 354 355 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) 356 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]); 357 adev->ib_pool_ready = false; 358 } 359 360 /** 361 * amdgpu_ib_ring_tests - test IBs on the rings 362 * 363 * @adev: amdgpu_device pointer 364 * 365 * Test an IB (Indirect Buffer) on each ring. 366 * If the test fails, disable the ring. 367 * Returns 0 on success, error if the primary GFX ring 368 * IB test fails. 369 */ 370 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 371 { 372 long tmo_gfx, tmo_mm; 373 int r, ret = 0; 374 unsigned i; 375 376 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 377 if (amdgpu_sriov_vf(adev)) { 378 /* for MM engines in hypervisor side they are not scheduled together 379 * with CP and SDMA engines, so even in exclusive mode MM engine could 380 * still running on other VF thus the IB TEST TIMEOUT for MM engines 381 * under SR-IOV should be set to a long time. 8 sec should be enough 382 * for the MM comes back to this VF. 383 */ 384 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 385 } 386 387 if (amdgpu_sriov_runtime(adev)) { 388 /* for CP & SDMA engines since they are scheduled together so 389 * need to make the timeout width enough to cover the time 390 * cost waiting for it coming back under RUNTIME only 391 */ 392 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 393 } else if (adev->gmc.xgmi.hive_id) { 394 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 395 } 396 397 for (i = 0; i < adev->num_rings; ++i) { 398 struct amdgpu_ring *ring = adev->rings[i]; 399 long tmo; 400 401 /* KIQ rings don't have an IB test because we never submit IBs 402 * to them and they have no interrupt support. 403 */ 404 if (!ring->sched.ready || !ring->funcs->test_ib) 405 continue; 406 407 /* MM engine need more time */ 408 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 409 ring->funcs->type == AMDGPU_RING_TYPE_VCE || 410 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 411 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 412 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 413 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 414 tmo = tmo_mm; 415 else 416 tmo = tmo_gfx; 417 418 r = amdgpu_ring_test_ib(ring, tmo); 419 if (!r) { 420 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 421 ring->name); 422 continue; 423 } 424 425 ring->sched.ready = false; 426 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 427 ring->name, r); 428 429 if (ring == &adev->gfx.gfx_ring[0]) { 430 /* oh, oh, that's really bad */ 431 adev->accel_working = false; 432 return r; 433 434 } else { 435 ret = r; 436 } 437 } 438 return ret; 439 } 440 441 /* 442 * Debugfs info 443 */ 444 #if defined(CONFIG_DEBUG_FS) 445 446 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 447 { 448 struct drm_info_node *node = (struct drm_info_node *) m->private; 449 struct drm_device *dev = node->minor->dev; 450 struct amdgpu_device *adev = drm_to_adev(dev); 451 452 seq_printf(m, "--------------------- DELAYED --------------------- \n"); 453 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED], 454 m); 455 seq_printf(m, "-------------------- IMMEDIATE -------------------- \n"); 456 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE], 457 m); 458 seq_printf(m, "--------------------- DIRECT ---------------------- \n"); 459 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m); 460 461 return 0; 462 } 463 464 static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 465 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 466 }; 467 468 #endif 469 470 int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 471 { 472 #if defined(CONFIG_DEBUG_FS) 473 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 474 ARRAY_SIZE(amdgpu_debugfs_sa_list)); 475 #else 476 return 0; 477 #endif 478 } 479