1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher 36bb7ad55bSChunming Zhou #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 37bbec97aaSChristian König 38d38ceaf9SAlex Deucher /* 39d38ceaf9SAlex Deucher * IB 40d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 41d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 42d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 43d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 44d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 45d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 46d38ceaf9SAlex Deucher */ 47d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 48d38ceaf9SAlex Deucher 49d38ceaf9SAlex Deucher /** 50d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 51d38ceaf9SAlex Deucher * 52d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 53d38ceaf9SAlex Deucher * @size: requested IB size 54d38ceaf9SAlex Deucher * @ib: IB object returned 55d38ceaf9SAlex Deucher * 56d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 57d38ceaf9SAlex Deucher * suballocator. 58d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 59d38ceaf9SAlex Deucher */ 60b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 61d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 62d38ceaf9SAlex Deucher { 63d38ceaf9SAlex Deucher int r; 64d38ceaf9SAlex Deucher 65d38ceaf9SAlex Deucher if (size) { 66bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 67d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 68d38ceaf9SAlex Deucher if (r) { 69d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 70d38ceaf9SAlex Deucher return r; 71d38ceaf9SAlex Deucher } 72d38ceaf9SAlex Deucher 73d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 74d38ceaf9SAlex Deucher 75d38ceaf9SAlex Deucher if (!vm) 76d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 77d38ceaf9SAlex Deucher } 78d38ceaf9SAlex Deucher 79d38ceaf9SAlex Deucher return 0; 80d38ceaf9SAlex Deucher } 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher /** 83d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 84d38ceaf9SAlex Deucher * 85d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 86d38ceaf9SAlex Deucher * @ib: IB object to free 87cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 88d38ceaf9SAlex Deucher * 89d38ceaf9SAlex Deucher * Free an IB (all asics). 90d38ceaf9SAlex Deucher */ 914d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 92f54d1867SChris Wilson struct dma_fence *f) 93d38ceaf9SAlex Deucher { 94cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95d38ceaf9SAlex Deucher } 96d38ceaf9SAlex Deucher 97d38ceaf9SAlex Deucher /** 98d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99d38ceaf9SAlex Deucher * 100d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 101d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 102d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 103ec72b800SChristian König * @f: fence created during this submission 104d38ceaf9SAlex Deucher * 105d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 106d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 107d38ceaf9SAlex Deucher * 108d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 109d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 110d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 111d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 112d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 113d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 114d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 115d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116d38ceaf9SAlex Deucher * to SI there was just a DE IB. 117d38ceaf9SAlex Deucher */ 118b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 11950ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 12050ddc75eSJunwei Zhang struct dma_fence **f) 121d38ceaf9SAlex Deucher { 122b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 123d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 124b9bf33d5SChunming Zhou struct dma_fence *tmp = NULL; 125f153d286SChristian König bool skip_preamble, need_ctx_switch; 12692f25098SChristian König unsigned patch_offset = ~0; 12792f25098SChristian König struct amdgpu_vm *vm; 1283aecd24cSMonk Liu uint64_t fence_ctx; 1299a9db6efSAlex Deucher uint32_t status = 0, alloc_size; 13003ccf481SMonk Liu 13192f25098SChristian König unsigned i; 132d38ceaf9SAlex Deucher int r = 0; 1338fdf074fSMonk Liu bool need_pipe_sync = false; 134d38ceaf9SAlex Deucher 135d38ceaf9SAlex Deucher if (num_ibs == 0) 136d38ceaf9SAlex Deucher return -EINVAL; 137d38ceaf9SAlex Deucher 13892f25098SChristian König /* ring tests don't use a job */ 13992f25098SChristian König if (job) { 140c5637837SMonk Liu vm = job->vm; 1413aecd24cSMonk Liu fence_ctx = job->fence_ctx; 14292f25098SChristian König } else { 14392f25098SChristian König vm = NULL; 1443aecd24cSMonk Liu fence_ctx = 0; 14592f25098SChristian König } 146d919ad49SChristian König 147d38ceaf9SAlex Deucher if (!ring->ready) { 1481b583649STom St Denis dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 149d38ceaf9SAlex Deucher return -EINVAL; 150d38ceaf9SAlex Deucher } 151be86c606SChunming Zhou 152d88bf583SChristian König if (vm && !job->vm_id) { 1538d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1548d0a7ceaSChristian König return -EINVAL; 1558d0a7ceaSChristian König } 1568d0a7ceaSChristian König 157e12f3d7aSChristian König alloc_size = ring->funcs->emit_frame_size + num_ibs * 158e12f3d7aSChristian König ring->funcs->emit_ib_size; 1599a9db6efSAlex Deucher 1609a9db6efSAlex Deucher r = amdgpu_ring_alloc(ring, alloc_size); 161d38ceaf9SAlex Deucher if (r) { 162d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 163d38ceaf9SAlex Deucher return r; 164d38ceaf9SAlex Deucher } 165df83d1ebSChunming Zhou 166df83d1ebSChunming Zhou if (ring->funcs->emit_pipeline_sync && job && 167cebb52b7SAndrey Grodzovsky ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 168b9bf33d5SChunming Zhou amdgpu_vm_need_pipeline_sync(ring, job))) { 1698fdf074fSMonk Liu need_pipe_sync = true; 170df83d1ebSChunming Zhou dma_fence_put(tmp); 171df83d1ebSChunming Zhou } 172d38ceaf9SAlex Deucher 173ef44f854SLeo Liu if (ring->funcs->insert_start) 174ef44f854SLeo Liu ring->funcs->insert_start(ring); 175ef44f854SLeo Liu 176df264f9eSChristian König if (job) { 1778fdf074fSMonk Liu r = amdgpu_vm_flush(ring, job, need_pipe_sync); 17841d9eb2cSChristian König if (r) { 17941d9eb2cSChristian König amdgpu_ring_undo(ring); 18041d9eb2cSChristian König return r; 18141d9eb2cSChristian König } 182794ff571SMonk Liu } 183d38ceaf9SAlex Deucher 184e9d672b2SMonk Liu if (ring->funcs->init_cond_exec) 185e9d672b2SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 186e9d672b2SMonk Liu 187c5cb934eSChristian König if (ring->funcs->emit_hdp_flush 188c5cb934eSChristian König #ifdef CONFIG_X86_64 189c5cb934eSChristian König && !(adev->flags & AMD_IS_APU) 190c5cb934eSChristian König #endif 191c5cb934eSChristian König ) 192d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 193d2edb07bSChristian König 1943aecd24cSMonk Liu skip_preamble = ring->current_ctx == fence_ctx; 1953aecd24cSMonk Liu need_ctx_switch = ring->current_ctx != fence_ctx; 196753ad49cSMonk Liu if (job && ring->funcs->emit_cntxcntl) { 197753ad49cSMonk Liu if (need_ctx_switch) 198753ad49cSMonk Liu status |= AMDGPU_HAVE_CTX_SWITCH; 199753ad49cSMonk Liu status |= job->preamble_status; 2007e6bf80fSMonk Liu 201753ad49cSMonk Liu amdgpu_ring_emit_cntxcntl(ring, status); 202753ad49cSMonk Liu } 203753ad49cSMonk Liu 204d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 205f153d286SChristian König ib = &ibs[i]; 2069f8fb5a2SChristian König 2079f8fb5a2SChristian König /* drop preamble IBs if we don't have a context switch */ 208753ad49cSMonk Liu if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 209753ad49cSMonk Liu skip_preamble && 21079bbbf8bSMonk Liu !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 21179bbbf8bSMonk Liu !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 2129f8fb5a2SChristian König continue; 2139f8fb5a2SChristian König 214d88bf583SChristian König amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 215d88bf583SChristian König need_ctx_switch); 216f153d286SChristian König need_ctx_switch = false; 217d38ceaf9SAlex Deucher } 218d38ceaf9SAlex Deucher 2193b4d68e9SMonk Liu if (ring->funcs->emit_tmz) 2203b4d68e9SMonk Liu amdgpu_ring_emit_tmz(ring, false); 2213b4d68e9SMonk Liu 222c5cb934eSChristian König if (ring->funcs->emit_hdp_invalidate 223c5cb934eSChristian König #ifdef CONFIG_X86_64 224c5cb934eSChristian König && !(adev->flags & AMD_IS_APU) 225c5cb934eSChristian König #endif 226c5cb934eSChristian König ) 22711afbde8SChunming Zhou amdgpu_ring_emit_hdp_invalidate(ring); 22811afbde8SChunming Zhou 22922a77cf6SChristian König r = amdgpu_fence_emit(ring, f); 230d38ceaf9SAlex Deucher if (r) { 231d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 232d88bf583SChristian König if (job && job->vm_id) 2337645670dSChristian König amdgpu_vm_reset_id(adev, ring->funcs->vmhub, 2347645670dSChristian König job->vm_id); 235a27de35cSChristian König amdgpu_ring_undo(ring); 236d38ceaf9SAlex Deucher return r; 237d38ceaf9SAlex Deucher } 238d38ceaf9SAlex Deucher 239135d4735SLeo Liu if (ring->funcs->insert_end) 240135d4735SLeo Liu ring->funcs->insert_end(ring); 241135d4735SLeo Liu 242d38ceaf9SAlex Deucher /* wrap the last IB with fence */ 243b5f5acbcSChristian König if (job && job->uf_addr) { 244b5f5acbcSChristian König amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 245890ee23fSChunming Zhou AMDGPU_FENCE_FLAG_64BIT); 246d38ceaf9SAlex Deucher } 247d38ceaf9SAlex Deucher 24803ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 24903ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 25003ccf481SMonk Liu 2513aecd24cSMonk Liu ring->current_ctx = fence_ctx; 252bc1e59b2SMonk Liu if (vm && ring->funcs->emit_switch_buffer) 253c2167a65SMonk Liu amdgpu_ring_emit_switch_buffer(ring); 254a27de35cSChristian König amdgpu_ring_commit(ring); 255d38ceaf9SAlex Deucher return 0; 256d38ceaf9SAlex Deucher } 257d38ceaf9SAlex Deucher 258d38ceaf9SAlex Deucher /** 259d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 260d38ceaf9SAlex Deucher * 261d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 262d38ceaf9SAlex Deucher * 263d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 264d38ceaf9SAlex Deucher * for use as IBs (all asics). 265d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 266d38ceaf9SAlex Deucher */ 267d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 268d38ceaf9SAlex Deucher { 269d38ceaf9SAlex Deucher int r; 270d38ceaf9SAlex Deucher 271d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 272d38ceaf9SAlex Deucher return 0; 273d38ceaf9SAlex Deucher } 274d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 275d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 276d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 277d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 278d38ceaf9SAlex Deucher if (r) { 279d38ceaf9SAlex Deucher return r; 280d38ceaf9SAlex Deucher } 281d38ceaf9SAlex Deucher 282d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 283d38ceaf9SAlex Deucher if (r) { 284d38ceaf9SAlex Deucher return r; 285d38ceaf9SAlex Deucher } 286d38ceaf9SAlex Deucher 287d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 288d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 289d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 290d38ceaf9SAlex Deucher } 291d38ceaf9SAlex Deucher return 0; 292d38ceaf9SAlex Deucher } 293d38ceaf9SAlex Deucher 294d38ceaf9SAlex Deucher /** 295d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 296d38ceaf9SAlex Deucher * 297d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 298d38ceaf9SAlex Deucher * 299d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 300d38ceaf9SAlex Deucher * for use as IBs (all asics). 301d38ceaf9SAlex Deucher */ 302d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 303d38ceaf9SAlex Deucher { 304d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 305d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 306d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 307d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 308d38ceaf9SAlex Deucher } 309d38ceaf9SAlex Deucher } 310d38ceaf9SAlex Deucher 311d38ceaf9SAlex Deucher /** 312d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 313d38ceaf9SAlex Deucher * 314d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 315d38ceaf9SAlex Deucher * 316d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 317d38ceaf9SAlex Deucher * If the test fails, disable the ring. 318d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 319d38ceaf9SAlex Deucher * IB test fails. 320d38ceaf9SAlex Deucher */ 321d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 322d38ceaf9SAlex Deucher { 323d38ceaf9SAlex Deucher unsigned i; 3241f703e66SChunming Zhou int r, ret = 0; 325d38ceaf9SAlex Deucher 326d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 327d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 328d38ceaf9SAlex Deucher 329d38ceaf9SAlex Deucher if (!ring || !ring->ready) 330d38ceaf9SAlex Deucher continue; 331d38ceaf9SAlex Deucher 332bbec97aaSChristian König r = amdgpu_ring_test_ib(ring, AMDGPU_IB_TEST_TIMEOUT); 333d38ceaf9SAlex Deucher if (r) { 334d38ceaf9SAlex Deucher ring->ready = false; 335d38ceaf9SAlex Deucher 336d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 337d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 338d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 339d38ceaf9SAlex Deucher adev->accel_working = false; 340d38ceaf9SAlex Deucher return r; 341d38ceaf9SAlex Deucher 342d38ceaf9SAlex Deucher } else { 343d38ceaf9SAlex Deucher /* still not good, but we can live with it */ 344d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 3451f703e66SChunming Zhou ret = r; 346d38ceaf9SAlex Deucher } 347d38ceaf9SAlex Deucher } 348d38ceaf9SAlex Deucher } 3491f703e66SChunming Zhou return ret; 350d38ceaf9SAlex Deucher } 351d38ceaf9SAlex Deucher 352d38ceaf9SAlex Deucher /* 353d38ceaf9SAlex Deucher * Debugfs info 354d38ceaf9SAlex Deucher */ 355d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 356d38ceaf9SAlex Deucher 357d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 358d38ceaf9SAlex Deucher { 359d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 360d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 361d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 362d38ceaf9SAlex Deucher 363d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 364d38ceaf9SAlex Deucher 365d38ceaf9SAlex Deucher return 0; 366d38ceaf9SAlex Deucher 367d38ceaf9SAlex Deucher } 368d38ceaf9SAlex Deucher 36906ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 370d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 371d38ceaf9SAlex Deucher }; 372d38ceaf9SAlex Deucher 373d38ceaf9SAlex Deucher #endif 374d38ceaf9SAlex Deucher 375d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 376d38ceaf9SAlex Deucher { 377d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 378d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 379d38ceaf9SAlex Deucher #else 380d38ceaf9SAlex Deucher return 0; 381d38ceaf9SAlex Deucher #endif 382d38ceaf9SAlex Deucher } 383