1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 3565f7260bSAndrey Grodzovsky #include "amdgpu_trace.h" 36d38ceaf9SAlex Deucher 37bb7ad55bSChunming Zhou #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 38bbec97aaSChristian König 39d38ceaf9SAlex Deucher /* 40d38ceaf9SAlex Deucher * IB 41d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 42d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 43d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 44d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 45d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 46d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 47d38ceaf9SAlex Deucher */ 48d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 49d38ceaf9SAlex Deucher 50d38ceaf9SAlex Deucher /** 51d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 52d38ceaf9SAlex Deucher * 53d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 54d38ceaf9SAlex Deucher * @size: requested IB size 55d38ceaf9SAlex Deucher * @ib: IB object returned 56d38ceaf9SAlex Deucher * 57d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 58d38ceaf9SAlex Deucher * suballocator. 59d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 60d38ceaf9SAlex Deucher */ 61b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 62d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 63d38ceaf9SAlex Deucher { 64d38ceaf9SAlex Deucher int r; 65d38ceaf9SAlex Deucher 66d38ceaf9SAlex Deucher if (size) { 67bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 68d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 69d38ceaf9SAlex Deucher if (r) { 70d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 71d38ceaf9SAlex Deucher return r; 72d38ceaf9SAlex Deucher } 73d38ceaf9SAlex Deucher 74d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 75d38ceaf9SAlex Deucher 76d38ceaf9SAlex Deucher if (!vm) 77d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 78d38ceaf9SAlex Deucher } 79d38ceaf9SAlex Deucher 80d38ceaf9SAlex Deucher return 0; 81d38ceaf9SAlex Deucher } 82d38ceaf9SAlex Deucher 83d38ceaf9SAlex Deucher /** 84d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 85d38ceaf9SAlex Deucher * 86d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 87d38ceaf9SAlex Deucher * @ib: IB object to free 88cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 89d38ceaf9SAlex Deucher * 90d38ceaf9SAlex Deucher * Free an IB (all asics). 91d38ceaf9SAlex Deucher */ 924d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 93f54d1867SChris Wilson struct dma_fence *f) 94d38ceaf9SAlex Deucher { 95cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 96d38ceaf9SAlex Deucher } 97d38ceaf9SAlex Deucher 98d38ceaf9SAlex Deucher /** 99d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 100d38ceaf9SAlex Deucher * 101d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 102d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 103d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 104ec72b800SChristian König * @f: fence created during this submission 105d38ceaf9SAlex Deucher * 106d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 107d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 108d38ceaf9SAlex Deucher * 109d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 110d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 111d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 112d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 113d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 114d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 115d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 116d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 117d38ceaf9SAlex Deucher * to SI there was just a DE IB. 118d38ceaf9SAlex Deucher */ 119b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 12050ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 12150ddc75eSJunwei Zhang struct dma_fence **f) 122d38ceaf9SAlex Deucher { 123b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 124d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 125b9bf33d5SChunming Zhou struct dma_fence *tmp = NULL; 126f153d286SChristian König bool skip_preamble, need_ctx_switch; 12792f25098SChristian König unsigned patch_offset = ~0; 12892f25098SChristian König struct amdgpu_vm *vm; 1293aecd24cSMonk Liu uint64_t fence_ctx; 1309a9db6efSAlex Deucher uint32_t status = 0, alloc_size; 131d240cd9eSMarek Olšák unsigned fence_flags = 0; 13203ccf481SMonk Liu 13392f25098SChristian König unsigned i; 134d38ceaf9SAlex Deucher int r = 0; 1358fdf074fSMonk Liu bool need_pipe_sync = false; 136d38ceaf9SAlex Deucher 137d38ceaf9SAlex Deucher if (num_ibs == 0) 138d38ceaf9SAlex Deucher return -EINVAL; 139d38ceaf9SAlex Deucher 14092f25098SChristian König /* ring tests don't use a job */ 14192f25098SChristian König if (job) { 142c5637837SMonk Liu vm = job->vm; 143eb3961a5SChristian König fence_ctx = job->base.s_fence->scheduled.context; 14492f25098SChristian König } else { 14592f25098SChristian König vm = NULL; 1463aecd24cSMonk Liu fence_ctx = 0; 14792f25098SChristian König } 148d919ad49SChristian König 149c66ed765SAndrey Grodzovsky if (!ring->sched.ready) { 1501b583649STom St Denis dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 151d38ceaf9SAlex Deucher return -EINVAL; 152d38ceaf9SAlex Deucher } 153be86c606SChunming Zhou 154c4f46f22SChristian König if (vm && !job->vmid) { 1558d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1568d0a7ceaSChristian König return -EINVAL; 1578d0a7ceaSChristian König } 1588d0a7ceaSChristian König 159e12f3d7aSChristian König alloc_size = ring->funcs->emit_frame_size + num_ibs * 160e12f3d7aSChristian König ring->funcs->emit_ib_size; 1619a9db6efSAlex Deucher 1629a9db6efSAlex Deucher r = amdgpu_ring_alloc(ring, alloc_size); 163d38ceaf9SAlex Deucher if (r) { 164d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 165d38ceaf9SAlex Deucher return r; 166d38ceaf9SAlex Deucher } 167df83d1ebSChunming Zhou 1684f0ecd36SEmily Deng need_ctx_switch = ring->current_ctx != fence_ctx; 169df83d1ebSChunming Zhou if (ring->funcs->emit_pipeline_sync && job && 170cebb52b7SAndrey Grodzovsky ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 1714f0ecd36SEmily Deng (amdgpu_sriov_vf(adev) && need_ctx_switch) || 172b9bf33d5SChunming Zhou amdgpu_vm_need_pipeline_sync(ring, job))) { 1738fdf074fSMonk Liu need_pipe_sync = true; 17465f7260bSAndrey Grodzovsky 17565f7260bSAndrey Grodzovsky if (tmp) 17665f7260bSAndrey Grodzovsky trace_amdgpu_ib_pipe_sync(job, tmp); 17765f7260bSAndrey Grodzovsky 178df83d1ebSChunming Zhou dma_fence_put(tmp); 179df83d1ebSChunming Zhou } 180d38ceaf9SAlex Deucher 181ef44f854SLeo Liu if (ring->funcs->insert_start) 182ef44f854SLeo Liu ring->funcs->insert_start(ring); 183ef44f854SLeo Liu 184df264f9eSChristian König if (job) { 1858fdf074fSMonk Liu r = amdgpu_vm_flush(ring, job, need_pipe_sync); 18641d9eb2cSChristian König if (r) { 18741d9eb2cSChristian König amdgpu_ring_undo(ring); 18841d9eb2cSChristian König return r; 18941d9eb2cSChristian König } 190794ff571SMonk Liu } 191d38ceaf9SAlex Deucher 192113890eeSMonk Liu if (job && ring->funcs->init_cond_exec) 193e9d672b2SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 194e9d672b2SMonk Liu 195c5cb934eSChristian König #ifdef CONFIG_X86_64 1961b9d17dbSChristian König if (!(adev->flags & AMD_IS_APU)) 197c5cb934eSChristian König #endif 1981b9d17dbSChristian König { 1991b9d17dbSChristian König if (ring->funcs->emit_hdp_flush) 200d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 2011b9d17dbSChristian König else 2021b9d17dbSChristian König amdgpu_asic_flush_hdp(adev, ring); 2031b9d17dbSChristian König } 204d2edb07bSChristian König 205753ad49cSMonk Liu if (need_ctx_switch) 206753ad49cSMonk Liu status |= AMDGPU_HAVE_CTX_SWITCH; 2077e6bf80fSMonk Liu 208c4c905ecSJack Xiao skip_preamble = ring->current_ctx == fence_ctx; 209c4c905ecSJack Xiao if (job && ring->funcs->emit_cntxcntl) { 210c4c905ecSJack Xiao status |= job->preamble_status; 211753ad49cSMonk Liu amdgpu_ring_emit_cntxcntl(ring, status); 212753ad49cSMonk Liu } 213753ad49cSMonk Liu 214d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 215f153d286SChristian König ib = &ibs[i]; 2169f8fb5a2SChristian König 2179f8fb5a2SChristian König /* drop preamble IBs if we don't have a context switch */ 218753ad49cSMonk Liu if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 219753ad49cSMonk Liu skip_preamble && 22079bbbf8bSMonk Liu !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 22179bbbf8bSMonk Liu !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 2229f8fb5a2SChristian König continue; 2239f8fb5a2SChristian König 224c4c905ecSJack Xiao amdgpu_ring_emit_ib(ring, job, ib, status); 225c4c905ecSJack Xiao status &= ~AMDGPU_HAVE_CTX_SWITCH; 226d38ceaf9SAlex Deucher } 227d38ceaf9SAlex Deucher 2283b4d68e9SMonk Liu if (ring->funcs->emit_tmz) 2293b4d68e9SMonk Liu amdgpu_ring_emit_tmz(ring, false); 2303b4d68e9SMonk Liu 231c5cb934eSChristian König #ifdef CONFIG_X86_64 2321b9d17dbSChristian König if (!(adev->flags & AMD_IS_APU)) 233c5cb934eSChristian König #endif 2341b9d17dbSChristian König amdgpu_asic_invalidate_hdp(adev, ring); 23511afbde8SChunming Zhou 236d240cd9eSMarek Olšák if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 237d240cd9eSMarek Olšák fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 238d240cd9eSMarek Olšák 2399fc15f5fSNicolai Hähnle /* wrap the last IB with fence */ 2409fc15f5fSNicolai Hähnle if (job && job->uf_addr) { 2419fc15f5fSNicolai Hähnle amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 2429fc15f5fSNicolai Hähnle fence_flags | AMDGPU_FENCE_FLAG_64BIT); 2439fc15f5fSNicolai Hähnle } 2449fc15f5fSNicolai Hähnle 245d240cd9eSMarek Olšák r = amdgpu_fence_emit(ring, f, fence_flags); 246d38ceaf9SAlex Deucher if (r) { 247d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 248c4f46f22SChristian König if (job && job->vmid) 249c4f46f22SChristian König amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 250a27de35cSChristian König amdgpu_ring_undo(ring); 251d38ceaf9SAlex Deucher return r; 252d38ceaf9SAlex Deucher } 253d38ceaf9SAlex Deucher 254135d4735SLeo Liu if (ring->funcs->insert_end) 255135d4735SLeo Liu ring->funcs->insert_end(ring); 256135d4735SLeo Liu 25703ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 25803ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 25903ccf481SMonk Liu 2603aecd24cSMonk Liu ring->current_ctx = fence_ctx; 261bc1e59b2SMonk Liu if (vm && ring->funcs->emit_switch_buffer) 262c2167a65SMonk Liu amdgpu_ring_emit_switch_buffer(ring); 263a27de35cSChristian König amdgpu_ring_commit(ring); 264d38ceaf9SAlex Deucher return 0; 265d38ceaf9SAlex Deucher } 266d38ceaf9SAlex Deucher 267d38ceaf9SAlex Deucher /** 268d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 269d38ceaf9SAlex Deucher * 270d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 271d38ceaf9SAlex Deucher * 272d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 273d38ceaf9SAlex Deucher * for use as IBs (all asics). 274d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 275d38ceaf9SAlex Deucher */ 276d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 277d38ceaf9SAlex Deucher { 278d38ceaf9SAlex Deucher int r; 279d38ceaf9SAlex Deucher 280d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 281d38ceaf9SAlex Deucher return 0; 282d38ceaf9SAlex Deucher } 283d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 284d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 285d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 286d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 287d38ceaf9SAlex Deucher if (r) { 288d38ceaf9SAlex Deucher return r; 289d38ceaf9SAlex Deucher } 290d38ceaf9SAlex Deucher 291d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 292d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 293d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 294d38ceaf9SAlex Deucher } 295d38ceaf9SAlex Deucher return 0; 296d38ceaf9SAlex Deucher } 297d38ceaf9SAlex Deucher 298d38ceaf9SAlex Deucher /** 299d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 300d38ceaf9SAlex Deucher * 301d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 302d38ceaf9SAlex Deucher * 303d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 304d38ceaf9SAlex Deucher * for use as IBs (all asics). 305d38ceaf9SAlex Deucher */ 306d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 307d38ceaf9SAlex Deucher { 308d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 309d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 310d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 311d38ceaf9SAlex Deucher } 312d38ceaf9SAlex Deucher } 313d38ceaf9SAlex Deucher 314d38ceaf9SAlex Deucher /** 315d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 316d38ceaf9SAlex Deucher * 317d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 318d38ceaf9SAlex Deucher * 319d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 320d38ceaf9SAlex Deucher * If the test fails, disable the ring. 321d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 322d38ceaf9SAlex Deucher * IB test fails. 323d38ceaf9SAlex Deucher */ 324d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 325d38ceaf9SAlex Deucher { 326d38ceaf9SAlex Deucher unsigned i; 3271f703e66SChunming Zhou int r, ret = 0; 328dbf79765SMonk Liu long tmo_gfx, tmo_mm; 329dbf79765SMonk Liu 330dbf79765SMonk Liu tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 331dbf79765SMonk Liu if (amdgpu_sriov_vf(adev)) { 332dbf79765SMonk Liu /* for MM engines in hypervisor side they are not scheduled together 333dbf79765SMonk Liu * with CP and SDMA engines, so even in exclusive mode MM engine could 334dbf79765SMonk Liu * still running on other VF thus the IB TEST TIMEOUT for MM engines 335dbf79765SMonk Liu * under SR-IOV should be set to a long time. 8 sec should be enough 336dbf79765SMonk Liu * for the MM comes back to this VF. 337dbf79765SMonk Liu */ 338dbf79765SMonk Liu tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 339dbf79765SMonk Liu } 340dbf79765SMonk Liu 341dbf79765SMonk Liu if (amdgpu_sriov_runtime(adev)) { 342dbf79765SMonk Liu /* for CP & SDMA engines since they are scheduled together so 343dbf79765SMonk Liu * need to make the timeout width enough to cover the time 344dbf79765SMonk Liu * cost waiting for it coming back under RUNTIME only 345dbf79765SMonk Liu */ 346dbf79765SMonk Liu tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 347dbf79765SMonk Liu } 348d38ceaf9SAlex Deucher 349af70a471SChristian König for (i = 0; i < adev->num_rings; ++i) { 350d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 351dbf79765SMonk Liu long tmo; 352d38ceaf9SAlex Deucher 353315fed03SChristian König /* KIQ rings don't have an IB test because we never submit IBs 354315fed03SChristian König * to them and they have no interrupt support. 355158b594aSPratik Vishwakarma */ 356315fed03SChristian König if (!ring->sched.ready || !ring->funcs->test_ib) 357158b594aSPratik Vishwakarma continue; 358158b594aSPratik Vishwakarma 359dbf79765SMonk Liu /* MM engine need more time */ 360dbf79765SMonk Liu if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 361dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_VCE || 362dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 363dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 3645b2329b6SBoyuan Zhang ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 3655b2329b6SBoyuan Zhang ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 366dbf79765SMonk Liu tmo = tmo_mm; 367dbf79765SMonk Liu else 368dbf79765SMonk Liu tmo = tmo_gfx; 369dbf79765SMonk Liu 370dbf79765SMonk Liu r = amdgpu_ring_test_ib(ring, tmo); 371af70a471SChristian König if (!r) { 372af70a471SChristian König DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 373af70a471SChristian König ring->name); 374af70a471SChristian König continue; 375af70a471SChristian König } 376af70a471SChristian König 377c66ed765SAndrey Grodzovsky ring->sched.ready = false; 378af70a471SChristian König DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 379af70a471SChristian König ring->name, r); 380d38ceaf9SAlex Deucher 381d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 382d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 383d38ceaf9SAlex Deucher adev->accel_working = false; 384d38ceaf9SAlex Deucher return r; 385d38ceaf9SAlex Deucher 386d38ceaf9SAlex Deucher } else { 3871f703e66SChunming Zhou ret = r; 388d38ceaf9SAlex Deucher } 389d38ceaf9SAlex Deucher } 3901f703e66SChunming Zhou return ret; 391d38ceaf9SAlex Deucher } 392d38ceaf9SAlex Deucher 393d38ceaf9SAlex Deucher /* 394d38ceaf9SAlex Deucher * Debugfs info 395d38ceaf9SAlex Deucher */ 396d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 397d38ceaf9SAlex Deucher 398d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 399d38ceaf9SAlex Deucher { 400d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 401d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 402d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 403d38ceaf9SAlex Deucher 404d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 405d38ceaf9SAlex Deucher 406d38ceaf9SAlex Deucher return 0; 407d38ceaf9SAlex Deucher 408d38ceaf9SAlex Deucher } 409d38ceaf9SAlex Deucher 41006ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 411d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 412d38ceaf9SAlex Deucher }; 413d38ceaf9SAlex Deucher 414d38ceaf9SAlex Deucher #endif 415d38ceaf9SAlex Deucher 416d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 417d38ceaf9SAlex Deucher { 418d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 419d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 420d38ceaf9SAlex Deucher #else 421d38ceaf9SAlex Deucher return 0; 422d38ceaf9SAlex Deucher #endif 423d38ceaf9SAlex Deucher } 424