1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher 36d38ceaf9SAlex Deucher /* 37d38ceaf9SAlex Deucher * IB 38d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 39d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 40d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 41d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 42d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 43d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 44d38ceaf9SAlex Deucher */ 45d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 46d38ceaf9SAlex Deucher 47d38ceaf9SAlex Deucher /** 48d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 49d38ceaf9SAlex Deucher * 50d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 51d38ceaf9SAlex Deucher * @size: requested IB size 52d38ceaf9SAlex Deucher * @ib: IB object returned 53d38ceaf9SAlex Deucher * 54d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 55d38ceaf9SAlex Deucher * suballocator. 56d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 57d38ceaf9SAlex Deucher */ 58d38ceaf9SAlex Deucher int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 59d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 60d38ceaf9SAlex Deucher { 61d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 62d38ceaf9SAlex Deucher int r; 63d38ceaf9SAlex Deucher 64d38ceaf9SAlex Deucher if (size) { 65bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 66d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 67d38ceaf9SAlex Deucher if (r) { 68d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 69d38ceaf9SAlex Deucher return r; 70d38ceaf9SAlex Deucher } 71d38ceaf9SAlex Deucher 72d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 73d38ceaf9SAlex Deucher 74d38ceaf9SAlex Deucher if (!vm) 75d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 76d38ceaf9SAlex Deucher } 77d38ceaf9SAlex Deucher 78d38ceaf9SAlex Deucher amdgpu_sync_create(&ib->sync); 79d38ceaf9SAlex Deucher 80d38ceaf9SAlex Deucher ib->ring = ring; 81d38ceaf9SAlex Deucher ib->vm = vm; 82d38ceaf9SAlex Deucher 83d38ceaf9SAlex Deucher return 0; 84d38ceaf9SAlex Deucher } 85d38ceaf9SAlex Deucher 86d38ceaf9SAlex Deucher /** 87d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 88d38ceaf9SAlex Deucher * 89d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 90d38ceaf9SAlex Deucher * @ib: IB object to free 91d38ceaf9SAlex Deucher * 92d38ceaf9SAlex Deucher * Free an IB (all asics). 93d38ceaf9SAlex Deucher */ 94d38ceaf9SAlex Deucher void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) 95d38ceaf9SAlex Deucher { 964ce9891eSChunming Zhou amdgpu_sync_free(adev, &ib->sync, &ib->fence->base); 974ce9891eSChunming Zhou amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base); 986ef68c17SChristian König if (ib->fence) 996ef68c17SChristian König fence_put(&ib->fence->base); 100d38ceaf9SAlex Deucher } 101d38ceaf9SAlex Deucher 102d38ceaf9SAlex Deucher /** 103d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 104d38ceaf9SAlex Deucher * 105d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 106d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 107d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 108d38ceaf9SAlex Deucher * @owner: owner for creating the fences 109d38ceaf9SAlex Deucher * 110d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 111d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 112d38ceaf9SAlex Deucher * 113d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 114d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 115d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 116d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 117d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 118d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 119d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 120d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 121d38ceaf9SAlex Deucher * to SI there was just a DE IB. 122d38ceaf9SAlex Deucher */ 123d38ceaf9SAlex Deucher int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 124d38ceaf9SAlex Deucher struct amdgpu_ib *ibs, void *owner) 125d38ceaf9SAlex Deucher { 126d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 127d919ad49SChristian König struct amdgpu_ring *ring; 1283cb485f3SChristian König struct amdgpu_ctx *ctx, *old_ctx; 129d919ad49SChristian König struct amdgpu_vm *vm; 130d38ceaf9SAlex Deucher unsigned i; 131d38ceaf9SAlex Deucher int r = 0; 132d38ceaf9SAlex Deucher 133d38ceaf9SAlex Deucher if (num_ibs == 0) 134d38ceaf9SAlex Deucher return -EINVAL; 135d38ceaf9SAlex Deucher 136d38ceaf9SAlex Deucher ring = ibs->ring; 1373cb485f3SChristian König ctx = ibs->ctx; 138d919ad49SChristian König vm = ibs->vm; 139d919ad49SChristian König 140d38ceaf9SAlex Deucher if (!ring->ready) { 141d38ceaf9SAlex Deucher dev_err(adev->dev, "couldn't schedule ib\n"); 142d38ceaf9SAlex Deucher return -EINVAL; 143d38ceaf9SAlex Deucher } 144be86c606SChunming Zhou 145d38ceaf9SAlex Deucher r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs); 146d38ceaf9SAlex Deucher if (r) { 147d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 148d38ceaf9SAlex Deucher return r; 149d38ceaf9SAlex Deucher } 150d38ceaf9SAlex Deucher 151d38ceaf9SAlex Deucher if (vm) { 152d38ceaf9SAlex Deucher /* grab a vm id if necessary */ 1537f8a5290SChristian König r = amdgpu_vm_grab_id(ibs->vm, ibs->ring, &ibs->sync); 15491e1a520SChristian König if (r) { 15591e1a520SChristian König amdgpu_ring_unlock_undo(ring); 15691e1a520SChristian König return r; 15791e1a520SChristian König } 158d38ceaf9SAlex Deucher } 159d38ceaf9SAlex Deucher 160be86c606SChunming Zhou r = amdgpu_sync_wait(&ibs->sync); 161d38ceaf9SAlex Deucher if (r) { 162d38ceaf9SAlex Deucher amdgpu_ring_unlock_undo(ring); 163be86c606SChunming Zhou dev_err(adev->dev, "failed to sync wait (%d)\n", r); 164d38ceaf9SAlex Deucher return r; 165d38ceaf9SAlex Deucher } 166d38ceaf9SAlex Deucher 167d38ceaf9SAlex Deucher if (vm) { 168d38ceaf9SAlex Deucher /* do context switch */ 169d38ceaf9SAlex Deucher amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); 170d38ceaf9SAlex Deucher 171e722b71aSmonk.liu if (ring->funcs->emit_gds_switch) 172d38ceaf9SAlex Deucher amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, 173d38ceaf9SAlex Deucher ib->gds_base, ib->gds_size, 174d38ceaf9SAlex Deucher ib->gws_base, ib->gws_size, 175d38ceaf9SAlex Deucher ib->oa_base, ib->oa_size); 176d38ceaf9SAlex Deucher 177d2edb07bSChristian König if (ring->funcs->emit_hdp_flush) 178d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 179e722b71aSmonk.liu } 180d2edb07bSChristian König 1813cb485f3SChristian König old_ctx = ring->current_ctx; 182d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 183d38ceaf9SAlex Deucher ib = &ibs[i]; 184d38ceaf9SAlex Deucher 1853cb485f3SChristian König if (ib->ring != ring || ib->ctx != ctx || ib->vm != vm) { 1863cb485f3SChristian König ring->current_ctx = old_ctx; 187d38ceaf9SAlex Deucher amdgpu_ring_unlock_undo(ring); 188d38ceaf9SAlex Deucher return -EINVAL; 189d38ceaf9SAlex Deucher } 190d38ceaf9SAlex Deucher amdgpu_ring_emit_ib(ring, ib); 1913cb485f3SChristian König ring->current_ctx = ctx; 192d38ceaf9SAlex Deucher } 193d38ceaf9SAlex Deucher 194d38ceaf9SAlex Deucher r = amdgpu_fence_emit(ring, owner, &ib->fence); 195d38ceaf9SAlex Deucher if (r) { 196d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 1973cb485f3SChristian König ring->current_ctx = old_ctx; 198d38ceaf9SAlex Deucher amdgpu_ring_unlock_undo(ring); 199d38ceaf9SAlex Deucher return r; 200d38ceaf9SAlex Deucher } 201d38ceaf9SAlex Deucher 202f556cb0cSChunming Zhou if (!amdgpu_enable_scheduler && ib->ctx) 2035430a3ffSChristian König ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring, 204ce882e6dSChristian König &ib->fence->base); 2055430a3ffSChristian König 206d38ceaf9SAlex Deucher /* wrap the last IB with fence */ 207d38ceaf9SAlex Deucher if (ib->user) { 208d38ceaf9SAlex Deucher uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 209d38ceaf9SAlex Deucher addr += ib->user->offset; 2105430a3ffSChristian König amdgpu_ring_emit_fence(ring, addr, ib->sequence, 211890ee23fSChunming Zhou AMDGPU_FENCE_FLAG_64BIT); 212d38ceaf9SAlex Deucher } 213d38ceaf9SAlex Deucher 214d38ceaf9SAlex Deucher if (ib->vm) 21516ae42feSChristian König amdgpu_vm_fence(adev, ib->vm, &ib->fence->base); 216d38ceaf9SAlex Deucher 217d38ceaf9SAlex Deucher amdgpu_ring_unlock_commit(ring); 218d38ceaf9SAlex Deucher return 0; 219d38ceaf9SAlex Deucher } 220d38ceaf9SAlex Deucher 221d38ceaf9SAlex Deucher /** 222d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 223d38ceaf9SAlex Deucher * 224d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 225d38ceaf9SAlex Deucher * 226d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 227d38ceaf9SAlex Deucher * for use as IBs (all asics). 228d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 229d38ceaf9SAlex Deucher */ 230d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 231d38ceaf9SAlex Deucher { 232d38ceaf9SAlex Deucher int r; 233d38ceaf9SAlex Deucher 234d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 235d38ceaf9SAlex Deucher return 0; 236d38ceaf9SAlex Deucher } 237d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 238d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 239d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 240d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 241d38ceaf9SAlex Deucher if (r) { 242d38ceaf9SAlex Deucher return r; 243d38ceaf9SAlex Deucher } 244d38ceaf9SAlex Deucher 245d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 246d38ceaf9SAlex Deucher if (r) { 247d38ceaf9SAlex Deucher return r; 248d38ceaf9SAlex Deucher } 249d38ceaf9SAlex Deucher 250d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 251d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 252d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 253d38ceaf9SAlex Deucher } 254d38ceaf9SAlex Deucher return 0; 255d38ceaf9SAlex Deucher } 256d38ceaf9SAlex Deucher 257d38ceaf9SAlex Deucher /** 258d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 259d38ceaf9SAlex Deucher * 260d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 261d38ceaf9SAlex Deucher * 262d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 263d38ceaf9SAlex Deucher * for use as IBs (all asics). 264d38ceaf9SAlex Deucher */ 265d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 266d38ceaf9SAlex Deucher { 267d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 268d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 269d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 270d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 271d38ceaf9SAlex Deucher } 272d38ceaf9SAlex Deucher } 273d38ceaf9SAlex Deucher 274d38ceaf9SAlex Deucher /** 275d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 276d38ceaf9SAlex Deucher * 277d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 278d38ceaf9SAlex Deucher * 279d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 280d38ceaf9SAlex Deucher * If the test fails, disable the ring. 281d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 282d38ceaf9SAlex Deucher * IB test fails. 283d38ceaf9SAlex Deucher */ 284d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 285d38ceaf9SAlex Deucher { 286d38ceaf9SAlex Deucher unsigned i; 287d38ceaf9SAlex Deucher int r; 288d38ceaf9SAlex Deucher 289d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 290d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 291d38ceaf9SAlex Deucher 292d38ceaf9SAlex Deucher if (!ring || !ring->ready) 293d38ceaf9SAlex Deucher continue; 294d38ceaf9SAlex Deucher 295d38ceaf9SAlex Deucher r = amdgpu_ring_test_ib(ring); 296d38ceaf9SAlex Deucher if (r) { 297d38ceaf9SAlex Deucher ring->ready = false; 298d38ceaf9SAlex Deucher 299d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 300d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 301d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 302d38ceaf9SAlex Deucher adev->accel_working = false; 303d38ceaf9SAlex Deucher return r; 304d38ceaf9SAlex Deucher 305d38ceaf9SAlex Deucher } else { 306d38ceaf9SAlex Deucher /* still not good, but we can live with it */ 307d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 308d38ceaf9SAlex Deucher } 309d38ceaf9SAlex Deucher } 310d38ceaf9SAlex Deucher } 311d38ceaf9SAlex Deucher return 0; 312d38ceaf9SAlex Deucher } 313d38ceaf9SAlex Deucher 314d38ceaf9SAlex Deucher /* 315d38ceaf9SAlex Deucher * Debugfs info 316d38ceaf9SAlex Deucher */ 317d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 318d38ceaf9SAlex Deucher 319d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 320d38ceaf9SAlex Deucher { 321d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 322d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 323d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 324d38ceaf9SAlex Deucher 325d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 326d38ceaf9SAlex Deucher 327d38ceaf9SAlex Deucher return 0; 328d38ceaf9SAlex Deucher 329d38ceaf9SAlex Deucher } 330d38ceaf9SAlex Deucher 331d38ceaf9SAlex Deucher static struct drm_info_list amdgpu_debugfs_sa_list[] = { 332d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 333d38ceaf9SAlex Deucher }; 334d38ceaf9SAlex Deucher 335d38ceaf9SAlex Deucher #endif 336d38ceaf9SAlex Deucher 337d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 338d38ceaf9SAlex Deucher { 339d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 340d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 341d38ceaf9SAlex Deucher #else 342d38ceaf9SAlex Deucher return 0; 343d38ceaf9SAlex Deucher #endif 344d38ceaf9SAlex Deucher } 345