1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher 36bb7ad55bSChunming Zhou #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 37bbec97aaSChristian König 38d38ceaf9SAlex Deucher /* 39d38ceaf9SAlex Deucher * IB 40d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 41d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 42d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 43d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 44d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 45d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 46d38ceaf9SAlex Deucher */ 47d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 48d38ceaf9SAlex Deucher 49d38ceaf9SAlex Deucher /** 50d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 51d38ceaf9SAlex Deucher * 52d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 53d38ceaf9SAlex Deucher * @size: requested IB size 54d38ceaf9SAlex Deucher * @ib: IB object returned 55d38ceaf9SAlex Deucher * 56d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 57d38ceaf9SAlex Deucher * suballocator. 58d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 59d38ceaf9SAlex Deucher */ 60b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 61d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 62d38ceaf9SAlex Deucher { 63d38ceaf9SAlex Deucher int r; 64d38ceaf9SAlex Deucher 65d38ceaf9SAlex Deucher if (size) { 66bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 67d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 68d38ceaf9SAlex Deucher if (r) { 69d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 70d38ceaf9SAlex Deucher return r; 71d38ceaf9SAlex Deucher } 72d38ceaf9SAlex Deucher 73d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 74d38ceaf9SAlex Deucher 75d38ceaf9SAlex Deucher if (!vm) 76d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 77d38ceaf9SAlex Deucher } 78d38ceaf9SAlex Deucher 79d38ceaf9SAlex Deucher return 0; 80d38ceaf9SAlex Deucher } 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher /** 83d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 84d38ceaf9SAlex Deucher * 85d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 86d38ceaf9SAlex Deucher * @ib: IB object to free 87cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 88d38ceaf9SAlex Deucher * 89d38ceaf9SAlex Deucher * Free an IB (all asics). 90d38ceaf9SAlex Deucher */ 914d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 92f54d1867SChris Wilson struct dma_fence *f) 93d38ceaf9SAlex Deucher { 94cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95d38ceaf9SAlex Deucher } 96d38ceaf9SAlex Deucher 97d38ceaf9SAlex Deucher /** 98d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99d38ceaf9SAlex Deucher * 100d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 101d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 102d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 103ec72b800SChristian König * @f: fence created during this submission 104d38ceaf9SAlex Deucher * 105d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 106d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 107d38ceaf9SAlex Deucher * 108d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 109d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 110d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 111d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 112d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 113d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 114d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 115d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116d38ceaf9SAlex Deucher * to SI there was just a DE IB. 117d38ceaf9SAlex Deucher */ 118b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 11950ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 12050ddc75eSJunwei Zhang struct dma_fence **f) 121d38ceaf9SAlex Deucher { 122b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 123d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 124b9bf33d5SChunming Zhou struct dma_fence *tmp = NULL; 125f153d286SChristian König bool skip_preamble, need_ctx_switch; 12692f25098SChristian König unsigned patch_offset = ~0; 12792f25098SChristian König struct amdgpu_vm *vm; 1283aecd24cSMonk Liu uint64_t fence_ctx; 1299a9db6efSAlex Deucher uint32_t status = 0, alloc_size; 130d240cd9eSMarek Olšák unsigned fence_flags = 0; 13103ccf481SMonk Liu 13292f25098SChristian König unsigned i; 133d38ceaf9SAlex Deucher int r = 0; 1348fdf074fSMonk Liu bool need_pipe_sync = false; 135d38ceaf9SAlex Deucher 136d38ceaf9SAlex Deucher if (num_ibs == 0) 137d38ceaf9SAlex Deucher return -EINVAL; 138d38ceaf9SAlex Deucher 13992f25098SChristian König /* ring tests don't use a job */ 14092f25098SChristian König if (job) { 141c5637837SMonk Liu vm = job->vm; 1423aecd24cSMonk Liu fence_ctx = job->fence_ctx; 14392f25098SChristian König } else { 14492f25098SChristian König vm = NULL; 1453aecd24cSMonk Liu fence_ctx = 0; 14692f25098SChristian König } 147d919ad49SChristian König 148d38ceaf9SAlex Deucher if (!ring->ready) { 1491b583649STom St Denis dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 150d38ceaf9SAlex Deucher return -EINVAL; 151d38ceaf9SAlex Deucher } 152be86c606SChunming Zhou 153c4f46f22SChristian König if (vm && !job->vmid) { 1548d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1558d0a7ceaSChristian König return -EINVAL; 1568d0a7ceaSChristian König } 1578d0a7ceaSChristian König 158e12f3d7aSChristian König alloc_size = ring->funcs->emit_frame_size + num_ibs * 159e12f3d7aSChristian König ring->funcs->emit_ib_size; 1609a9db6efSAlex Deucher 1619a9db6efSAlex Deucher r = amdgpu_ring_alloc(ring, alloc_size); 162d38ceaf9SAlex Deucher if (r) { 163d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 164d38ceaf9SAlex Deucher return r; 165d38ceaf9SAlex Deucher } 166df83d1ebSChunming Zhou 167df83d1ebSChunming Zhou if (ring->funcs->emit_pipeline_sync && job && 168cebb52b7SAndrey Grodzovsky ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 169b9bf33d5SChunming Zhou amdgpu_vm_need_pipeline_sync(ring, job))) { 1708fdf074fSMonk Liu need_pipe_sync = true; 171df83d1ebSChunming Zhou dma_fence_put(tmp); 172df83d1ebSChunming Zhou } 173d38ceaf9SAlex Deucher 174ef44f854SLeo Liu if (ring->funcs->insert_start) 175ef44f854SLeo Liu ring->funcs->insert_start(ring); 176ef44f854SLeo Liu 177df264f9eSChristian König if (job) { 1788fdf074fSMonk Liu r = amdgpu_vm_flush(ring, job, need_pipe_sync); 17941d9eb2cSChristian König if (r) { 18041d9eb2cSChristian König amdgpu_ring_undo(ring); 18141d9eb2cSChristian König return r; 18241d9eb2cSChristian König } 183794ff571SMonk Liu } 184d38ceaf9SAlex Deucher 185113890eeSMonk Liu if (job && ring->funcs->init_cond_exec) 186e9d672b2SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 187e9d672b2SMonk Liu 188c5cb934eSChristian König #ifdef CONFIG_X86_64 1891b9d17dbSChristian König if (!(adev->flags & AMD_IS_APU)) 190c5cb934eSChristian König #endif 1911b9d17dbSChristian König { 1921b9d17dbSChristian König if (ring->funcs->emit_hdp_flush) 193d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 1941b9d17dbSChristian König else 1951b9d17dbSChristian König amdgpu_asic_flush_hdp(adev, ring); 1961b9d17dbSChristian König } 197d2edb07bSChristian König 1983aecd24cSMonk Liu skip_preamble = ring->current_ctx == fence_ctx; 1993aecd24cSMonk Liu need_ctx_switch = ring->current_ctx != fence_ctx; 200753ad49cSMonk Liu if (job && ring->funcs->emit_cntxcntl) { 201753ad49cSMonk Liu if (need_ctx_switch) 202753ad49cSMonk Liu status |= AMDGPU_HAVE_CTX_SWITCH; 203753ad49cSMonk Liu status |= job->preamble_status; 2047e6bf80fSMonk Liu 205753ad49cSMonk Liu amdgpu_ring_emit_cntxcntl(ring, status); 206753ad49cSMonk Liu } 207753ad49cSMonk Liu 208d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 209f153d286SChristian König ib = &ibs[i]; 2109f8fb5a2SChristian König 2119f8fb5a2SChristian König /* drop preamble IBs if we don't have a context switch */ 212753ad49cSMonk Liu if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 213753ad49cSMonk Liu skip_preamble && 21479bbbf8bSMonk Liu !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 21579bbbf8bSMonk Liu !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 2169f8fb5a2SChristian König continue; 2179f8fb5a2SChristian König 218c4f46f22SChristian König amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0, 219d88bf583SChristian König need_ctx_switch); 220f153d286SChristian König need_ctx_switch = false; 221d38ceaf9SAlex Deucher } 222d38ceaf9SAlex Deucher 2233b4d68e9SMonk Liu if (ring->funcs->emit_tmz) 2243b4d68e9SMonk Liu amdgpu_ring_emit_tmz(ring, false); 2253b4d68e9SMonk Liu 226c5cb934eSChristian König #ifdef CONFIG_X86_64 2271b9d17dbSChristian König if (!(adev->flags & AMD_IS_APU)) 228c5cb934eSChristian König #endif 2291b9d17dbSChristian König amdgpu_asic_invalidate_hdp(adev, ring); 23011afbde8SChunming Zhou 231d240cd9eSMarek Olšák if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 232d240cd9eSMarek Olšák fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 233d240cd9eSMarek Olšák 234d240cd9eSMarek Olšák r = amdgpu_fence_emit(ring, f, fence_flags); 235d38ceaf9SAlex Deucher if (r) { 236d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 237c4f46f22SChristian König if (job && job->vmid) 238c4f46f22SChristian König amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 239a27de35cSChristian König amdgpu_ring_undo(ring); 240d38ceaf9SAlex Deucher return r; 241d38ceaf9SAlex Deucher } 242d38ceaf9SAlex Deucher 243135d4735SLeo Liu if (ring->funcs->insert_end) 244135d4735SLeo Liu ring->funcs->insert_end(ring); 245135d4735SLeo Liu 246d38ceaf9SAlex Deucher /* wrap the last IB with fence */ 247b5f5acbcSChristian König if (job && job->uf_addr) { 248b5f5acbcSChristian König amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 249d240cd9eSMarek Olšák fence_flags | AMDGPU_FENCE_FLAG_64BIT); 250d38ceaf9SAlex Deucher } 251d38ceaf9SAlex Deucher 25203ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 25303ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 25403ccf481SMonk Liu 2553aecd24cSMonk Liu ring->current_ctx = fence_ctx; 256bc1e59b2SMonk Liu if (vm && ring->funcs->emit_switch_buffer) 257c2167a65SMonk Liu amdgpu_ring_emit_switch_buffer(ring); 258a27de35cSChristian König amdgpu_ring_commit(ring); 259d38ceaf9SAlex Deucher return 0; 260d38ceaf9SAlex Deucher } 261d38ceaf9SAlex Deucher 262d38ceaf9SAlex Deucher /** 263d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 264d38ceaf9SAlex Deucher * 265d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 266d38ceaf9SAlex Deucher * 267d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 268d38ceaf9SAlex Deucher * for use as IBs (all asics). 269d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 270d38ceaf9SAlex Deucher */ 271d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 272d38ceaf9SAlex Deucher { 273d38ceaf9SAlex Deucher int r; 274d38ceaf9SAlex Deucher 275d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 276d38ceaf9SAlex Deucher return 0; 277d38ceaf9SAlex Deucher } 278d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 279d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 280d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 281d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 282d38ceaf9SAlex Deucher if (r) { 283d38ceaf9SAlex Deucher return r; 284d38ceaf9SAlex Deucher } 285d38ceaf9SAlex Deucher 286d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 287d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 288d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 289d38ceaf9SAlex Deucher } 290d38ceaf9SAlex Deucher return 0; 291d38ceaf9SAlex Deucher } 292d38ceaf9SAlex Deucher 293d38ceaf9SAlex Deucher /** 294d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 295d38ceaf9SAlex Deucher * 296d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 297d38ceaf9SAlex Deucher * 298d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 299d38ceaf9SAlex Deucher * for use as IBs (all asics). 300d38ceaf9SAlex Deucher */ 301d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 302d38ceaf9SAlex Deucher { 303d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 304d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 305d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 306d38ceaf9SAlex Deucher } 307d38ceaf9SAlex Deucher } 308d38ceaf9SAlex Deucher 309d38ceaf9SAlex Deucher /** 310d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 311d38ceaf9SAlex Deucher * 312d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 313d38ceaf9SAlex Deucher * 314d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 315d38ceaf9SAlex Deucher * If the test fails, disable the ring. 316d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 317d38ceaf9SAlex Deucher * IB test fails. 318d38ceaf9SAlex Deucher */ 319d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 320d38ceaf9SAlex Deucher { 321d38ceaf9SAlex Deucher unsigned i; 3221f703e66SChunming Zhou int r, ret = 0; 323dbf79765SMonk Liu long tmo_gfx, tmo_mm; 324dbf79765SMonk Liu 325dbf79765SMonk Liu tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 326dbf79765SMonk Liu if (amdgpu_sriov_vf(adev)) { 327dbf79765SMonk Liu /* for MM engines in hypervisor side they are not scheduled together 328dbf79765SMonk Liu * with CP and SDMA engines, so even in exclusive mode MM engine could 329dbf79765SMonk Liu * still running on other VF thus the IB TEST TIMEOUT for MM engines 330dbf79765SMonk Liu * under SR-IOV should be set to a long time. 8 sec should be enough 331dbf79765SMonk Liu * for the MM comes back to this VF. 332dbf79765SMonk Liu */ 333dbf79765SMonk Liu tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 334dbf79765SMonk Liu } 335dbf79765SMonk Liu 336dbf79765SMonk Liu if (amdgpu_sriov_runtime(adev)) { 337dbf79765SMonk Liu /* for CP & SDMA engines since they are scheduled together so 338dbf79765SMonk Liu * need to make the timeout width enough to cover the time 339dbf79765SMonk Liu * cost waiting for it coming back under RUNTIME only 340dbf79765SMonk Liu */ 341dbf79765SMonk Liu tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 342dbf79765SMonk Liu } 343d38ceaf9SAlex Deucher 344d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 345d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 346dbf79765SMonk Liu long tmo; 347d38ceaf9SAlex Deucher 348d38ceaf9SAlex Deucher if (!ring || !ring->ready) 349d38ceaf9SAlex Deucher continue; 350d38ceaf9SAlex Deucher 351dbf79765SMonk Liu /* MM engine need more time */ 352dbf79765SMonk Liu if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 353dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_VCE || 354dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 355dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 3565b2329b6SBoyuan Zhang ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 3575b2329b6SBoyuan Zhang ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 358dbf79765SMonk Liu tmo = tmo_mm; 359dbf79765SMonk Liu else 360dbf79765SMonk Liu tmo = tmo_gfx; 361dbf79765SMonk Liu 362dbf79765SMonk Liu r = amdgpu_ring_test_ib(ring, tmo); 363d38ceaf9SAlex Deucher if (r) { 364d38ceaf9SAlex Deucher ring->ready = false; 365d38ceaf9SAlex Deucher 366d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 367d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 368d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 369d38ceaf9SAlex Deucher adev->accel_working = false; 370d38ceaf9SAlex Deucher return r; 371d38ceaf9SAlex Deucher 372d38ceaf9SAlex Deucher } else { 373d38ceaf9SAlex Deucher /* still not good, but we can live with it */ 374d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 3751f703e66SChunming Zhou ret = r; 376d38ceaf9SAlex Deucher } 377d38ceaf9SAlex Deucher } 378d38ceaf9SAlex Deucher } 3791f703e66SChunming Zhou return ret; 380d38ceaf9SAlex Deucher } 381d38ceaf9SAlex Deucher 382d38ceaf9SAlex Deucher /* 383d38ceaf9SAlex Deucher * Debugfs info 384d38ceaf9SAlex Deucher */ 385d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 386d38ceaf9SAlex Deucher 387d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 388d38ceaf9SAlex Deucher { 389d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 390d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 391d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 392d38ceaf9SAlex Deucher 393d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 394d38ceaf9SAlex Deucher 395d38ceaf9SAlex Deucher return 0; 396d38ceaf9SAlex Deucher 397d38ceaf9SAlex Deucher } 398d38ceaf9SAlex Deucher 39906ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 400d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 401d38ceaf9SAlex Deucher }; 402d38ceaf9SAlex Deucher 403d38ceaf9SAlex Deucher #endif 404d38ceaf9SAlex Deucher 405d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 406d38ceaf9SAlex Deucher { 407d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 408d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 409d38ceaf9SAlex Deucher #else 410d38ceaf9SAlex Deucher return 0; 411d38ceaf9SAlex Deucher #endif 412d38ceaf9SAlex Deucher } 413