1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher 36d38ceaf9SAlex Deucher /* 37d38ceaf9SAlex Deucher * IB 38d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 39d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 40d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 41d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 42d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 43d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 44d38ceaf9SAlex Deucher */ 45d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 46d38ceaf9SAlex Deucher 47d38ceaf9SAlex Deucher /** 48d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 49d38ceaf9SAlex Deucher * 50d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 51d38ceaf9SAlex Deucher * @size: requested IB size 52d38ceaf9SAlex Deucher * @ib: IB object returned 53d38ceaf9SAlex Deucher * 54d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 55d38ceaf9SAlex Deucher * suballocator. 56d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 57d38ceaf9SAlex Deucher */ 58b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 59d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 60d38ceaf9SAlex Deucher { 61d38ceaf9SAlex Deucher int r; 62d38ceaf9SAlex Deucher 63d38ceaf9SAlex Deucher if (size) { 64bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 65d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 66d38ceaf9SAlex Deucher if (r) { 67d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 68d38ceaf9SAlex Deucher return r; 69d38ceaf9SAlex Deucher } 70d38ceaf9SAlex Deucher 71d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 72d38ceaf9SAlex Deucher 73d38ceaf9SAlex Deucher if (!vm) 74d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 75d38ceaf9SAlex Deucher } 76d38ceaf9SAlex Deucher 774ff37a83SChristian König ib->vm_id = 0; 78d38ceaf9SAlex Deucher 79d38ceaf9SAlex Deucher return 0; 80d38ceaf9SAlex Deucher } 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher /** 83d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 84d38ceaf9SAlex Deucher * 85d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 86d38ceaf9SAlex Deucher * @ib: IB object to free 87cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 88d38ceaf9SAlex Deucher * 89d38ceaf9SAlex Deucher * Free an IB (all asics). 90d38ceaf9SAlex Deucher */ 914d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 924d9c514dSChristian König struct fence *f) 93d38ceaf9SAlex Deucher { 94cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95d38ceaf9SAlex Deucher } 96d38ceaf9SAlex Deucher 97d38ceaf9SAlex Deucher /** 98d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99d38ceaf9SAlex Deucher * 100d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 101d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 102d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 103ec72b800SChristian König * @f: fence created during this submission 104d38ceaf9SAlex Deucher * 105d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 106d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 107d38ceaf9SAlex Deucher * 108d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 109d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 110d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 111d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 112d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 113d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 114d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 115d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116d38ceaf9SAlex Deucher * to SI there was just a DE IB. 117d38ceaf9SAlex Deucher */ 118b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 119336d1f5eSChristian König struct amdgpu_ib *ibs, struct fence *last_vm_update, 120c5637837SMonk Liu struct amdgpu_job *job, struct fence **f) 121d38ceaf9SAlex Deucher { 122b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 123d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 1243cb485f3SChristian König struct amdgpu_ctx *ctx, *old_ctx; 12573cfa5f5SMonk Liu struct fence *hwf; 126c5637837SMonk Liu struct amdgpu_vm *vm = NULL; 12703ccf481SMonk Liu unsigned i, patch_offset = ~0; 12803ccf481SMonk Liu 129d38ceaf9SAlex Deucher int r = 0; 130d38ceaf9SAlex Deucher 131d38ceaf9SAlex Deucher if (num_ibs == 0) 132d38ceaf9SAlex Deucher return -EINVAL; 133d38ceaf9SAlex Deucher 1343cb485f3SChristian König ctx = ibs->ctx; 135c5637837SMonk Liu if (job) /* for domain0 job like ring test, ibs->job is not assigned */ 136c5637837SMonk Liu vm = job->vm; 137d919ad49SChristian König 138d38ceaf9SAlex Deucher if (!ring->ready) { 139d38ceaf9SAlex Deucher dev_err(adev->dev, "couldn't schedule ib\n"); 140d38ceaf9SAlex Deucher return -EINVAL; 141d38ceaf9SAlex Deucher } 142be86c606SChunming Zhou 1434ff37a83SChristian König if (vm && !ibs->vm_id) { 1448d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1458d0a7ceaSChristian König return -EINVAL; 1468d0a7ceaSChristian König } 1478d0a7ceaSChristian König 148867d0517SChristian König r = amdgpu_ring_alloc(ring, 256 * num_ibs); 149d38ceaf9SAlex Deucher if (r) { 150d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 151d38ceaf9SAlex Deucher return r; 152d38ceaf9SAlex Deucher } 153d38ceaf9SAlex Deucher 15403ccf481SMonk Liu if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec) 15503ccf481SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 15603ccf481SMonk Liu 157d38ceaf9SAlex Deucher if (vm) { 158d38ceaf9SAlex Deucher /* do context switch */ 15941d9eb2cSChristian König r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr, 160d38ceaf9SAlex Deucher ib->gds_base, ib->gds_size, 161d38ceaf9SAlex Deucher ib->gws_base, ib->gws_size, 162d38ceaf9SAlex Deucher ib->oa_base, ib->oa_size); 16341d9eb2cSChristian König if (r) { 16441d9eb2cSChristian König amdgpu_ring_undo(ring); 16541d9eb2cSChristian König return r; 16641d9eb2cSChristian König } 167794ff571SMonk Liu } 168d38ceaf9SAlex Deucher 169d2edb07bSChristian König if (ring->funcs->emit_hdp_flush) 170d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 171d2edb07bSChristian König 172128cff1aSMonk Liu /* always set cond_exec_polling to CONTINUE */ 173128cff1aSMonk Liu *ring->cond_exe_cpu_addr = 1; 174128cff1aSMonk Liu 1753cb485f3SChristian König old_ctx = ring->current_ctx; 176d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 177d38ceaf9SAlex Deucher ib = &ibs[i]; 178d38ceaf9SAlex Deucher amdgpu_ring_emit_ib(ring, ib); 1793cb485f3SChristian König ring->current_ctx = ctx; 180d38ceaf9SAlex Deucher } 181d38ceaf9SAlex Deucher 18211afbde8SChunming Zhou if (ring->funcs->emit_hdp_invalidate) 18311afbde8SChunming Zhou amdgpu_ring_emit_hdp_invalidate(ring); 18411afbde8SChunming Zhou 18573cfa5f5SMonk Liu r = amdgpu_fence_emit(ring, &hwf); 186d38ceaf9SAlex Deucher if (r) { 187d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 1883cb485f3SChristian König ring->current_ctx = old_ctx; 189971fe9a9SChristian König if (ib->vm_id) 190971fe9a9SChristian König amdgpu_vm_reset_id(adev, ib->vm_id); 191a27de35cSChristian König amdgpu_ring_undo(ring); 192d38ceaf9SAlex Deucher return r; 193d38ceaf9SAlex Deucher } 194d38ceaf9SAlex Deucher 195d38ceaf9SAlex Deucher /* wrap the last IB with fence */ 196d38ceaf9SAlex Deucher if (ib->user) { 197d38ceaf9SAlex Deucher uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 198d38ceaf9SAlex Deucher addr += ib->user->offset; 1995430a3ffSChristian König amdgpu_ring_emit_fence(ring, addr, ib->sequence, 200890ee23fSChunming Zhou AMDGPU_FENCE_FLAG_64BIT); 201d38ceaf9SAlex Deucher } 202d38ceaf9SAlex Deucher 203ec72b800SChristian König if (f) 20473cfa5f5SMonk Liu *f = fence_get(hwf); 205ec72b800SChristian König 20603ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 20703ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 20803ccf481SMonk Liu 209a27de35cSChristian König amdgpu_ring_commit(ring); 210d38ceaf9SAlex Deucher return 0; 211d38ceaf9SAlex Deucher } 212d38ceaf9SAlex Deucher 213d38ceaf9SAlex Deucher /** 214d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 215d38ceaf9SAlex Deucher * 216d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 217d38ceaf9SAlex Deucher * 218d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 219d38ceaf9SAlex Deucher * for use as IBs (all asics). 220d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 221d38ceaf9SAlex Deucher */ 222d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 223d38ceaf9SAlex Deucher { 224d38ceaf9SAlex Deucher int r; 225d38ceaf9SAlex Deucher 226d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 227d38ceaf9SAlex Deucher return 0; 228d38ceaf9SAlex Deucher } 229d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 230d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 231d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 232d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 233d38ceaf9SAlex Deucher if (r) { 234d38ceaf9SAlex Deucher return r; 235d38ceaf9SAlex Deucher } 236d38ceaf9SAlex Deucher 237d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 238d38ceaf9SAlex Deucher if (r) { 239d38ceaf9SAlex Deucher return r; 240d38ceaf9SAlex Deucher } 241d38ceaf9SAlex Deucher 242d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 243d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 244d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 245d38ceaf9SAlex Deucher } 246d38ceaf9SAlex Deucher return 0; 247d38ceaf9SAlex Deucher } 248d38ceaf9SAlex Deucher 249d38ceaf9SAlex Deucher /** 250d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 251d38ceaf9SAlex Deucher * 252d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 253d38ceaf9SAlex Deucher * 254d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 255d38ceaf9SAlex Deucher * for use as IBs (all asics). 256d38ceaf9SAlex Deucher */ 257d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 258d38ceaf9SAlex Deucher { 259d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 260d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 261d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 262d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 263d38ceaf9SAlex Deucher } 264d38ceaf9SAlex Deucher } 265d38ceaf9SAlex Deucher 266d38ceaf9SAlex Deucher /** 267d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 268d38ceaf9SAlex Deucher * 269d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 270d38ceaf9SAlex Deucher * 271d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 272d38ceaf9SAlex Deucher * If the test fails, disable the ring. 273d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 274d38ceaf9SAlex Deucher * IB test fails. 275d38ceaf9SAlex Deucher */ 276d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 277d38ceaf9SAlex Deucher { 278d38ceaf9SAlex Deucher unsigned i; 279d38ceaf9SAlex Deucher int r; 280d38ceaf9SAlex Deucher 281d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 282d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 283d38ceaf9SAlex Deucher 284d38ceaf9SAlex Deucher if (!ring || !ring->ready) 285d38ceaf9SAlex Deucher continue; 286d38ceaf9SAlex Deucher 287d38ceaf9SAlex Deucher r = amdgpu_ring_test_ib(ring); 288d38ceaf9SAlex Deucher if (r) { 289d38ceaf9SAlex Deucher ring->ready = false; 290d38ceaf9SAlex Deucher 291d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 292d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 293d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 294d38ceaf9SAlex Deucher adev->accel_working = false; 295d38ceaf9SAlex Deucher return r; 296d38ceaf9SAlex Deucher 297d38ceaf9SAlex Deucher } else { 298d38ceaf9SAlex Deucher /* still not good, but we can live with it */ 299d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 300d38ceaf9SAlex Deucher } 301d38ceaf9SAlex Deucher } 302d38ceaf9SAlex Deucher } 303d38ceaf9SAlex Deucher return 0; 304d38ceaf9SAlex Deucher } 305d38ceaf9SAlex Deucher 306d38ceaf9SAlex Deucher /* 307d38ceaf9SAlex Deucher * Debugfs info 308d38ceaf9SAlex Deucher */ 309d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 310d38ceaf9SAlex Deucher 311d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 312d38ceaf9SAlex Deucher { 313d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 314d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 315d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 316d38ceaf9SAlex Deucher 317d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 318d38ceaf9SAlex Deucher 319d38ceaf9SAlex Deucher return 0; 320d38ceaf9SAlex Deucher 321d38ceaf9SAlex Deucher } 322d38ceaf9SAlex Deucher 32306ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 324d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 325d38ceaf9SAlex Deucher }; 326d38ceaf9SAlex Deucher 327d38ceaf9SAlex Deucher #endif 328d38ceaf9SAlex Deucher 329d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 330d38ceaf9SAlex Deucher { 331d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 332d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 333d38ceaf9SAlex Deucher #else 334d38ceaf9SAlex Deucher return 0; 335d38ceaf9SAlex Deucher #endif 336d38ceaf9SAlex Deucher } 337