1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher 36bb7ad55bSChunming Zhou #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 37bbec97aaSChristian König 38d38ceaf9SAlex Deucher /* 39d38ceaf9SAlex Deucher * IB 40d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 41d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 42d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 43d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 44d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 45d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 46d38ceaf9SAlex Deucher */ 47d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 48d38ceaf9SAlex Deucher 49d38ceaf9SAlex Deucher /** 50d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 51d38ceaf9SAlex Deucher * 52d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 53d38ceaf9SAlex Deucher * @size: requested IB size 54d38ceaf9SAlex Deucher * @ib: IB object returned 55d38ceaf9SAlex Deucher * 56d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 57d38ceaf9SAlex Deucher * suballocator. 58d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 59d38ceaf9SAlex Deucher */ 60b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 61d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 62d38ceaf9SAlex Deucher { 63d38ceaf9SAlex Deucher int r; 64d38ceaf9SAlex Deucher 65d38ceaf9SAlex Deucher if (size) { 66bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 67d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 68d38ceaf9SAlex Deucher if (r) { 69d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 70d38ceaf9SAlex Deucher return r; 71d38ceaf9SAlex Deucher } 72d38ceaf9SAlex Deucher 73d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 74d38ceaf9SAlex Deucher 75d38ceaf9SAlex Deucher if (!vm) 76d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 77d38ceaf9SAlex Deucher } 78d38ceaf9SAlex Deucher 79d38ceaf9SAlex Deucher return 0; 80d38ceaf9SAlex Deucher } 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher /** 83d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 84d38ceaf9SAlex Deucher * 85d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 86d38ceaf9SAlex Deucher * @ib: IB object to free 87cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 88d38ceaf9SAlex Deucher * 89d38ceaf9SAlex Deucher * Free an IB (all asics). 90d38ceaf9SAlex Deucher */ 914d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 924d9c514dSChristian König struct fence *f) 93d38ceaf9SAlex Deucher { 94cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 95d38ceaf9SAlex Deucher } 96d38ceaf9SAlex Deucher 97d38ceaf9SAlex Deucher /** 98d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 99d38ceaf9SAlex Deucher * 100d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 101d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 102d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 103ec72b800SChristian König * @f: fence created during this submission 104d38ceaf9SAlex Deucher * 105d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 106d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 107d38ceaf9SAlex Deucher * 108d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 109d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 110d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 111d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 112d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 113d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 114d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 115d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 116d38ceaf9SAlex Deucher * to SI there was just a DE IB. 117d38ceaf9SAlex Deucher */ 118b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 119336d1f5eSChristian König struct amdgpu_ib *ibs, struct fence *last_vm_update, 120c5637837SMonk Liu struct amdgpu_job *job, struct fence **f) 121d38ceaf9SAlex Deucher { 122b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 123d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 124f153d286SChristian König bool skip_preamble, need_ctx_switch; 12592f25098SChristian König unsigned patch_offset = ~0; 12692f25098SChristian König struct amdgpu_vm *vm; 1273aecd24cSMonk Liu uint64_t fence_ctx; 12803ccf481SMonk Liu 12992f25098SChristian König unsigned i; 130d38ceaf9SAlex Deucher int r = 0; 131d38ceaf9SAlex Deucher 132d38ceaf9SAlex Deucher if (num_ibs == 0) 133d38ceaf9SAlex Deucher return -EINVAL; 134d38ceaf9SAlex Deucher 13592f25098SChristian König /* ring tests don't use a job */ 13692f25098SChristian König if (job) { 137c5637837SMonk Liu vm = job->vm; 1383aecd24cSMonk Liu fence_ctx = job->fence_ctx; 13992f25098SChristian König } else { 14092f25098SChristian König vm = NULL; 1413aecd24cSMonk Liu fence_ctx = 0; 14292f25098SChristian König } 143d919ad49SChristian König 144d38ceaf9SAlex Deucher if (!ring->ready) { 1451b583649STom St Denis dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 146d38ceaf9SAlex Deucher return -EINVAL; 147d38ceaf9SAlex Deucher } 148be86c606SChunming Zhou 149d88bf583SChristian König if (vm && !job->vm_id) { 1508d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1518d0a7ceaSChristian König return -EINVAL; 1528d0a7ceaSChristian König } 1538d0a7ceaSChristian König 154867d0517SChristian König r = amdgpu_ring_alloc(ring, 256 * num_ibs); 155d38ceaf9SAlex Deucher if (r) { 156d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 157d38ceaf9SAlex Deucher return r; 158d38ceaf9SAlex Deucher } 159d38ceaf9SAlex Deucher 16003ccf481SMonk Liu if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec) 16103ccf481SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 16203ccf481SMonk Liu 163d38ceaf9SAlex Deucher if (vm) { 164fd53be30SChunming Zhou r = amdgpu_vm_flush(ring, job); 16541d9eb2cSChristian König if (r) { 16641d9eb2cSChristian König amdgpu_ring_undo(ring); 16741d9eb2cSChristian König return r; 16841d9eb2cSChristian König } 169794ff571SMonk Liu } 170d38ceaf9SAlex Deucher 171d2edb07bSChristian König if (ring->funcs->emit_hdp_flush) 172d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 173d2edb07bSChristian König 174128cff1aSMonk Liu /* always set cond_exec_polling to CONTINUE */ 175128cff1aSMonk Liu *ring->cond_exe_cpu_addr = 1; 176128cff1aSMonk Liu 1773aecd24cSMonk Liu skip_preamble = ring->current_ctx == fence_ctx; 1783aecd24cSMonk Liu need_ctx_switch = ring->current_ctx != fence_ctx; 179d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 180f153d286SChristian König ib = &ibs[i]; 1819f8fb5a2SChristian König 1829f8fb5a2SChristian König /* drop preamble IBs if we don't have a context switch */ 1839f8fb5a2SChristian König if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) 1849f8fb5a2SChristian König continue; 1859f8fb5a2SChristian König 186d88bf583SChristian König amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 187d88bf583SChristian König need_ctx_switch); 188f153d286SChristian König need_ctx_switch = false; 189d38ceaf9SAlex Deucher } 190d38ceaf9SAlex Deucher 19111afbde8SChunming Zhou if (ring->funcs->emit_hdp_invalidate) 19211afbde8SChunming Zhou amdgpu_ring_emit_hdp_invalidate(ring); 19311afbde8SChunming Zhou 19422a77cf6SChristian König r = amdgpu_fence_emit(ring, f); 195d38ceaf9SAlex Deucher if (r) { 196d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 197d88bf583SChristian König if (job && job->vm_id) 198d88bf583SChristian König amdgpu_vm_reset_id(adev, job->vm_id); 199a27de35cSChristian König amdgpu_ring_undo(ring); 200d38ceaf9SAlex Deucher return r; 201d38ceaf9SAlex Deucher } 202d38ceaf9SAlex Deucher 203d38ceaf9SAlex Deucher /* wrap the last IB with fence */ 204b5f5acbcSChristian König if (job && job->uf_addr) { 205b5f5acbcSChristian König amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 206890ee23fSChunming Zhou AMDGPU_FENCE_FLAG_64BIT); 207d38ceaf9SAlex Deucher } 208d38ceaf9SAlex Deucher 20903ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 21003ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 21103ccf481SMonk Liu 2123aecd24cSMonk Liu ring->current_ctx = fence_ctx; 213c2167a65SMonk Liu if (ring->funcs->emit_switch_buffer) 214c2167a65SMonk Liu amdgpu_ring_emit_switch_buffer(ring); 215a27de35cSChristian König amdgpu_ring_commit(ring); 216d38ceaf9SAlex Deucher return 0; 217d38ceaf9SAlex Deucher } 218d38ceaf9SAlex Deucher 219d38ceaf9SAlex Deucher /** 220d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 221d38ceaf9SAlex Deucher * 222d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 223d38ceaf9SAlex Deucher * 224d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 225d38ceaf9SAlex Deucher * for use as IBs (all asics). 226d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 227d38ceaf9SAlex Deucher */ 228d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 229d38ceaf9SAlex Deucher { 230d38ceaf9SAlex Deucher int r; 231d38ceaf9SAlex Deucher 232d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 233d38ceaf9SAlex Deucher return 0; 234d38ceaf9SAlex Deucher } 235d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 236d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 237d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 238d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 239d38ceaf9SAlex Deucher if (r) { 240d38ceaf9SAlex Deucher return r; 241d38ceaf9SAlex Deucher } 242d38ceaf9SAlex Deucher 243d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 244d38ceaf9SAlex Deucher if (r) { 245d38ceaf9SAlex Deucher return r; 246d38ceaf9SAlex Deucher } 247d38ceaf9SAlex Deucher 248d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 249d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 250d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 251d38ceaf9SAlex Deucher } 252d38ceaf9SAlex Deucher return 0; 253d38ceaf9SAlex Deucher } 254d38ceaf9SAlex Deucher 255d38ceaf9SAlex Deucher /** 256d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 257d38ceaf9SAlex Deucher * 258d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 259d38ceaf9SAlex Deucher * 260d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 261d38ceaf9SAlex Deucher * for use as IBs (all asics). 262d38ceaf9SAlex Deucher */ 263d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 264d38ceaf9SAlex Deucher { 265d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 266d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 267d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 268d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 269d38ceaf9SAlex Deucher } 270d38ceaf9SAlex Deucher } 271d38ceaf9SAlex Deucher 272d38ceaf9SAlex Deucher /** 273d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 274d38ceaf9SAlex Deucher * 275d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 276d38ceaf9SAlex Deucher * 277d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 278d38ceaf9SAlex Deucher * If the test fails, disable the ring. 279d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 280d38ceaf9SAlex Deucher * IB test fails. 281d38ceaf9SAlex Deucher */ 282d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 283d38ceaf9SAlex Deucher { 284d38ceaf9SAlex Deucher unsigned i; 285d38ceaf9SAlex Deucher int r; 286d38ceaf9SAlex Deucher 287d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 288d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 289d38ceaf9SAlex Deucher 290d38ceaf9SAlex Deucher if (!ring || !ring->ready) 291d38ceaf9SAlex Deucher continue; 292d38ceaf9SAlex Deucher 293bbec97aaSChristian König r = amdgpu_ring_test_ib(ring, AMDGPU_IB_TEST_TIMEOUT); 294d38ceaf9SAlex Deucher if (r) { 295d38ceaf9SAlex Deucher ring->ready = false; 296d38ceaf9SAlex Deucher 297d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 298d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 299d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 300d38ceaf9SAlex Deucher adev->accel_working = false; 301d38ceaf9SAlex Deucher return r; 302d38ceaf9SAlex Deucher 303d38ceaf9SAlex Deucher } else { 304d38ceaf9SAlex Deucher /* still not good, but we can live with it */ 305d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 306d38ceaf9SAlex Deucher } 307d38ceaf9SAlex Deucher } 308d38ceaf9SAlex Deucher } 309d38ceaf9SAlex Deucher return 0; 310d38ceaf9SAlex Deucher } 311d38ceaf9SAlex Deucher 312d38ceaf9SAlex Deucher /* 313d38ceaf9SAlex Deucher * Debugfs info 314d38ceaf9SAlex Deucher */ 315d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 316d38ceaf9SAlex Deucher 317d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 318d38ceaf9SAlex Deucher { 319d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 320d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 321d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 322d38ceaf9SAlex Deucher 323d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 324d38ceaf9SAlex Deucher 325d38ceaf9SAlex Deucher return 0; 326d38ceaf9SAlex Deucher 327d38ceaf9SAlex Deucher } 328d38ceaf9SAlex Deucher 32906ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 330d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 331d38ceaf9SAlex Deucher }; 332d38ceaf9SAlex Deucher 333d38ceaf9SAlex Deucher #endif 334d38ceaf9SAlex Deucher 335d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 336d38ceaf9SAlex Deucher { 337d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 338d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 339d38ceaf9SAlex Deucher #else 340d38ceaf9SAlex Deucher return 0; 341d38ceaf9SAlex Deucher #endif 342d38ceaf9SAlex Deucher } 343