1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31d38ceaf9SAlex Deucher #include <drm/drmP.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher 36d38ceaf9SAlex Deucher /* 37d38ceaf9SAlex Deucher * IB 38d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 39d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 40d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 41d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 42d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 43d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 44d38ceaf9SAlex Deucher */ 45d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 46d38ceaf9SAlex Deucher 47d38ceaf9SAlex Deucher /** 48d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 49d38ceaf9SAlex Deucher * 50d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 51d38ceaf9SAlex Deucher * @size: requested IB size 52d38ceaf9SAlex Deucher * @ib: IB object returned 53d38ceaf9SAlex Deucher * 54d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 55d38ceaf9SAlex Deucher * suballocator. 56d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 57d38ceaf9SAlex Deucher */ 58b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 59d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 60d38ceaf9SAlex Deucher { 61d38ceaf9SAlex Deucher int r; 62d38ceaf9SAlex Deucher 63d38ceaf9SAlex Deucher if (size) { 64bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 65d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 66d38ceaf9SAlex Deucher if (r) { 67d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 68d38ceaf9SAlex Deucher return r; 69d38ceaf9SAlex Deucher } 70d38ceaf9SAlex Deucher 71d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 72d38ceaf9SAlex Deucher 73d38ceaf9SAlex Deucher if (!vm) 74d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 75d38ceaf9SAlex Deucher } 76d38ceaf9SAlex Deucher 77d38ceaf9SAlex Deucher return 0; 78d38ceaf9SAlex Deucher } 79d38ceaf9SAlex Deucher 80d38ceaf9SAlex Deucher /** 81d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 82d38ceaf9SAlex Deucher * 83d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 84d38ceaf9SAlex Deucher * @ib: IB object to free 85cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 86d38ceaf9SAlex Deucher * 87d38ceaf9SAlex Deucher * Free an IB (all asics). 88d38ceaf9SAlex Deucher */ 894d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 904d9c514dSChristian König struct fence *f) 91d38ceaf9SAlex Deucher { 92cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 93d38ceaf9SAlex Deucher } 94d38ceaf9SAlex Deucher 95d38ceaf9SAlex Deucher /** 96d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 97d38ceaf9SAlex Deucher * 98d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 99d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 100d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 101ec72b800SChristian König * @f: fence created during this submission 102d38ceaf9SAlex Deucher * 103d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 104d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 105d38ceaf9SAlex Deucher * 106d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 107d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 108d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 109d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 110d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 111d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 112d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 113d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 114d38ceaf9SAlex Deucher * to SI there was just a DE IB. 115d38ceaf9SAlex Deucher */ 116b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 117336d1f5eSChristian König struct amdgpu_ib *ibs, struct fence *last_vm_update, 118c5637837SMonk Liu struct amdgpu_job *job, struct fence **f) 119d38ceaf9SAlex Deucher { 120b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 121d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 122f153d286SChristian König bool skip_preamble, need_ctx_switch; 12392f25098SChristian König unsigned patch_offset = ~0; 12492f25098SChristian König struct amdgpu_vm *vm; 12592f25098SChristian König uint64_t ctx; 12603ccf481SMonk Liu 12792f25098SChristian König unsigned i; 128d38ceaf9SAlex Deucher int r = 0; 129d38ceaf9SAlex Deucher 130d38ceaf9SAlex Deucher if (num_ibs == 0) 131d38ceaf9SAlex Deucher return -EINVAL; 132d38ceaf9SAlex Deucher 13392f25098SChristian König /* ring tests don't use a job */ 13492f25098SChristian König if (job) { 135c5637837SMonk Liu vm = job->vm; 13692f25098SChristian König ctx = job->ctx; 13792f25098SChristian König } else { 13892f25098SChristian König vm = NULL; 13992f25098SChristian König ctx = 0; 14092f25098SChristian König } 141d919ad49SChristian König 142d38ceaf9SAlex Deucher if (!ring->ready) { 143d38ceaf9SAlex Deucher dev_err(adev->dev, "couldn't schedule ib\n"); 144d38ceaf9SAlex Deucher return -EINVAL; 145d38ceaf9SAlex Deucher } 146be86c606SChunming Zhou 147d88bf583SChristian König if (vm && !job->vm_id) { 1488d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1498d0a7ceaSChristian König return -EINVAL; 1508d0a7ceaSChristian König } 1518d0a7ceaSChristian König 152867d0517SChristian König r = amdgpu_ring_alloc(ring, 256 * num_ibs); 153d38ceaf9SAlex Deucher if (r) { 154d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 155d38ceaf9SAlex Deucher return r; 156d38ceaf9SAlex Deucher } 157d38ceaf9SAlex Deucher 15803ccf481SMonk Liu if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec) 15903ccf481SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 16003ccf481SMonk Liu 161d38ceaf9SAlex Deucher if (vm) { 162fd53be30SChunming Zhou r = amdgpu_vm_flush(ring, job); 16341d9eb2cSChristian König if (r) { 16441d9eb2cSChristian König amdgpu_ring_undo(ring); 16541d9eb2cSChristian König return r; 16641d9eb2cSChristian König } 167794ff571SMonk Liu } 168d38ceaf9SAlex Deucher 169d2edb07bSChristian König if (ring->funcs->emit_hdp_flush) 170d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 171d2edb07bSChristian König 172128cff1aSMonk Liu /* always set cond_exec_polling to CONTINUE */ 173128cff1aSMonk Liu *ring->cond_exe_cpu_addr = 1; 174128cff1aSMonk Liu 17592f25098SChristian König skip_preamble = ring->current_ctx == ctx; 17692f25098SChristian König need_ctx_switch = ring->current_ctx != ctx; 177d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 178f153d286SChristian König ib = &ibs[i]; 1799f8fb5a2SChristian König 1809f8fb5a2SChristian König /* drop preamble IBs if we don't have a context switch */ 1819f8fb5a2SChristian König if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) 1829f8fb5a2SChristian König continue; 1839f8fb5a2SChristian König 184d88bf583SChristian König amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 185d88bf583SChristian König need_ctx_switch); 186f153d286SChristian König need_ctx_switch = false; 187d38ceaf9SAlex Deucher } 188d38ceaf9SAlex Deucher 18911afbde8SChunming Zhou if (ring->funcs->emit_hdp_invalidate) 19011afbde8SChunming Zhou amdgpu_ring_emit_hdp_invalidate(ring); 19111afbde8SChunming Zhou 19222a77cf6SChristian König r = amdgpu_fence_emit(ring, f); 193d38ceaf9SAlex Deucher if (r) { 194d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 195d88bf583SChristian König if (job && job->vm_id) 196d88bf583SChristian König amdgpu_vm_reset_id(adev, job->vm_id); 197a27de35cSChristian König amdgpu_ring_undo(ring); 198d38ceaf9SAlex Deucher return r; 199d38ceaf9SAlex Deucher } 200d38ceaf9SAlex Deucher 201d38ceaf9SAlex Deucher /* wrap the last IB with fence */ 202b5f5acbcSChristian König if (job && job->uf_addr) { 203b5f5acbcSChristian König amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 204890ee23fSChunming Zhou AMDGPU_FENCE_FLAG_64BIT); 205d38ceaf9SAlex Deucher } 206d38ceaf9SAlex Deucher 20703ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 20803ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 20903ccf481SMonk Liu 21092f25098SChristian König ring->current_ctx = ctx; 211a27de35cSChristian König amdgpu_ring_commit(ring); 212d38ceaf9SAlex Deucher return 0; 213d38ceaf9SAlex Deucher } 214d38ceaf9SAlex Deucher 215d38ceaf9SAlex Deucher /** 216d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 217d38ceaf9SAlex Deucher * 218d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 219d38ceaf9SAlex Deucher * 220d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 221d38ceaf9SAlex Deucher * for use as IBs (all asics). 222d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 223d38ceaf9SAlex Deucher */ 224d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 225d38ceaf9SAlex Deucher { 226d38ceaf9SAlex Deucher int r; 227d38ceaf9SAlex Deucher 228d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 229d38ceaf9SAlex Deucher return 0; 230d38ceaf9SAlex Deucher } 231d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 232d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 233d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 234d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 235d38ceaf9SAlex Deucher if (r) { 236d38ceaf9SAlex Deucher return r; 237d38ceaf9SAlex Deucher } 238d38ceaf9SAlex Deucher 239d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 240d38ceaf9SAlex Deucher if (r) { 241d38ceaf9SAlex Deucher return r; 242d38ceaf9SAlex Deucher } 243d38ceaf9SAlex Deucher 244d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 245d38ceaf9SAlex Deucher if (amdgpu_debugfs_sa_init(adev)) { 246d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to register debugfs file for SA\n"); 247d38ceaf9SAlex Deucher } 248d38ceaf9SAlex Deucher return 0; 249d38ceaf9SAlex Deucher } 250d38ceaf9SAlex Deucher 251d38ceaf9SAlex Deucher /** 252d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 253d38ceaf9SAlex Deucher * 254d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 255d38ceaf9SAlex Deucher * 256d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 257d38ceaf9SAlex Deucher * for use as IBs (all asics). 258d38ceaf9SAlex Deucher */ 259d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 260d38ceaf9SAlex Deucher { 261d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 262d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 263d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 264d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 265d38ceaf9SAlex Deucher } 266d38ceaf9SAlex Deucher } 267d38ceaf9SAlex Deucher 268d38ceaf9SAlex Deucher /** 269d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 270d38ceaf9SAlex Deucher * 271d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 272d38ceaf9SAlex Deucher * 273d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 274d38ceaf9SAlex Deucher * If the test fails, disable the ring. 275d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 276d38ceaf9SAlex Deucher * IB test fails. 277d38ceaf9SAlex Deucher */ 278d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 279d38ceaf9SAlex Deucher { 280d38ceaf9SAlex Deucher unsigned i; 281d38ceaf9SAlex Deucher int r; 282d38ceaf9SAlex Deucher 283d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 284d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 285d38ceaf9SAlex Deucher 286d38ceaf9SAlex Deucher if (!ring || !ring->ready) 287d38ceaf9SAlex Deucher continue; 288d38ceaf9SAlex Deucher 289d38ceaf9SAlex Deucher r = amdgpu_ring_test_ib(ring); 290d38ceaf9SAlex Deucher if (r) { 291d38ceaf9SAlex Deucher ring->ready = false; 292d38ceaf9SAlex Deucher 293d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 294d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 295d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 296d38ceaf9SAlex Deucher adev->accel_working = false; 297d38ceaf9SAlex Deucher return r; 298d38ceaf9SAlex Deucher 299d38ceaf9SAlex Deucher } else { 300d38ceaf9SAlex Deucher /* still not good, but we can live with it */ 301d38ceaf9SAlex Deucher DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 302d38ceaf9SAlex Deucher } 303d38ceaf9SAlex Deucher } 304d38ceaf9SAlex Deucher } 305d38ceaf9SAlex Deucher return 0; 306d38ceaf9SAlex Deucher } 307d38ceaf9SAlex Deucher 308d38ceaf9SAlex Deucher /* 309d38ceaf9SAlex Deucher * Debugfs info 310d38ceaf9SAlex Deucher */ 311d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 312d38ceaf9SAlex Deucher 313d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 314d38ceaf9SAlex Deucher { 315d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 316d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 317d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 318d38ceaf9SAlex Deucher 319d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 320d38ceaf9SAlex Deucher 321d38ceaf9SAlex Deucher return 0; 322d38ceaf9SAlex Deucher 323d38ceaf9SAlex Deucher } 324d38ceaf9SAlex Deucher 32506ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 326d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 327d38ceaf9SAlex Deucher }; 328d38ceaf9SAlex Deucher 329d38ceaf9SAlex Deucher #endif 330d38ceaf9SAlex Deucher 331d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 332d38ceaf9SAlex Deucher { 333d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 334d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 335d38ceaf9SAlex Deucher #else 336d38ceaf9SAlex Deucher return 0; 337d38ceaf9SAlex Deucher #endif 338d38ceaf9SAlex Deucher } 339