1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 5d38ceaf9SAlex Deucher * 6d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 9d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 14d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 15d38ceaf9SAlex Deucher * 16d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 23d38ceaf9SAlex Deucher * 24d38ceaf9SAlex Deucher * Authors: Dave Airlie 25d38ceaf9SAlex Deucher * Alex Deucher 26d38ceaf9SAlex Deucher * Jerome Glisse 27d38ceaf9SAlex Deucher * Christian König 28d38ceaf9SAlex Deucher */ 29d38ceaf9SAlex Deucher #include <linux/seq_file.h> 30d38ceaf9SAlex Deucher #include <linux/slab.h> 31fdf2f6c5SSam Ravnborg 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33fdf2f6c5SSam Ravnborg #include <drm/drm_debugfs.h> 34fdf2f6c5SSam Ravnborg 35d38ceaf9SAlex Deucher #include "amdgpu.h" 36d38ceaf9SAlex Deucher #include "atom.h" 3765f7260bSAndrey Grodzovsky #include "amdgpu_trace.h" 38d38ceaf9SAlex Deucher 39bb7ad55bSChunming Zhou #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000) 40d4162c61Sshaoyunl #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000) 41bbec97aaSChristian König 42d38ceaf9SAlex Deucher /* 43d38ceaf9SAlex Deucher * IB 44d38ceaf9SAlex Deucher * IBs (Indirect Buffers) and areas of GPU accessible memory where 45d38ceaf9SAlex Deucher * commands are stored. You can put a pointer to the IB in the 46d38ceaf9SAlex Deucher * command ring and the hw will fetch the commands from the IB 47d38ceaf9SAlex Deucher * and execute them. Generally userspace acceleration drivers 48d38ceaf9SAlex Deucher * produce command buffers which are send to the kernel and 49d38ceaf9SAlex Deucher * put in IBs for execution by the requested ring. 50d38ceaf9SAlex Deucher */ 51d38ceaf9SAlex Deucher 52d38ceaf9SAlex Deucher /** 53d38ceaf9SAlex Deucher * amdgpu_ib_get - request an IB (Indirect Buffer) 54d38ceaf9SAlex Deucher * 55d38ceaf9SAlex Deucher * @ring: ring index the IB is associated with 56d38ceaf9SAlex Deucher * @size: requested IB size 57d38ceaf9SAlex Deucher * @ib: IB object returned 58d38ceaf9SAlex Deucher * 59d38ceaf9SAlex Deucher * Request an IB (all asics). IBs are allocated using the 60d38ceaf9SAlex Deucher * suballocator. 61d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 62d38ceaf9SAlex Deucher */ 63b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 64d38ceaf9SAlex Deucher unsigned size, struct amdgpu_ib *ib) 65d38ceaf9SAlex Deucher { 66d38ceaf9SAlex Deucher int r; 67d38ceaf9SAlex Deucher 68d38ceaf9SAlex Deucher if (size) { 69bbf0b345SJunwei Zhang r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 70d38ceaf9SAlex Deucher &ib->sa_bo, size, 256); 71d38ceaf9SAlex Deucher if (r) { 72d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 73d38ceaf9SAlex Deucher return r; 74d38ceaf9SAlex Deucher } 75d38ceaf9SAlex Deucher 76d38ceaf9SAlex Deucher ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 77d38ceaf9SAlex Deucher 78d38ceaf9SAlex Deucher if (!vm) 79d38ceaf9SAlex Deucher ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 80d38ceaf9SAlex Deucher } 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher return 0; 83d38ceaf9SAlex Deucher } 84d38ceaf9SAlex Deucher 85d38ceaf9SAlex Deucher /** 86d38ceaf9SAlex Deucher * amdgpu_ib_free - free an IB (Indirect Buffer) 87d38ceaf9SAlex Deucher * 88d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 89d38ceaf9SAlex Deucher * @ib: IB object to free 90cc55c45dSMonk Liu * @f: the fence SA bo need wait on for the ib alloation 91d38ceaf9SAlex Deucher * 92d38ceaf9SAlex Deucher * Free an IB (all asics). 93d38ceaf9SAlex Deucher */ 944d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 95f54d1867SChris Wilson struct dma_fence *f) 96d38ceaf9SAlex Deucher { 97cc55c45dSMonk Liu amdgpu_sa_bo_free(adev, &ib->sa_bo, f); 98d38ceaf9SAlex Deucher } 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher /** 101d38ceaf9SAlex Deucher * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 102d38ceaf9SAlex Deucher * 103d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 104d38ceaf9SAlex Deucher * @num_ibs: number of IBs to schedule 105d38ceaf9SAlex Deucher * @ibs: IB objects to schedule 106ec72b800SChristian König * @f: fence created during this submission 107d38ceaf9SAlex Deucher * 108d38ceaf9SAlex Deucher * Schedule an IB on the associated ring (all asics). 109d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 110d38ceaf9SAlex Deucher * 111d38ceaf9SAlex Deucher * On SI, there are two parallel engines fed from the primary ring, 112d38ceaf9SAlex Deucher * the CE (Constant Engine) and the DE (Drawing Engine). Since 113d38ceaf9SAlex Deucher * resource descriptors have moved to memory, the CE allows you to 114d38ceaf9SAlex Deucher * prime the caches while the DE is updating register state so that 115d38ceaf9SAlex Deucher * the resource descriptors will be already in cache when the draw is 116d38ceaf9SAlex Deucher * processed. To accomplish this, the userspace driver submits two 117d38ceaf9SAlex Deucher * IBs, one for the CE and one for the DE. If there is a CE IB (called 118d38ceaf9SAlex Deucher * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 119d38ceaf9SAlex Deucher * to SI there was just a DE IB. 120d38ceaf9SAlex Deucher */ 121b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 12250ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 12350ddc75eSJunwei Zhang struct dma_fence **f) 124d38ceaf9SAlex Deucher { 125b07c60c0SChristian König struct amdgpu_device *adev = ring->adev; 126d38ceaf9SAlex Deucher struct amdgpu_ib *ib = &ibs[0]; 127b9bf33d5SChunming Zhou struct dma_fence *tmp = NULL; 128f153d286SChristian König bool skip_preamble, need_ctx_switch; 12992f25098SChristian König unsigned patch_offset = ~0; 13092f25098SChristian König struct amdgpu_vm *vm; 1313aecd24cSMonk Liu uint64_t fence_ctx; 1329a9db6efSAlex Deucher uint32_t status = 0, alloc_size; 133d240cd9eSMarek Olšák unsigned fence_flags = 0; 13403ccf481SMonk Liu 13592f25098SChristian König unsigned i; 136d38ceaf9SAlex Deucher int r = 0; 1378fdf074fSMonk Liu bool need_pipe_sync = false; 138d38ceaf9SAlex Deucher 139d38ceaf9SAlex Deucher if (num_ibs == 0) 140d38ceaf9SAlex Deucher return -EINVAL; 141d38ceaf9SAlex Deucher 14292f25098SChristian König /* ring tests don't use a job */ 14392f25098SChristian König if (job) { 144c5637837SMonk Liu vm = job->vm; 145dcafbd50SFelix Kuehling fence_ctx = job->base.s_fence ? 146dcafbd50SFelix Kuehling job->base.s_fence->scheduled.context : 0; 14792f25098SChristian König } else { 14892f25098SChristian König vm = NULL; 1493aecd24cSMonk Liu fence_ctx = 0; 15092f25098SChristian König } 151d919ad49SChristian König 152c66ed765SAndrey Grodzovsky if (!ring->sched.ready) { 1531b583649STom St Denis dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 154d38ceaf9SAlex Deucher return -EINVAL; 155d38ceaf9SAlex Deucher } 156be86c606SChunming Zhou 157c4f46f22SChristian König if (vm && !job->vmid) { 1588d0a7ceaSChristian König dev_err(adev->dev, "VM IB without ID\n"); 1598d0a7ceaSChristian König return -EINVAL; 1608d0a7ceaSChristian König } 1618d0a7ceaSChristian König 162e12f3d7aSChristian König alloc_size = ring->funcs->emit_frame_size + num_ibs * 163e12f3d7aSChristian König ring->funcs->emit_ib_size; 1649a9db6efSAlex Deucher 1659a9db6efSAlex Deucher r = amdgpu_ring_alloc(ring, alloc_size); 166d38ceaf9SAlex Deucher if (r) { 167d38ceaf9SAlex Deucher dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 168d38ceaf9SAlex Deucher return r; 169d38ceaf9SAlex Deucher } 170df83d1ebSChunming Zhou 1714f0ecd36SEmily Deng need_ctx_switch = ring->current_ctx != fence_ctx; 172df83d1ebSChunming Zhou if (ring->funcs->emit_pipeline_sync && job && 173cebb52b7SAndrey Grodzovsky ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || 1744f0ecd36SEmily Deng (amdgpu_sriov_vf(adev) && need_ctx_switch) || 175b9bf33d5SChunming Zhou amdgpu_vm_need_pipeline_sync(ring, job))) { 1768fdf074fSMonk Liu need_pipe_sync = true; 17765f7260bSAndrey Grodzovsky 17865f7260bSAndrey Grodzovsky if (tmp) 17965f7260bSAndrey Grodzovsky trace_amdgpu_ib_pipe_sync(job, tmp); 18065f7260bSAndrey Grodzovsky 181df83d1ebSChunming Zhou dma_fence_put(tmp); 182df83d1ebSChunming Zhou } 183d38ceaf9SAlex Deucher 184ef44f854SLeo Liu if (ring->funcs->insert_start) 185ef44f854SLeo Liu ring->funcs->insert_start(ring); 186ef44f854SLeo Liu 187df264f9eSChristian König if (job) { 1888fdf074fSMonk Liu r = amdgpu_vm_flush(ring, job, need_pipe_sync); 18941d9eb2cSChristian König if (r) { 19041d9eb2cSChristian König amdgpu_ring_undo(ring); 19141d9eb2cSChristian König return r; 19241d9eb2cSChristian König } 193794ff571SMonk Liu } 194d38ceaf9SAlex Deucher 195113890eeSMonk Liu if (job && ring->funcs->init_cond_exec) 196e9d672b2SMonk Liu patch_offset = amdgpu_ring_init_cond_exec(ring); 197e9d672b2SMonk Liu 198c5cb934eSChristian König #ifdef CONFIG_X86_64 1991b9d17dbSChristian König if (!(adev->flags & AMD_IS_APU)) 200c5cb934eSChristian König #endif 2011b9d17dbSChristian König { 2021b9d17dbSChristian König if (ring->funcs->emit_hdp_flush) 203d2edb07bSChristian König amdgpu_ring_emit_hdp_flush(ring); 2041b9d17dbSChristian König else 2051b9d17dbSChristian König amdgpu_asic_flush_hdp(adev, ring); 2061b9d17dbSChristian König } 207d2edb07bSChristian König 208753ad49cSMonk Liu if (need_ctx_switch) 209753ad49cSMonk Liu status |= AMDGPU_HAVE_CTX_SWITCH; 2107e6bf80fSMonk Liu 211c4c905ecSJack Xiao skip_preamble = ring->current_ctx == fence_ctx; 212c4c905ecSJack Xiao if (job && ring->funcs->emit_cntxcntl) { 213c4c905ecSJack Xiao status |= job->preamble_status; 214d8780dc7SJack Xiao status |= job->preemption_status; 215753ad49cSMonk Liu amdgpu_ring_emit_cntxcntl(ring, status); 216753ad49cSMonk Liu } 217753ad49cSMonk Liu 218d38ceaf9SAlex Deucher for (i = 0; i < num_ibs; ++i) { 219f153d286SChristian König ib = &ibs[i]; 2209f8fb5a2SChristian König 2219f8fb5a2SChristian König /* drop preamble IBs if we don't have a context switch */ 222753ad49cSMonk Liu if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 223753ad49cSMonk Liu skip_preamble && 22479bbbf8bSMonk Liu !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && 225f92d5c61SJack Xiao !amdgpu_mcbp && 22679bbbf8bSMonk Liu !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ 2279f8fb5a2SChristian König continue; 2289f8fb5a2SChristian König 229c4c905ecSJack Xiao amdgpu_ring_emit_ib(ring, job, ib, status); 230c4c905ecSJack Xiao status &= ~AMDGPU_HAVE_CTX_SWITCH; 231d38ceaf9SAlex Deucher } 232d38ceaf9SAlex Deucher 2333b4d68e9SMonk Liu if (ring->funcs->emit_tmz) 2343b4d68e9SMonk Liu amdgpu_ring_emit_tmz(ring, false); 2353b4d68e9SMonk Liu 236c5cb934eSChristian König #ifdef CONFIG_X86_64 2371b9d17dbSChristian König if (!(adev->flags & AMD_IS_APU)) 238c5cb934eSChristian König #endif 2391b9d17dbSChristian König amdgpu_asic_invalidate_hdp(adev, ring); 24011afbde8SChunming Zhou 241d240cd9eSMarek Olšák if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) 242d240cd9eSMarek Olšák fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; 243d240cd9eSMarek Olšák 2449fc15f5fSNicolai Hähnle /* wrap the last IB with fence */ 2459fc15f5fSNicolai Hähnle if (job && job->uf_addr) { 2469fc15f5fSNicolai Hähnle amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, 2479fc15f5fSNicolai Hähnle fence_flags | AMDGPU_FENCE_FLAG_64BIT); 2489fc15f5fSNicolai Hähnle } 2499fc15f5fSNicolai Hähnle 250d240cd9eSMarek Olšák r = amdgpu_fence_emit(ring, f, fence_flags); 251d38ceaf9SAlex Deucher if (r) { 252d38ceaf9SAlex Deucher dev_err(adev->dev, "failed to emit fence (%d)\n", r); 253c4f46f22SChristian König if (job && job->vmid) 254c4f46f22SChristian König amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid); 255a27de35cSChristian König amdgpu_ring_undo(ring); 256d38ceaf9SAlex Deucher return r; 257d38ceaf9SAlex Deucher } 258d38ceaf9SAlex Deucher 259135d4735SLeo Liu if (ring->funcs->insert_end) 260135d4735SLeo Liu ring->funcs->insert_end(ring); 261135d4735SLeo Liu 26203ccf481SMonk Liu if (patch_offset != ~0 && ring->funcs->patch_cond_exec) 26303ccf481SMonk Liu amdgpu_ring_patch_cond_exec(ring, patch_offset); 26403ccf481SMonk Liu 2653aecd24cSMonk Liu ring->current_ctx = fence_ctx; 266bc1e59b2SMonk Liu if (vm && ring->funcs->emit_switch_buffer) 267c2167a65SMonk Liu amdgpu_ring_emit_switch_buffer(ring); 268a27de35cSChristian König amdgpu_ring_commit(ring); 269d38ceaf9SAlex Deucher return 0; 270d38ceaf9SAlex Deucher } 271d38ceaf9SAlex Deucher 272d38ceaf9SAlex Deucher /** 273d38ceaf9SAlex Deucher * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 274d38ceaf9SAlex Deucher * 275d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 276d38ceaf9SAlex Deucher * 277d38ceaf9SAlex Deucher * Initialize the suballocator to manage a pool of memory 278d38ceaf9SAlex Deucher * for use as IBs (all asics). 279d38ceaf9SAlex Deucher * Returns 0 on success, error on failure. 280d38ceaf9SAlex Deucher */ 281d38ceaf9SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev) 282d38ceaf9SAlex Deucher { 283d38ceaf9SAlex Deucher int r; 284d38ceaf9SAlex Deucher 285d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 286d38ceaf9SAlex Deucher return 0; 287d38ceaf9SAlex Deucher } 288d38ceaf9SAlex Deucher r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 289d38ceaf9SAlex Deucher AMDGPU_IB_POOL_SIZE*64*1024, 290d38ceaf9SAlex Deucher AMDGPU_GPU_PAGE_SIZE, 291d38ceaf9SAlex Deucher AMDGPU_GEM_DOMAIN_GTT); 292d38ceaf9SAlex Deucher if (r) { 293d38ceaf9SAlex Deucher return r; 294d38ceaf9SAlex Deucher } 295d38ceaf9SAlex Deucher 296d38ceaf9SAlex Deucher adev->ib_pool_ready = true; 29715997544SAlex Deucher 298d38ceaf9SAlex Deucher return 0; 299d38ceaf9SAlex Deucher } 300d38ceaf9SAlex Deucher 301d38ceaf9SAlex Deucher /** 302d38ceaf9SAlex Deucher * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 303d38ceaf9SAlex Deucher * 304d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 305d38ceaf9SAlex Deucher * 306d38ceaf9SAlex Deucher * Tear down the suballocator managing the pool of memory 307d38ceaf9SAlex Deucher * for use as IBs (all asics). 308d38ceaf9SAlex Deucher */ 309d38ceaf9SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 310d38ceaf9SAlex Deucher { 311d38ceaf9SAlex Deucher if (adev->ib_pool_ready) { 312d38ceaf9SAlex Deucher amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 313d38ceaf9SAlex Deucher adev->ib_pool_ready = false; 314d38ceaf9SAlex Deucher } 315d38ceaf9SAlex Deucher } 316d38ceaf9SAlex Deucher 317d38ceaf9SAlex Deucher /** 318d38ceaf9SAlex Deucher * amdgpu_ib_ring_tests - test IBs on the rings 319d38ceaf9SAlex Deucher * 320d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 321d38ceaf9SAlex Deucher * 322d38ceaf9SAlex Deucher * Test an IB (Indirect Buffer) on each ring. 323d38ceaf9SAlex Deucher * If the test fails, disable the ring. 324d38ceaf9SAlex Deucher * Returns 0 on success, error if the primary GFX ring 325d38ceaf9SAlex Deucher * IB test fails. 326d38ceaf9SAlex Deucher */ 327d38ceaf9SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 328d38ceaf9SAlex Deucher { 329d38ceaf9SAlex Deucher unsigned i; 3301f703e66SChunming Zhou int r, ret = 0; 331dbf79765SMonk Liu long tmo_gfx, tmo_mm; 332dbf79765SMonk Liu 333dbf79765SMonk Liu tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT; 334dbf79765SMonk Liu if (amdgpu_sriov_vf(adev)) { 335dbf79765SMonk Liu /* for MM engines in hypervisor side they are not scheduled together 336dbf79765SMonk Liu * with CP and SDMA engines, so even in exclusive mode MM engine could 337dbf79765SMonk Liu * still running on other VF thus the IB TEST TIMEOUT for MM engines 338dbf79765SMonk Liu * under SR-IOV should be set to a long time. 8 sec should be enough 339dbf79765SMonk Liu * for the MM comes back to this VF. 340dbf79765SMonk Liu */ 341dbf79765SMonk Liu tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT; 342dbf79765SMonk Liu } 343dbf79765SMonk Liu 344dbf79765SMonk Liu if (amdgpu_sriov_runtime(adev)) { 345dbf79765SMonk Liu /* for CP & SDMA engines since they are scheduled together so 346dbf79765SMonk Liu * need to make the timeout width enough to cover the time 347dbf79765SMonk Liu * cost waiting for it coming back under RUNTIME only 348dbf79765SMonk Liu */ 349dbf79765SMonk Liu tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT; 350d4162c61Sshaoyunl } else if (adev->gmc.xgmi.hive_id) { 351d4162c61Sshaoyunl tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT; 352dbf79765SMonk Liu } 353d38ceaf9SAlex Deucher 354af70a471SChristian König for (i = 0; i < adev->num_rings; ++i) { 355d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 356dbf79765SMonk Liu long tmo; 357d38ceaf9SAlex Deucher 358315fed03SChristian König /* KIQ rings don't have an IB test because we never submit IBs 359315fed03SChristian König * to them and they have no interrupt support. 360158b594aSPratik Vishwakarma */ 361315fed03SChristian König if (!ring->sched.ready || !ring->funcs->test_ib) 362158b594aSPratik Vishwakarma continue; 363158b594aSPratik Vishwakarma 364dbf79765SMonk Liu /* MM engine need more time */ 365dbf79765SMonk Liu if (ring->funcs->type == AMDGPU_RING_TYPE_UVD || 366dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_VCE || 367dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC || 368dbf79765SMonk Liu ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC || 3695b2329b6SBoyuan Zhang ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 3705b2329b6SBoyuan Zhang ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 371dbf79765SMonk Liu tmo = tmo_mm; 372dbf79765SMonk Liu else 373dbf79765SMonk Liu tmo = tmo_gfx; 374dbf79765SMonk Liu 375dbf79765SMonk Liu r = amdgpu_ring_test_ib(ring, tmo); 376af70a471SChristian König if (!r) { 377af70a471SChristian König DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n", 378af70a471SChristian König ring->name); 379af70a471SChristian König continue; 380af70a471SChristian König } 381af70a471SChristian König 382c66ed765SAndrey Grodzovsky ring->sched.ready = false; 383af70a471SChristian König DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n", 384af70a471SChristian König ring->name, r); 385d38ceaf9SAlex Deucher 386d38ceaf9SAlex Deucher if (ring == &adev->gfx.gfx_ring[0]) { 387d38ceaf9SAlex Deucher /* oh, oh, that's really bad */ 388d38ceaf9SAlex Deucher adev->accel_working = false; 389d38ceaf9SAlex Deucher return r; 390d38ceaf9SAlex Deucher 391d38ceaf9SAlex Deucher } else { 3921f703e66SChunming Zhou ret = r; 393d38ceaf9SAlex Deucher } 394d38ceaf9SAlex Deucher } 3951f703e66SChunming Zhou return ret; 396d38ceaf9SAlex Deucher } 397d38ceaf9SAlex Deucher 398d38ceaf9SAlex Deucher /* 399d38ceaf9SAlex Deucher * Debugfs info 400d38ceaf9SAlex Deucher */ 401d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 402d38ceaf9SAlex Deucher 403d38ceaf9SAlex Deucher static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 404d38ceaf9SAlex Deucher { 405d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 406d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 407d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 408d38ceaf9SAlex Deucher 409d38ceaf9SAlex Deucher amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 410d38ceaf9SAlex Deucher 411d38ceaf9SAlex Deucher return 0; 412d38ceaf9SAlex Deucher 413d38ceaf9SAlex Deucher } 414d38ceaf9SAlex Deucher 41506ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_sa_list[] = { 416d38ceaf9SAlex Deucher {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 417d38ceaf9SAlex Deucher }; 418d38ceaf9SAlex Deucher 419d38ceaf9SAlex Deucher #endif 420d38ceaf9SAlex Deucher 42115997544SAlex Deucher int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 422d38ceaf9SAlex Deucher { 423d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 424d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 425d38ceaf9SAlex Deucher #else 426d38ceaf9SAlex Deucher return 0; 427d38ceaf9SAlex Deucher #endif 428d38ceaf9SAlex Deucher } 429