1*474e2d49SHawking Zhang /*
2*474e2d49SHawking Zhang * Copyright 2023 Advanced Micro Devices, Inc.
3*474e2d49SHawking Zhang *
4*474e2d49SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a
5*474e2d49SHawking Zhang * copy of this software and associated documentation files (the "Software"),
6*474e2d49SHawking Zhang * to deal in the Software without restriction, including without limitation
7*474e2d49SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*474e2d49SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the
9*474e2d49SHawking Zhang * Software is furnished to do so, subject to the following conditions:
10*474e2d49SHawking Zhang *
11*474e2d49SHawking Zhang * The above copyright notice and this permission notice shall be included in
12*474e2d49SHawking Zhang * all copies or substantial portions of the Software.
13*474e2d49SHawking Zhang *
14*474e2d49SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*474e2d49SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*474e2d49SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*474e2d49SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*474e2d49SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*474e2d49SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*474e2d49SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE.
21*474e2d49SHawking Zhang *
22*474e2d49SHawking Zhang */
23*474e2d49SHawking Zhang #include "amdgpu.h"
24*474e2d49SHawking Zhang #include "amdgpu_ras.h"
25*474e2d49SHawking Zhang
amdgpu_hdp_ras_sw_init(struct amdgpu_device * adev)26*474e2d49SHawking Zhang int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
27*474e2d49SHawking Zhang {
28*474e2d49SHawking Zhang int err;
29*474e2d49SHawking Zhang struct amdgpu_hdp_ras *ras;
30*474e2d49SHawking Zhang
31*474e2d49SHawking Zhang if (!adev->hdp.ras)
32*474e2d49SHawking Zhang return 0;
33*474e2d49SHawking Zhang
34*474e2d49SHawking Zhang ras = adev->hdp.ras;
35*474e2d49SHawking Zhang err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
36*474e2d49SHawking Zhang if (err) {
37*474e2d49SHawking Zhang dev_err(adev->dev, "Failed to register hdp ras block!\n");
38*474e2d49SHawking Zhang return err;
39*474e2d49SHawking Zhang }
40*474e2d49SHawking Zhang
41*474e2d49SHawking Zhang strcpy(ras->ras_block.ras_comm.name, "hdp");
42*474e2d49SHawking Zhang ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP;
43*474e2d49SHawking Zhang ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
44*474e2d49SHawking Zhang adev->hdp.ras_if = &ras->ras_block.ras_comm;
45*474e2d49SHawking Zhang
46*474e2d49SHawking Zhang /* hdp ras follows amdgpu_ras_block_late_init_default for late init */
47*474e2d49SHawking Zhang return 0;
48*474e2d49SHawking Zhang }
49