1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_ras.h" 33 34 /* VA hole for 48bit addresses on Vega10 */ 35 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 36 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 37 38 /* 39 * Hardware is programmed as if the hole doesn't exists with start and end 40 * address values. 41 * 42 * This mask is used to remove the upper 16bits of the VA and so come up with 43 * the linear addr value. 44 */ 45 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 46 47 /* 48 * Ring size as power of two for the log of recent faults. 49 */ 50 #define AMDGPU_GMC_FAULT_RING_ORDER 8 51 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 52 53 /* 54 * Hash size as power of two for the log of recent faults 55 */ 56 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 57 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 58 59 /* 60 * Number of IH timestamp ticks until a fault is considered handled 61 */ 62 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 63 64 struct firmware; 65 66 /* 67 * GMC page fault information 68 */ 69 struct amdgpu_gmc_fault { 70 uint64_t timestamp:48; 71 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 72 atomic64_t key; 73 uint64_t timestamp_expiry:48; 74 }; 75 76 /* 77 * VMHUB structures, functions & helpers 78 */ 79 struct amdgpu_vmhub_funcs { 80 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 81 uint32_t status); 82 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 83 }; 84 85 struct amdgpu_vmhub { 86 uint32_t ctx0_ptb_addr_lo32; 87 uint32_t ctx0_ptb_addr_hi32; 88 uint32_t vm_inv_eng0_sem; 89 uint32_t vm_inv_eng0_req; 90 uint32_t vm_inv_eng0_ack; 91 uint32_t vm_context0_cntl; 92 uint32_t vm_l2_pro_fault_status; 93 uint32_t vm_l2_pro_fault_cntl; 94 95 /* 96 * store the register distances between two continuous context domain 97 * and invalidation engine. 98 */ 99 uint32_t ctx_distance; 100 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 101 uint32_t eng_distance; 102 uint32_t eng_addr_distance; /* include LO32/HI32 */ 103 104 uint32_t vm_cntx_cntl; 105 uint32_t vm_cntx_cntl_vm_fault; 106 uint32_t vm_l2_bank_select_reserved_cid2; 107 108 uint32_t vm_contexts_disable; 109 110 const struct amdgpu_vmhub_funcs *vmhub_funcs; 111 }; 112 113 /* 114 * GPU MC structures, functions & helpers 115 */ 116 struct amdgpu_gmc_funcs { 117 /* flush the vm tlb via mmio */ 118 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 119 uint32_t vmhub, uint32_t flush_type); 120 /* flush the vm tlb via pasid */ 121 int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 122 uint32_t flush_type, bool all_hub); 123 /* flush the vm tlb via ring */ 124 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 125 uint64_t pd_addr); 126 /* Change the VMID -> PASID mapping */ 127 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 128 unsigned pasid); 129 /* enable/disable PRT support */ 130 void (*set_prt)(struct amdgpu_device *adev, bool enable); 131 /* map mtype to hardware flags */ 132 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 133 /* get the pde for a given mc addr */ 134 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 135 u64 *dst, u64 *flags); 136 /* get the pte flags to use for a BO VA mapping */ 137 void (*get_vm_pte)(struct amdgpu_device *adev, 138 struct amdgpu_bo_va_mapping *mapping, 139 uint64_t *flags); 140 /* get the amount of memory used by the vbios for pre-OS console */ 141 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 142 }; 143 144 struct amdgpu_xgmi_ras { 145 struct amdgpu_ras_block_object ras_block; 146 }; 147 148 struct amdgpu_xgmi { 149 /* from psp */ 150 u64 node_id; 151 u64 hive_id; 152 /* fixed per family */ 153 u64 node_segment_size; 154 /* physical node (0-3) */ 155 unsigned physical_node_id; 156 /* number of nodes (0-4) */ 157 unsigned num_physical_nodes; 158 /* gpu list in the same hive */ 159 struct list_head head; 160 bool supported; 161 struct ras_common_if *ras_if; 162 bool connected_to_cpu; 163 bool pending_reset; 164 struct amdgpu_xgmi_ras *ras; 165 }; 166 167 struct amdgpu_gmc { 168 /* FB's physical address in MMIO space (for CPU to 169 * map FB). This is different compared to the agp/ 170 * gart/vram_start/end field as the later is from 171 * GPU's view and aper_base is from CPU's view. 172 */ 173 resource_size_t aper_size; 174 resource_size_t aper_base; 175 /* for some chips with <= 32MB we need to lie 176 * about vram size near mc fb location */ 177 u64 mc_vram_size; 178 u64 visible_vram_size; 179 /* AGP aperture start and end in MC address space 180 * Driver find a hole in the MC address space 181 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 182 * Under VMID0, logical address == MC address. AGP 183 * aperture maps to physical bus or IOVA addressed. 184 * AGP aperture is used to simulate FB in ZFB case. 185 * AGP aperture is also used for page table in system 186 * memory (mainly for APU). 187 * 188 */ 189 u64 agp_size; 190 u64 agp_start; 191 u64 agp_end; 192 /* GART aperture start and end in MC address space 193 * Driver find a hole in the MC address space 194 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 195 * registers 196 * Under VMID0, logical address inside GART aperture will 197 * be translated through gpuvm gart page table to access 198 * paged system memory 199 */ 200 u64 gart_size; 201 u64 gart_start; 202 u64 gart_end; 203 /* Frame buffer aperture of this GPU device. Different from 204 * fb_start (see below), this only covers the local GPU device. 205 * If driver uses FB aperture to access FB, driver get fb_start from 206 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 207 * of this local device by adding an offset inside the XGMI hive. 208 * If driver uses GART table for VMID0 FB access, driver finds a hole in 209 * VMID0's virtual address space to place the SYSVM aperture inside 210 * which the first part is vram and the second part is gart (covering 211 * system ram). 212 */ 213 u64 vram_start; 214 u64 vram_end; 215 /* FB region , it's same as local vram region in single GPU, in XGMI 216 * configuration, this region covers all GPUs in the same hive , 217 * each GPU in the hive has the same view of this FB region . 218 * GPU0's vram starts at offset (0 * segment size) , 219 * GPU1 starts at offset (1 * segment size), etc. 220 */ 221 u64 fb_start; 222 u64 fb_end; 223 unsigned vram_width; 224 u64 real_vram_size; 225 int vram_mtrr; 226 u64 mc_mask; 227 const struct firmware *fw; /* MC firmware */ 228 uint32_t fw_version; 229 struct amdgpu_irq_src vm_fault; 230 uint32_t vram_type; 231 uint8_t vram_vendor; 232 uint32_t srbm_soft_reset; 233 bool prt_warning; 234 uint32_t sdpif_register; 235 /* apertures */ 236 u64 shared_aperture_start; 237 u64 shared_aperture_end; 238 u64 private_aperture_start; 239 u64 private_aperture_end; 240 /* protects concurrent invalidation */ 241 spinlock_t invalidate_lock; 242 bool translate_further; 243 struct kfd_vm_fault_info *vm_fault_info; 244 atomic_t vm_fault_info_updated; 245 246 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 247 struct { 248 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 249 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 250 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 251 252 bool tmz_enabled; 253 254 const struct amdgpu_gmc_funcs *gmc_funcs; 255 256 struct amdgpu_xgmi xgmi; 257 struct amdgpu_irq_src ecc_irq; 258 int noretry; 259 260 uint32_t vmid0_page_table_block_size; 261 uint32_t vmid0_page_table_depth; 262 struct amdgpu_bo *pdb0_bo; 263 /* CPU kmapped address of pdb0*/ 264 void *ptr_pdb0; 265 266 /* MALL size */ 267 u64 mall_size; 268 /* number of UMC instances */ 269 int num_umc; 270 /* mode2 save restore */ 271 u64 VM_L2_CNTL; 272 u64 VM_L2_CNTL2; 273 u64 VM_DUMMY_PAGE_FAULT_CNTL; 274 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 275 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 276 u64 VM_L2_PROTECTION_FAULT_CNTL; 277 u64 VM_L2_PROTECTION_FAULT_CNTL2; 278 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 279 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 280 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 281 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 282 u64 VM_DEBUG; 283 u64 VM_L2_MM_GROUP_RT_CLASSES; 284 u64 VM_L2_BANK_SELECT_RESERVED_CID; 285 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 286 u64 VM_L2_CACHE_PARITY_CNTL; 287 u64 VM_L2_IH_LOG_CNTL; 288 u64 VM_CONTEXT_CNTL[16]; 289 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 290 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 291 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 292 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 293 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 294 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 295 u64 MC_VM_MX_L1_TLB_CNTL; 296 }; 297 298 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) 299 #define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \ 300 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \ 301 ((adev), (pasid), (type), (allhub))) 302 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 303 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 304 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 305 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 306 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 307 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 308 309 /** 310 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 311 * 312 * @adev: amdgpu_device pointer 313 * 314 * Returns: 315 * True if full VRAM is visible through the BAR 316 */ 317 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 318 { 319 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 320 321 return (gmc->real_vram_size == gmc->visible_vram_size); 322 } 323 324 /** 325 * amdgpu_gmc_sign_extend - sign extend the given gmc address 326 * 327 * @addr: address to extend 328 */ 329 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 330 { 331 if (addr >= AMDGPU_GMC_HOLE_START) 332 addr |= AMDGPU_GMC_HOLE_END; 333 334 return addr; 335 } 336 337 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 338 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 339 uint64_t *addr, uint64_t *flags); 340 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 341 uint32_t gpu_page_idx, uint64_t addr, 342 uint64_t flags); 343 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 344 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 345 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 346 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 347 u64 base); 348 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 349 struct amdgpu_gmc *mc); 350 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 351 struct amdgpu_gmc *mc); 352 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 353 struct amdgpu_ih_ring *ih, uint64_t addr, 354 uint16_t pasid, uint64_t timestamp); 355 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 356 uint16_t pasid); 357 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 358 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 359 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 360 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 361 362 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 363 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 364 365 extern void 366 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 367 bool enable); 368 369 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 370 371 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 372 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 373 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 374 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 375 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 376 #endif 377