1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_ras.h" 33 34 /* VA hole for 48bit addresses on Vega10 */ 35 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 36 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 37 38 /* 39 * Hardware is programmed as if the hole doesn't exists with start and end 40 * address values. 41 * 42 * This mask is used to remove the upper 16bits of the VA and so come up with 43 * the linear addr value. 44 */ 45 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 46 47 /* 48 * Ring size as power of two for the log of recent faults. 49 */ 50 #define AMDGPU_GMC_FAULT_RING_ORDER 8 51 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 52 53 /* 54 * Hash size as power of two for the log of recent faults 55 */ 56 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 57 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 58 59 /* 60 * Number of IH timestamp ticks until a fault is considered handled 61 */ 62 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 63 64 struct firmware; 65 66 /* 67 * GMC page fault information 68 */ 69 struct amdgpu_gmc_fault { 70 uint64_t timestamp:48; 71 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 72 atomic64_t key; 73 }; 74 75 /* 76 * VMHUB structures, functions & helpers 77 */ 78 struct amdgpu_vmhub_funcs { 79 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 80 uint32_t status); 81 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 82 }; 83 84 struct amdgpu_vmhub { 85 uint32_t ctx0_ptb_addr_lo32; 86 uint32_t ctx0_ptb_addr_hi32; 87 uint32_t vm_inv_eng0_sem; 88 uint32_t vm_inv_eng0_req; 89 uint32_t vm_inv_eng0_ack; 90 uint32_t vm_context0_cntl; 91 uint32_t vm_l2_pro_fault_status; 92 uint32_t vm_l2_pro_fault_cntl; 93 94 /* 95 * store the register distances between two continuous context domain 96 * and invalidation engine. 97 */ 98 uint32_t ctx_distance; 99 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 100 uint32_t eng_distance; 101 uint32_t eng_addr_distance; /* include LO32/HI32 */ 102 103 uint32_t vm_cntx_cntl; 104 uint32_t vm_cntx_cntl_vm_fault; 105 uint32_t vm_l2_bank_select_reserved_cid2; 106 107 uint32_t vm_contexts_disable; 108 109 const struct amdgpu_vmhub_funcs *vmhub_funcs; 110 }; 111 112 /* 113 * GPU MC structures, functions & helpers 114 */ 115 struct amdgpu_gmc_funcs { 116 /* flush the vm tlb via mmio */ 117 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 118 uint32_t vmhub, uint32_t flush_type); 119 /* flush the vm tlb via pasid */ 120 int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 121 uint32_t flush_type, bool all_hub); 122 /* flush the vm tlb via ring */ 123 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 124 uint64_t pd_addr); 125 /* Change the VMID -> PASID mapping */ 126 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 127 unsigned pasid); 128 /* enable/disable PRT support */ 129 void (*set_prt)(struct amdgpu_device *adev, bool enable); 130 /* map mtype to hardware flags */ 131 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 132 /* get the pde for a given mc addr */ 133 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 134 u64 *dst, u64 *flags); 135 /* get the pte flags to use for a BO VA mapping */ 136 void (*get_vm_pte)(struct amdgpu_device *adev, 137 struct amdgpu_bo_va_mapping *mapping, 138 uint64_t *flags); 139 /* get the amount of memory used by the vbios for pre-OS console */ 140 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 141 }; 142 143 struct amdgpu_xgmi_ras { 144 struct amdgpu_ras_block_object ras_block; 145 }; 146 147 struct amdgpu_xgmi { 148 /* from psp */ 149 u64 node_id; 150 u64 hive_id; 151 /* fixed per family */ 152 u64 node_segment_size; 153 /* physical node (0-3) */ 154 unsigned physical_node_id; 155 /* number of nodes (0-4) */ 156 unsigned num_physical_nodes; 157 /* gpu list in the same hive */ 158 struct list_head head; 159 bool supported; 160 struct ras_common_if *ras_if; 161 bool connected_to_cpu; 162 bool pending_reset; 163 struct amdgpu_xgmi_ras *ras; 164 }; 165 166 struct amdgpu_gmc { 167 /* FB's physical address in MMIO space (for CPU to 168 * map FB). This is different compared to the agp/ 169 * gart/vram_start/end field as the later is from 170 * GPU's view and aper_base is from CPU's view. 171 */ 172 resource_size_t aper_size; 173 resource_size_t aper_base; 174 /* for some chips with <= 32MB we need to lie 175 * about vram size near mc fb location */ 176 u64 mc_vram_size; 177 u64 visible_vram_size; 178 /* AGP aperture start and end in MC address space 179 * Driver find a hole in the MC address space 180 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 181 * Under VMID0, logical address == MC address. AGP 182 * aperture maps to physical bus or IOVA addressed. 183 * AGP aperture is used to simulate FB in ZFB case. 184 * AGP aperture is also used for page table in system 185 * memory (mainly for APU). 186 * 187 */ 188 u64 agp_size; 189 u64 agp_start; 190 u64 agp_end; 191 /* GART aperture start and end in MC address space 192 * Driver find a hole in the MC address space 193 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 194 * registers 195 * Under VMID0, logical address inside GART aperture will 196 * be translated through gpuvm gart page table to access 197 * paged system memory 198 */ 199 u64 gart_size; 200 u64 gart_start; 201 u64 gart_end; 202 /* Frame buffer aperture of this GPU device. Different from 203 * fb_start (see below), this only covers the local GPU device. 204 * If driver uses FB aperture to access FB, driver get fb_start from 205 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 206 * of this local device by adding an offset inside the XGMI hive. 207 * If driver uses GART table for VMID0 FB access, driver finds a hole in 208 * VMID0's virtual address space to place the SYSVM aperture inside 209 * which the first part is vram and the second part is gart (covering 210 * system ram). 211 */ 212 u64 vram_start; 213 u64 vram_end; 214 /* FB region , it's same as local vram region in single GPU, in XGMI 215 * configuration, this region covers all GPUs in the same hive , 216 * each GPU in the hive has the same view of this FB region . 217 * GPU0's vram starts at offset (0 * segment size) , 218 * GPU1 starts at offset (1 * segment size), etc. 219 */ 220 u64 fb_start; 221 u64 fb_end; 222 unsigned vram_width; 223 u64 real_vram_size; 224 int vram_mtrr; 225 u64 mc_mask; 226 const struct firmware *fw; /* MC firmware */ 227 uint32_t fw_version; 228 struct amdgpu_irq_src vm_fault; 229 uint32_t vram_type; 230 uint8_t vram_vendor; 231 uint32_t srbm_soft_reset; 232 bool prt_warning; 233 uint32_t sdpif_register; 234 /* apertures */ 235 u64 shared_aperture_start; 236 u64 shared_aperture_end; 237 u64 private_aperture_start; 238 u64 private_aperture_end; 239 /* protects concurrent invalidation */ 240 spinlock_t invalidate_lock; 241 bool translate_further; 242 struct kfd_vm_fault_info *vm_fault_info; 243 atomic_t vm_fault_info_updated; 244 245 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 246 struct { 247 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 248 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 249 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 250 251 bool tmz_enabled; 252 253 const struct amdgpu_gmc_funcs *gmc_funcs; 254 255 struct amdgpu_xgmi xgmi; 256 struct amdgpu_irq_src ecc_irq; 257 int noretry; 258 259 uint32_t vmid0_page_table_block_size; 260 uint32_t vmid0_page_table_depth; 261 struct amdgpu_bo *pdb0_bo; 262 /* CPU kmapped address of pdb0*/ 263 void *ptr_pdb0; 264 265 /* MALL size */ 266 u64 mall_size; 267 /* number of UMC instances */ 268 int num_umc; 269 /* mode2 save restore */ 270 u64 VM_L2_CNTL; 271 u64 VM_L2_CNTL2; 272 u64 VM_DUMMY_PAGE_FAULT_CNTL; 273 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 274 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 275 u64 VM_L2_PROTECTION_FAULT_CNTL; 276 u64 VM_L2_PROTECTION_FAULT_CNTL2; 277 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 278 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 279 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 280 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 281 u64 VM_DEBUG; 282 u64 VM_L2_MM_GROUP_RT_CLASSES; 283 u64 VM_L2_BANK_SELECT_RESERVED_CID; 284 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 285 u64 VM_L2_CACHE_PARITY_CNTL; 286 u64 VM_L2_IH_LOG_CNTL; 287 u64 VM_CONTEXT_CNTL[16]; 288 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 289 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 290 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 291 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 292 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 293 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 294 u64 MC_VM_MX_L1_TLB_CNTL; 295 }; 296 297 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) 298 #define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \ 299 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \ 300 ((adev), (pasid), (type), (allhub))) 301 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 302 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 303 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 304 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 305 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 306 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 307 308 /** 309 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 310 * 311 * @adev: amdgpu_device pointer 312 * 313 * Returns: 314 * True if full VRAM is visible through the BAR 315 */ 316 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 317 { 318 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 319 320 return (gmc->real_vram_size == gmc->visible_vram_size); 321 } 322 323 /** 324 * amdgpu_gmc_sign_extend - sign extend the given gmc address 325 * 326 * @addr: address to extend 327 */ 328 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 329 { 330 if (addr >= AMDGPU_GMC_HOLE_START) 331 addr |= AMDGPU_GMC_HOLE_END; 332 333 return addr; 334 } 335 336 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 337 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 338 uint64_t *addr, uint64_t *flags); 339 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 340 uint32_t gpu_page_idx, uint64_t addr, 341 uint64_t flags); 342 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 343 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 344 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 345 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 346 u64 base); 347 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 348 struct amdgpu_gmc *mc); 349 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 350 struct amdgpu_gmc *mc); 351 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 352 struct amdgpu_ih_ring *ih, uint64_t addr, 353 uint16_t pasid, uint64_t timestamp); 354 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 355 uint16_t pasid); 356 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 357 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 358 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 359 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 360 361 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 362 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 363 364 extern void 365 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 366 bool enable); 367 368 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 369 370 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 371 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 372 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 373 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 374 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 375 #endif 376