1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 33 /* VA hole for 48bit addresses on Vega10 */ 34 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 35 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 36 37 /* 38 * Hardware is programmed as if the hole doesn't exists with start and end 39 * address values. 40 * 41 * This mask is used to remove the upper 16bits of the VA and so come up with 42 * the linear addr value. 43 */ 44 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 45 46 /* 47 * Ring size as power of two for the log of recent faults. 48 */ 49 #define AMDGPU_GMC_FAULT_RING_ORDER 8 50 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 51 52 /* 53 * Hash size as power of two for the log of recent faults 54 */ 55 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 56 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 57 58 /* 59 * Number of IH timestamp ticks until a fault is considered handled 60 */ 61 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 62 63 struct firmware; 64 65 /* 66 * GMC page fault information 67 */ 68 struct amdgpu_gmc_fault { 69 uint64_t timestamp; 70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 71 uint64_t key:52; 72 }; 73 74 /* 75 * VMHUB structures, functions & helpers 76 */ 77 struct amdgpu_vmhub { 78 uint32_t ctx0_ptb_addr_lo32; 79 uint32_t ctx0_ptb_addr_hi32; 80 uint32_t vm_inv_eng0_req; 81 uint32_t vm_inv_eng0_ack; 82 uint32_t vm_context0_cntl; 83 uint32_t vm_l2_pro_fault_status; 84 uint32_t vm_l2_pro_fault_cntl; 85 }; 86 87 /* 88 * GPU MC structures, functions & helpers 89 */ 90 struct amdgpu_gmc_funcs { 91 /* flush the vm tlb via mmio */ 92 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 93 uint32_t vmhub, uint32_t flush_type); 94 /* flush the vm tlb via ring */ 95 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 96 uint64_t pd_addr); 97 /* Change the VMID -> PASID mapping */ 98 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 99 unsigned pasid); 100 /* enable/disable PRT support */ 101 void (*set_prt)(struct amdgpu_device *adev, bool enable); 102 /* map mtype to hardware flags */ 103 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 104 /* get the pde for a given mc addr */ 105 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 106 u64 *dst, u64 *flags); 107 /* get the pte flags to use for a BO VA mapping */ 108 void (*get_vm_pte)(struct amdgpu_device *adev, 109 struct amdgpu_bo_va_mapping *mapping, 110 uint64_t *flags); 111 }; 112 113 struct amdgpu_xgmi { 114 /* from psp */ 115 u64 node_id; 116 u64 hive_id; 117 /* fixed per family */ 118 u64 node_segment_size; 119 /* physical node (0-3) */ 120 unsigned physical_node_id; 121 /* number of nodes (0-4) */ 122 unsigned num_physical_nodes; 123 /* gpu list in the same hive */ 124 struct list_head head; 125 bool supported; 126 struct ras_common_if *ras_if; 127 }; 128 129 struct amdgpu_gmc { 130 /* FB's physical address in MMIO space (for CPU to 131 * map FB). This is different compared to the agp/ 132 * gart/vram_start/end field as the later is from 133 * GPU's view and aper_base is from CPU's view. 134 */ 135 resource_size_t aper_size; 136 resource_size_t aper_base; 137 /* for some chips with <= 32MB we need to lie 138 * about vram size near mc fb location */ 139 u64 mc_vram_size; 140 u64 visible_vram_size; 141 /* AGP aperture start and end in MC address space 142 * Driver find a hole in the MC address space 143 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 144 * Under VMID0, logical address == MC address. AGP 145 * aperture maps to physical bus or IOVA addressed. 146 * AGP aperture is used to simulate FB in ZFB case. 147 * AGP aperture is also used for page table in system 148 * memory (mainly for APU). 149 * 150 */ 151 u64 agp_size; 152 u64 agp_start; 153 u64 agp_end; 154 /* GART aperture start and end in MC address space 155 * Driver find a hole in the MC address space 156 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 157 * registers 158 * Under VMID0, logical address inside GART aperture will 159 * be translated through gpuvm gart page table to access 160 * paged system memory 161 */ 162 u64 gart_size; 163 u64 gart_start; 164 u64 gart_end; 165 /* Frame buffer aperture of this GPU device. Different from 166 * fb_start (see below), this only covers the local GPU device. 167 * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios) 168 * and calculate vram_start of this local device by adding an 169 * offset inside the XGMI hive. 170 * Under VMID0, logical address == MC address 171 */ 172 u64 vram_start; 173 u64 vram_end; 174 /* FB region , it's same as local vram region in single GPU, in XGMI 175 * configuration, this region covers all GPUs in the same hive , 176 * each GPU in the hive has the same view of this FB region . 177 * GPU0's vram starts at offset (0 * segment size) , 178 * GPU1 starts at offset (1 * segment size), etc. 179 */ 180 u64 fb_start; 181 u64 fb_end; 182 unsigned vram_width; 183 u64 real_vram_size; 184 int vram_mtrr; 185 u64 mc_mask; 186 const struct firmware *fw; /* MC firmware */ 187 uint32_t fw_version; 188 struct amdgpu_irq_src vm_fault; 189 uint32_t vram_type; 190 uint8_t vram_vendor; 191 uint32_t srbm_soft_reset; 192 bool prt_warning; 193 uint64_t stolen_size; 194 /* apertures */ 195 u64 shared_aperture_start; 196 u64 shared_aperture_end; 197 u64 private_aperture_start; 198 u64 private_aperture_end; 199 /* protects concurrent invalidation */ 200 spinlock_t invalidate_lock; 201 bool translate_further; 202 struct kfd_vm_fault_info *vm_fault_info; 203 atomic_t vm_fault_info_updated; 204 205 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 206 struct { 207 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 208 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 209 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 210 211 const struct amdgpu_gmc_funcs *gmc_funcs; 212 213 struct amdgpu_xgmi xgmi; 214 struct amdgpu_irq_src ecc_irq; 215 }; 216 217 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) 218 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 219 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 220 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 221 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 222 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 223 224 /** 225 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 226 * 227 * @adev: amdgpu_device pointer 228 * 229 * Returns: 230 * True if full VRAM is visible through the BAR 231 */ 232 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 233 { 234 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 235 236 return (gmc->real_vram_size == gmc->visible_vram_size); 237 } 238 239 /** 240 * amdgpu_gmc_sign_extend - sign extend the given gmc address 241 * 242 * @addr: address to extend 243 */ 244 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 245 { 246 if (addr >= AMDGPU_GMC_HOLE_START) 247 addr |= AMDGPU_GMC_HOLE_END; 248 249 return addr; 250 } 251 252 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 253 uint64_t *addr, uint64_t *flags); 254 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 255 uint32_t gpu_page_idx, uint64_t addr, 256 uint64_t flags); 257 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 258 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 259 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 260 u64 base); 261 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 262 struct amdgpu_gmc *mc); 263 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 264 struct amdgpu_gmc *mc); 265 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 266 uint16_t pasid, uint64_t timestamp); 267 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 268 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 269 270 #endif 271