1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 #ifndef __AMDGPU_GMC_H__
27 #define __AMDGPU_GMC_H__
28 
29 #include <linux/types.h>
30 
31 #include "amdgpu_irq.h"
32 #include "amdgpu_ras.h"
33 
34 /* VA hole for 48bit addresses on Vega10 */
35 #define AMDGPU_GMC_HOLE_START	0x0000800000000000ULL
36 #define AMDGPU_GMC_HOLE_END	0xffff800000000000ULL
37 
38 /*
39  * Hardware is programmed as if the hole doesn't exists with start and end
40  * address values.
41  *
42  * This mask is used to remove the upper 16bits of the VA and so come up with
43  * the linear addr value.
44  */
45 #define AMDGPU_GMC_HOLE_MASK	0x0000ffffffffffffULL
46 
47 /*
48  * Ring size as power of two for the log of recent faults.
49  */
50 #define AMDGPU_GMC_FAULT_RING_ORDER	8
51 #define AMDGPU_GMC_FAULT_RING_SIZE	(1 << AMDGPU_GMC_FAULT_RING_ORDER)
52 
53 /*
54  * Hash size as power of two for the log of recent faults
55  */
56 #define AMDGPU_GMC_FAULT_HASH_ORDER	8
57 #define AMDGPU_GMC_FAULT_HASH_SIZE	(1 << AMDGPU_GMC_FAULT_HASH_ORDER)
58 
59 /*
60  * Number of IH timestamp ticks until a fault is considered handled
61  */
62 #define AMDGPU_GMC_FAULT_TIMEOUT	5000ULL
63 
64 struct firmware;
65 
66 enum amdgpu_memory_partition {
67 	UNKNOWN_MEMORY_PARTITION_MODE = 0,
68 	AMDGPU_NPS1_PARTITION_MODE = 1,
69 	AMDGPU_NPS2_PARTITION_MODE = 2,
70 	AMDGPU_NPS3_PARTITION_MODE = 3,
71 	AMDGPU_NPS4_PARTITION_MODE = 4,
72 	AMDGPU_NPS6_PARTITION_MODE = 6,
73 	AMDGPU_NPS8_PARTITION_MODE = 8,
74 };
75 
76 /*
77  * GMC page fault information
78  */
79 struct amdgpu_gmc_fault {
80 	uint64_t	timestamp:48;
81 	uint64_t	next:AMDGPU_GMC_FAULT_RING_ORDER;
82 	atomic64_t	key;
83 	uint64_t	timestamp_expiry:48;
84 };
85 
86 /*
87  * VMHUB structures, functions & helpers
88  */
89 struct amdgpu_vmhub_funcs {
90 	void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
91 						 uint32_t status);
92 	uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
93 };
94 
95 struct amdgpu_vmhub {
96 	uint32_t	ctx0_ptb_addr_lo32;
97 	uint32_t	ctx0_ptb_addr_hi32;
98 	uint32_t	vm_inv_eng0_sem;
99 	uint32_t	vm_inv_eng0_req;
100 	uint32_t	vm_inv_eng0_ack;
101 	uint32_t	vm_context0_cntl;
102 	uint32_t	vm_l2_pro_fault_status;
103 	uint32_t	vm_l2_pro_fault_cntl;
104 
105 	/*
106 	 * store the register distances between two continuous context domain
107 	 * and invalidation engine.
108 	 */
109 	uint32_t	ctx_distance;
110 	uint32_t	ctx_addr_distance; /* include LO32/HI32 */
111 	uint32_t	eng_distance;
112 	uint32_t	eng_addr_distance; /* include LO32/HI32 */
113 
114 	uint32_t        vm_cntx_cntl;
115 	uint32_t	vm_cntx_cntl_vm_fault;
116 	uint32_t	vm_l2_bank_select_reserved_cid2;
117 
118 	uint32_t	vm_contexts_disable;
119 
120 	const struct amdgpu_vmhub_funcs *vmhub_funcs;
121 };
122 
123 /*
124  * GPU MC structures, functions & helpers
125  */
126 struct amdgpu_gmc_funcs {
127 	/* flush the vm tlb via mmio */
128 	void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
129 				uint32_t vmhub, uint32_t flush_type);
130 	/* flush the vm tlb via pasid */
131 	int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
132 					uint32_t flush_type, bool all_hub,
133 					uint32_t inst);
134 	/* flush the vm tlb via ring */
135 	uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
136 				       uint64_t pd_addr);
137 	/* Change the VMID -> PASID mapping */
138 	void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
139 				   unsigned pasid);
140 	/* enable/disable PRT support */
141 	void (*set_prt)(struct amdgpu_device *adev, bool enable);
142 	/* map mtype to hardware flags */
143 	uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
144 	/* get the pde for a given mc addr */
145 	void (*get_vm_pde)(struct amdgpu_device *adev, int level,
146 			   u64 *dst, u64 *flags);
147 	/* get the pte flags to use for a BO VA mapping */
148 	void (*get_vm_pte)(struct amdgpu_device *adev,
149 			   struct amdgpu_bo_va_mapping *mapping,
150 			   uint64_t *flags);
151 	/* override per-page pte flags */
152 	void (*override_vm_pte_flags)(struct amdgpu_device *dev,
153 				      struct amdgpu_vm *vm,
154 				      uint64_t addr, uint64_t *flags);
155 	/* get the amount of memory used by the vbios for pre-OS console */
156 	unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
157 
158 	enum amdgpu_memory_partition (*query_mem_partition_mode)(
159 		struct amdgpu_device *adev);
160 };
161 
162 struct amdgpu_xgmi_ras {
163 	struct amdgpu_ras_block_object ras_block;
164 };
165 
166 struct amdgpu_xgmi {
167 	/* from psp */
168 	u64 node_id;
169 	u64 hive_id;
170 	/* fixed per family */
171 	u64 node_segment_size;
172 	/* physical node (0-3) */
173 	unsigned physical_node_id;
174 	/* number of nodes (0-4) */
175 	unsigned num_physical_nodes;
176 	/* gpu list in the same hive */
177 	struct list_head head;
178 	bool supported;
179 	struct ras_common_if *ras_if;
180 	bool connected_to_cpu;
181 	bool pending_reset;
182 	struct amdgpu_xgmi_ras *ras;
183 };
184 
185 struct amdgpu_mem_partition_info {
186 	union {
187 		struct {
188 			uint32_t fpfn;
189 			uint32_t lpfn;
190 		} range;
191 		struct {
192 			int node;
193 		} numa;
194 	};
195 	uint64_t size;
196 };
197 
198 #define INVALID_PFN    -1
199 
200 struct amdgpu_gmc {
201 	/* FB's physical address in MMIO space (for CPU to
202 	 * map FB). This is different compared to the agp/
203 	 * gart/vram_start/end field as the later is from
204 	 * GPU's view and aper_base is from CPU's view.
205 	 */
206 	resource_size_t		aper_size;
207 	resource_size_t		aper_base;
208 	/* for some chips with <= 32MB we need to lie
209 	 * about vram size near mc fb location */
210 	u64			mc_vram_size;
211 	u64			visible_vram_size;
212 	/* AGP aperture start and end in MC address space
213 	 * Driver find a hole in the MC address space
214 	 * to place AGP by setting MC_VM_AGP_BOT/TOP registers
215 	 * Under VMID0, logical address == MC address. AGP
216 	 * aperture maps to physical bus or IOVA addressed.
217 	 * AGP aperture is used to simulate FB in ZFB case.
218 	 * AGP aperture is also used for page table in system
219 	 * memory (mainly for APU).
220 	 *
221 	 */
222 	u64			agp_size;
223 	u64			agp_start;
224 	u64			agp_end;
225 	/* GART aperture start and end in MC address space
226 	 * Driver find a hole in the MC address space
227 	 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
228 	 * registers
229 	 * Under VMID0, logical address inside GART aperture will
230 	 * be translated through gpuvm gart page table to access
231 	 * paged system memory
232 	 */
233 	u64			gart_size;
234 	u64			gart_start;
235 	u64			gart_end;
236 	/* Frame buffer aperture of this GPU device. Different from
237 	 * fb_start (see below), this only covers the local GPU device.
238 	 * If driver uses FB aperture to access FB, driver get fb_start from
239 	 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start
240 	 * of this local device by adding an offset inside the XGMI hive.
241 	 * If driver uses GART table for VMID0 FB access, driver finds a hole in
242 	 * VMID0's virtual address space to place the SYSVM aperture inside
243 	 * which the first part is vram and the second part is gart (covering
244 	 * system ram).
245 	 */
246 	u64			vram_start;
247 	u64			vram_end;
248 	/* FB region , it's same as local vram region in single GPU, in XGMI
249 	 * configuration, this region covers all GPUs in the same hive ,
250 	 * each GPU in the hive has the same view of this FB region .
251 	 * GPU0's vram starts at offset (0 * segment size) ,
252 	 * GPU1 starts at offset (1 * segment size), etc.
253 	 */
254 	u64			fb_start;
255 	u64			fb_end;
256 	unsigned		vram_width;
257 	u64			real_vram_size;
258 	int			vram_mtrr;
259 	u64                     mc_mask;
260 	const struct firmware   *fw;	/* MC firmware */
261 	uint32_t                fw_version;
262 	struct amdgpu_irq_src	vm_fault;
263 	uint32_t		vram_type;
264 	uint8_t			vram_vendor;
265 	uint32_t                srbm_soft_reset;
266 	bool			prt_warning;
267 	uint32_t		sdpif_register;
268 	/* apertures */
269 	u64			shared_aperture_start;
270 	u64			shared_aperture_end;
271 	u64			private_aperture_start;
272 	u64			private_aperture_end;
273 	/* protects concurrent invalidation */
274 	spinlock_t		invalidate_lock;
275 	bool			translate_further;
276 	struct kfd_vm_fault_info *vm_fault_info;
277 	atomic_t		vm_fault_info_updated;
278 
279 	struct amdgpu_gmc_fault	fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
280 	struct {
281 		uint64_t	idx:AMDGPU_GMC_FAULT_RING_ORDER;
282 	} fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
283 	uint64_t		last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
284 
285 	bool tmz_enabled;
286 	bool is_app_apu;
287 
288 	struct amdgpu_mem_partition_info *mem_partitions;
289 	uint8_t num_mem_partitions;
290 	const struct amdgpu_gmc_funcs	*gmc_funcs;
291 
292 	struct amdgpu_xgmi xgmi;
293 	struct amdgpu_irq_src	ecc_irq;
294 	int noretry;
295 
296 	uint32_t	vmid0_page_table_block_size;
297 	uint32_t	vmid0_page_table_depth;
298 	struct amdgpu_bo		*pdb0_bo;
299 	/* CPU kmapped address of pdb0*/
300 	void				*ptr_pdb0;
301 
302 	/* MALL size */
303 	u64 mall_size;
304 	uint32_t m_half_use;
305 
306 	/* number of UMC instances */
307 	int num_umc;
308 	/* mode2 save restore */
309 	u64 VM_L2_CNTL;
310 	u64 VM_L2_CNTL2;
311 	u64 VM_DUMMY_PAGE_FAULT_CNTL;
312 	u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
313 	u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
314 	u64 VM_L2_PROTECTION_FAULT_CNTL;
315 	u64 VM_L2_PROTECTION_FAULT_CNTL2;
316 	u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
317 	u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
318 	u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
319 	u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;
320 	u64 VM_DEBUG;
321 	u64 VM_L2_MM_GROUP_RT_CLASSES;
322 	u64 VM_L2_BANK_SELECT_RESERVED_CID;
323 	u64 VM_L2_BANK_SELECT_RESERVED_CID2;
324 	u64 VM_L2_CACHE_PARITY_CNTL;
325 	u64 VM_L2_IH_LOG_CNTL;
326 	u64 VM_CONTEXT_CNTL[16];
327 	u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];
328 	u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];
329 	u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];
330 	u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];
331 	u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];
332 	u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];
333 	u64 MC_VM_MX_L1_TLB_CNTL;
334 
335 	u64 noretry_flags;
336 };
337 
338 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
339 #define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub, inst) \
340 	((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
341 	((adev), (pasid), (type), (allhub), (inst)))
342 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
343 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
344 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
345 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
346 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
347 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags)	\
348 	(adev)->gmc.gmc_funcs->override_vm_pte_flags			\
349 		((adev), (vm), (addr), (pte_flags))
350 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
351 
352 /**
353  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
354  *
355  * @adev: amdgpu_device pointer
356  *
357  * Returns:
358  * True if full VRAM is visible through the BAR
359  */
360 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
361 {
362 	WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
363 
364 	return (gmc->real_vram_size == gmc->visible_vram_size);
365 }
366 
367 /**
368  * amdgpu_gmc_sign_extend - sign extend the given gmc address
369  *
370  * @addr: address to extend
371  */
372 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
373 {
374 	if (addr >= AMDGPU_GMC_HOLE_START)
375 		addr |= AMDGPU_GMC_HOLE_END;
376 
377 	return addr;
378 }
379 
380 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);
381 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
382 			       uint64_t *addr, uint64_t *flags);
383 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
384 				uint32_t gpu_page_idx, uint64_t addr,
385 				uint64_t flags);
386 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
387 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
388 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc);
389 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
390 			      u64 base);
391 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
392 			      struct amdgpu_gmc *mc);
393 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
394 			     struct amdgpu_gmc *mc);
395 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
396 			      struct amdgpu_ih_ring *ih, uint64_t addr,
397 			      uint16_t pasid, uint64_t timestamp);
398 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
399 				     uint16_t pasid);
400 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev);
401 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
402 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
403 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
404 
405 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
406 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev);
407 
408 extern void
409 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
410 			      bool enable);
411 
412 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
413 
414 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
415 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
416 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
417 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
418 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
419 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev);
420 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev);
421 
422 #endif
423