1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 33 /* VA hole for 48bit addresses on Vega10 */ 34 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 35 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 36 37 /* 38 * Hardware is programmed as if the hole doesn't exists with start and end 39 * address values. 40 * 41 * This mask is used to remove the upper 16bits of the VA and so come up with 42 * the linear addr value. 43 */ 44 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 45 46 /* 47 * Ring size as power of two for the log of recent faults. 48 */ 49 #define AMDGPU_GMC_FAULT_RING_ORDER 8 50 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 51 52 /* 53 * Hash size as power of two for the log of recent faults 54 */ 55 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 56 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 57 58 /* 59 * Number of IH timestamp ticks until a fault is considered handled 60 */ 61 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 62 63 struct firmware; 64 65 /* 66 * GMC page fault information 67 */ 68 struct amdgpu_gmc_fault { 69 uint64_t timestamp; 70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 71 uint64_t key:52; 72 }; 73 74 /* 75 * VMHUB structures, functions & helpers 76 */ 77 struct amdgpu_vmhub { 78 uint32_t ctx0_ptb_addr_lo32; 79 uint32_t ctx0_ptb_addr_hi32; 80 uint32_t vm_inv_eng0_sem; 81 uint32_t vm_inv_eng0_req; 82 uint32_t vm_inv_eng0_ack; 83 uint32_t vm_context0_cntl; 84 uint32_t vm_l2_pro_fault_status; 85 uint32_t vm_l2_pro_fault_cntl; 86 }; 87 88 /* 89 * GPU MC structures, functions & helpers 90 */ 91 struct amdgpu_gmc_funcs { 92 /* flush the vm tlb via mmio */ 93 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 94 uint32_t vmhub, uint32_t flush_type); 95 /* flush the vm tlb via ring */ 96 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 97 uint64_t pd_addr); 98 /* Change the VMID -> PASID mapping */ 99 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 100 unsigned pasid); 101 /* enable/disable PRT support */ 102 void (*set_prt)(struct amdgpu_device *adev, bool enable); 103 /* map mtype to hardware flags */ 104 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 105 /* get the pde for a given mc addr */ 106 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 107 u64 *dst, u64 *flags); 108 /* get the pte flags to use for a BO VA mapping */ 109 void (*get_vm_pte)(struct amdgpu_device *adev, 110 struct amdgpu_bo_va_mapping *mapping, 111 uint64_t *flags); 112 }; 113 114 struct amdgpu_xgmi { 115 /* from psp */ 116 u64 node_id; 117 u64 hive_id; 118 /* fixed per family */ 119 u64 node_segment_size; 120 /* physical node (0-3) */ 121 unsigned physical_node_id; 122 /* number of nodes (0-4) */ 123 unsigned num_physical_nodes; 124 /* gpu list in the same hive */ 125 struct list_head head; 126 bool supported; 127 struct ras_common_if *ras_if; 128 }; 129 130 struct amdgpu_gmc { 131 /* FB's physical address in MMIO space (for CPU to 132 * map FB). This is different compared to the agp/ 133 * gart/vram_start/end field as the later is from 134 * GPU's view and aper_base is from CPU's view. 135 */ 136 resource_size_t aper_size; 137 resource_size_t aper_base; 138 /* for some chips with <= 32MB we need to lie 139 * about vram size near mc fb location */ 140 u64 mc_vram_size; 141 u64 visible_vram_size; 142 /* AGP aperture start and end in MC address space 143 * Driver find a hole in the MC address space 144 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 145 * Under VMID0, logical address == MC address. AGP 146 * aperture maps to physical bus or IOVA addressed. 147 * AGP aperture is used to simulate FB in ZFB case. 148 * AGP aperture is also used for page table in system 149 * memory (mainly for APU). 150 * 151 */ 152 u64 agp_size; 153 u64 agp_start; 154 u64 agp_end; 155 /* GART aperture start and end in MC address space 156 * Driver find a hole in the MC address space 157 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 158 * registers 159 * Under VMID0, logical address inside GART aperture will 160 * be translated through gpuvm gart page table to access 161 * paged system memory 162 */ 163 u64 gart_size; 164 u64 gart_start; 165 u64 gart_end; 166 /* Frame buffer aperture of this GPU device. Different from 167 * fb_start (see below), this only covers the local GPU device. 168 * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios) 169 * and calculate vram_start of this local device by adding an 170 * offset inside the XGMI hive. 171 * Under VMID0, logical address == MC address 172 */ 173 u64 vram_start; 174 u64 vram_end; 175 /* FB region , it's same as local vram region in single GPU, in XGMI 176 * configuration, this region covers all GPUs in the same hive , 177 * each GPU in the hive has the same view of this FB region . 178 * GPU0's vram starts at offset (0 * segment size) , 179 * GPU1 starts at offset (1 * segment size), etc. 180 */ 181 u64 fb_start; 182 u64 fb_end; 183 unsigned vram_width; 184 u64 real_vram_size; 185 int vram_mtrr; 186 u64 mc_mask; 187 const struct firmware *fw; /* MC firmware */ 188 uint32_t fw_version; 189 struct amdgpu_irq_src vm_fault; 190 uint32_t vram_type; 191 uint8_t vram_vendor; 192 uint32_t srbm_soft_reset; 193 bool prt_warning; 194 uint64_t stolen_size; 195 /* apertures */ 196 u64 shared_aperture_start; 197 u64 shared_aperture_end; 198 u64 private_aperture_start; 199 u64 private_aperture_end; 200 /* protects concurrent invalidation */ 201 spinlock_t invalidate_lock; 202 bool translate_further; 203 struct kfd_vm_fault_info *vm_fault_info; 204 atomic_t vm_fault_info_updated; 205 206 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 207 struct { 208 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 209 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 210 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 211 212 const struct amdgpu_gmc_funcs *gmc_funcs; 213 214 struct amdgpu_xgmi xgmi; 215 struct amdgpu_irq_src ecc_irq; 216 }; 217 218 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) 219 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 220 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 221 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 222 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 223 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 224 225 /** 226 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 227 * 228 * @adev: amdgpu_device pointer 229 * 230 * Returns: 231 * True if full VRAM is visible through the BAR 232 */ 233 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 234 { 235 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 236 237 return (gmc->real_vram_size == gmc->visible_vram_size); 238 } 239 240 /** 241 * amdgpu_gmc_sign_extend - sign extend the given gmc address 242 * 243 * @addr: address to extend 244 */ 245 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 246 { 247 if (addr >= AMDGPU_GMC_HOLE_START) 248 addr |= AMDGPU_GMC_HOLE_END; 249 250 return addr; 251 } 252 253 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 254 uint64_t *addr, uint64_t *flags); 255 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 256 uint32_t gpu_page_idx, uint64_t addr, 257 uint64_t flags); 258 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 259 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 260 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 261 u64 base); 262 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 263 struct amdgpu_gmc *mc); 264 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 265 struct amdgpu_gmc *mc); 266 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 267 uint16_t pasid, uint64_t timestamp); 268 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 269 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 270 271 #endif 272